Hi,
> * Document more devices:
> - the video card is added by default;
> - so is the Ethernet adapter, apparently.
>
> The last part seems to clash with some of Gerd's comments,
> so I'm kinda puzzled.
Oh yes, the wonderful confusing world of default devices ;)
So, if you run qemu w
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PULL 000/107] ppc-for-2.9 queue 20170202
Message-id: 20170202051445.5735-1-da...@gibson.dropbear.id.au
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$
"Daniel P. Berrange" writes:
> On Wed, Feb 01, 2017 at 01:31:01PM +0100, Max Reitz wrote:
>> On 01.02.2017 13:28, Daniel P. Berrange wrote:
>> > On Wed, Feb 01, 2017 at 01:23:54PM +0100, Max Reitz wrote:
>> >> On 01.02.2017 13:16, Daniel P. Berrange wrote:
>> >>> On Wed, Feb 01, 2017 at 01:13:39P
Max Reitz writes:
> On 01.02.2017 13:28, Daniel P. Berrange wrote:
>> On Wed, Feb 01, 2017 at 01:23:54PM +0100, Max Reitz wrote:
>>> On 01.02.2017 13:16, Daniel P. Berrange wrote:
On Wed, Feb 01, 2017 at 01:13:39PM +0100, Max Reitz wrote:
> On 30.01.2017 19:37, Eric Blake wrote:
>> O
From: Thomas Huth
When running with KVM on POWER, we are registering a "family" CPU
type for the host CPU that we are running on. For example, on all
POWER8-compatible hosts, we register a "POWER8" CPU type, so that
you can always start QEMU with "-cpu POWER8" there, without the
need to know whet
Hi,
> - usb with usbredir 0.7.1
What kind of device do you assign to the guest?
> - guest windows 7 - renesas driver 2.1.36 or 2.1.39
ok.
> Where is the verfied windows driver that is compatible/tested with xhci code ?
Usually I test with the drivers shipped by the operating system, i.e.
lin
From: Nikunj A Dadhania
xststdcsp: VSX Scalar Test Data Class Single-Precision
xststdcdp: VSX Scalar Test Data Class Double-Precision
xststdcqp: VSX Scalar Test Data Class Quad-Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 66
From: "Michael S. Tsirkin"
We are switching BUILD_BUG_ON to verify that it's parameter is a
compile-time constant, and it turns out that some gcc versions
(specifically gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609) are
not smart enough to figure it out for expressions involving local
variab
This patch changes resetting strategy of the audio polling timer.
It does not change expiration time if the timer is already set.
This patch is needed to make this timer deterministic and to use execution
record/replay for audio devices.
audio_reset_timer is used in the function audio_vm_change_st
From: Nikunj A Dadhania
xvtstdcsp: VSX Vector Test Data Class Single-Precision
xvtstdcdp: VSX Vector Test Data Class Double-Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 40 +
target/ppc/hel
This patch adds recording and replaying audio data. Is saves synchronization
information for audio out and inputs from the microphone.
v2: removed unneeded whitespace change
Signed-off-by: Pavel Dovgalyuk
---
audio/audio.c|9 -
audio/audio.h|5 +++
audio/mixe
From: Suraj Jitindar Singh
pcr_supported is used to define the supported PCR values for a given
processor. A POWER9 processor can support 3.00, 2.07, 2.06 and 2.05
compatibility modes, thus we set this accordingly.
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: David Gibson
---
target/ppc
From: Laurent Vivier
This is a port to ppc of the i386 commit:
00f4d64 kvmclock: clock should count only if vm is running
We remove timebase_post_load function, and use the VM state
change handler to save and restore the guest_timebase (on stop
and continue).
We keep timebase_pre_save to re
From: Thomas Huth
hw_error() is for CPU related errors only (it dumps the CPU registers
and calls abort()!), so using error_report() is the better choice
of reporting an error in case we simply did not find a file.
Signed-off-by: Thomas Huth
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 6 +
From: Thomas Huth
There is no CPU model called "7447_v1.2" in our list, so the
"7447" alias should point to "7447_v1.1" instead. Let's also
remove the "codename" aliases that point to non-implemented
CPU models - they are really of no use here.
Signed-off-by: Thomas Huth
Signed-off-by: David Gi
From: Bharata B Rao
xscvqpsdz: VSX Scalar truncate & Convert Quad-Precision format to
Signed Doubleword format
xscvqpswz: VSX Scalar truncate & Convert Quad-Precision format to
Signed Word format
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by:
From: Suraj Jitindar Singh
The cp_abort instruction is used to remove the state of an in progress
copy paste sequence. POWER9 compilers add this in various places, such
as context switches which causes illegal instruction signals since we
don't yet implement this instruction.
Given there is no i
From: Nikunj A Dadhania
xvcvhpsp: VSX Vector Convert Half Precision to Single Precision
xvcvsphp: VSX Vector Convert Single Precision to Half Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 27 ++-
target
From: Nikunj A Dadhania
xvxexpsp: VSX Vector Extract Exponent Single Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 17 +
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 18 insertions(+)
diff --git
From: Jose Ricardo Ziviani
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 51 +++
From: Suraj Jitindar Singh
We were printing an unsigned value as a signed value, fix this.
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: David Gibson
---
target/ppc/mmu-hash64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/m
From: Bharata B Rao
xscvsdqp: VSX Scalar Convert Signed Doubleword format to
Quad-Precision format
xscvudqp: VSX Scalar Convert Unsigned Doubleword format to
Quad-Precision format
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
From: Jose Ricardo Ziviani
Implements 128-bit left shift and right shift as well as their
testcases. By design, shift silently mods by 128, so the caller is
responsible to assert the shift range if necessary.
Left shift sets the overflow flag if any non-zero digit is shifted out.
Examples:
uls
From: Nikunj A Dadhania
xsiexpqp: VSX Scalar Insert Exponent Quad Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 22 ++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 23 insertions(+)
diff --g
From: Suraj Jitindar Singh
We are calculating the authority mask register key value wrong.
The pte entry contains the key value with the two upper bits and the three
lower bits stored separately. We should use these two portions to get a 5
bit value, not or them together which will only give us
From: Jose Ricardo Ziviani
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/helper.h
From: Bharata B Rao
xsmulqp: VSX Scalar Multiply Quad-Precision
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 35 +++
target/ppc/helper.h | 1 +
target/ppc/t
From: Nikunj A Dadhania
xvxsigdp: VSX Vector Extract Significand Dual Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 40 +
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 41 inse
From: Suraj Jitindar Singh
It can be useful when debugging to print the LPCR value.
Thus we add the LPCR to the "info registers" output if the register had
been defined.
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: David Gibson
---
target/ppc/translate.c | 3 +++
1 file changed, 3 inse
From: Nikunj A Dadhania
xvxexpdp: VSX Vector Extract Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 17 +
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 18 insertions(+)
diff --git a
The PCI Expander Bridge (PXB) device is essentially a hack to allow
different PCIe devices to be assigned to different NUMA nodes on x86. Each
PXB is sort-of a separate PCI host bridge, except that its config space
is shared with the config space of the main PCI host bridge, rather than
being inde
From: Valentin Plotkin
Machines bamboo, e500 and virtex-ml507 assume a certain MMU model,
otherwise resulting in unpredictable behavior. Add apropriate checks
into *_init functions.
Signed-off-by: Valentin Plotkin
[regarding virtex parts]
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Igl
From: Nikunj A Dadhania
xviexpsp: VSX Vector Insert Exponent Single Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 26 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
2 files changed, 28 insertions(+)
d
From: Nikunj A Dadhania
xvxsigsp: VSX Vector Extract Significand Single Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 20
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c |
From: Nikunj A Dadhania
xsxexpqp: VSX Scalar Extract Exponent Quad Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 15 +++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 16 insertions(+)
diff --git a/t
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Signed-off-by: David Gibson
---
MAINTAINERS | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index e0be7bc..b1f4d9d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -671,10 +671,13 @@ F: hw/mis
From: Nikunj A Dadhania
xviexpdp: VSX Vector Insert Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 26 ++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 27 insertions(+)
diff
From: Bharata B Rao
xscmpoqp, xscmpuqp & xscmpexpqp were added before f128 field was
introduced in ppc_vsr_t. Now that we have it, use it instead of
generating the 128 bit float using two 64bit fields.
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
-
From: Thomas Huth
We do not support POWER1 CPUs in QEMU, so it does not make sense
to keep this stub around.
Signed-off-by: Thomas Huth
Signed-off-by: David Gibson
---
target/ppc/translate_init.c | 22 --
1 file changed, 22 deletions(-)
diff --git a/target/ppc/translate_i
Once a compatiblity mode is negotiated with the guest,
h_client_architecture_support() uses run_on_cpu() to update each CPU to
the new mode. We're going to want this logic somewhere else shortly,
so make a helper function to do this global update.
We put it in target-ppc/compat.c - it makes as mu
From: Bharata B Rao
xsdivqp: VSX Scalar Divide Quad-Precision
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 36
target/ppc/helper.h | 1 +
target/ppc/tr
From: Nikunj A Dadhania
xsiexpdp: VSX Scalar Insert Exponent Double Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 20
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 21 insertions(+)
diff --g
From: Bharata B Rao
xscvdpqp: VSX Scalar Convert Double-Precision format to
Quad-Precision format
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 45 +
target/ppc
From: Suraj Jitindar Singh
This logical PVR value now corresponds to ISA version 3.00 so rename it
accordingly.
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: David Gibson
---
target/ppc/cpu-models.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu-models
From: Jose Ricardo Ziviani
bcds.: Decimal shift. Given two registers vra and vrb, this instruction
shift the vrb value by vra bits into the result register.
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c
From: Jose Ricardo Ziviani
It is not possible to implement functions in host-utils.c for
architectures with quadwords because the guard is implemented in the
Makefile. This patch move the guard out of the Makefile to the
implementation file.
Signed-off-by: Jose Ricardo Ziviani
Reviewed-by: Eric
During boot, PAPR guests negotiate CPU model support with the
ibm,client-architecture-support mechanism. The logic to implement this in
qemu is very convoluted. This cleans it up to be cleaner, using the new
ppc_check_compat() call.
The new logic for choosing a compatibility mode is:
1. Usua
From: Jose Ricardo Ziviani
bcdsr.: Decimal shift and round. This instruction works like bcds.
however, when performing right shift, 1 will be added to the
result if the last digit was >= 5.
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/helper.h
From: Nikunj A Dadhania
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 8c8e3c5..77f68e9 100644
--- a/target/ppc/fpu_helper.c
+++
From: Bharata B Rao
xscvdphp: VSX Scalar round & Convert Double-Precision format to
Half-Precision format
xscvhpdp: VSX Scalar Convert Half-Precision format to
Double-Precision format
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
From: Jose Ricardo Ziviani
bcdus.: Decimal unsigned shift. This instruction works like bcds. but
considers only unsigned BCDs (no sign in least meaning 4 bits).
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/helper.h | 1 +
target/ppc/int_helpe
From: Thomas Huth
It is completely unused, thus it can be removed without problems.
Signed-off-by: Thomas Huth
Signed-off-by: David Gibson
---
hw/ppc/ppc.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 8945869..f9a4b51 100644
--- a/hw/ppc/ppc.c
++
From: Hervé Poussineau
Machine supports both Open Hack'Ware and OpenBIOS.
Open Hack'Ware is the default because OpenBIOS is currently unable to boot
PReP boot partitions or PReP kernels.
Signed-off-by: Hervé Poussineau
[dwg: Correct compile failure with KVM located by Thomas Huth]
Signed-off-by
From: Nikunj A Dadhania
xsxsigqp: VSX Scalar Extract Significand Quad Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 29 +
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 30 insertions(+
From: Jose Ricardo Ziviani
This commit fixes a warning in the code "(i * 2) ? .. : ..", which
should be better as "i ? .. : ..", and improves the BCD_DIG_BYTE
macro by placing parentheses around its argument to avoid possible
expansion issues like: BCD_DIG_BYTE(i + j).
Signed-off-by: Jose Ricard
From: Bharata B Rao
Since helper_compute_fprf() works on float64 argument, rename it
to helper_compute_fprf_float64(). Also use a macro to generate
helper_compute_fprf_float64() so that float128 version of the same
helper can be introduced easily later.
Signed-off-by: Bharata B Rao
Signed-off-b
From: Bharata B Rao
Currently float128_default_nan() returns 0x8000 in the
higher double word, but it should return 0x7FFF8000 which
is the correct higher double word for default qNAN on PowerPC.
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: D
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Reviewed-by: David Gibson
[dwg: Added CONFIG_RS6000_MC to ppc64 or it breaks testcases]
Signed-off-by: David Gibson
---
default-configs/ppc-softmmu.mak | 1 +
default-configs/ppc64-softmmu.mak | 1 +
hw/ppc/Makefile.objs
From: Bharata B Rao
xsaddqp: VSX Scalar Add Quad-Precision
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 36
target/ppc/helper.h | 1 +
target/ppc/inte
From: Nikunj A Dadhania
xsxsigdp: VSX Scalar Extract Significand Dual Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 29 +
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 30 insertions(+
From: Laurent Vivier
The test has been converted to use libqos, we can
now use it on ppc64. We also make the test fail on
all other architectures.
As libqos on ppc64 is not able to manage hotplug
and IRQ/MSI, we disable this part in the test on ppc64.
Signed-off-by: Laurent Vivier
[dwg: Make te
From: Hervé Poussineau
This device is a partial duplicate of System I/O device available in
hw/ppc/prep.c
This new one doesn't have all the Motorola-specific registers.
The old one should be deprecated and removed with the 'prep' machine.
Partial documentation available at
ftp://ftp.software.ib
From: Nikunj A Dadhania
xsxexpdp: VSX Scalar Extract Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 13 +
target/ppc/translate/vsx-ops.inc.c | 4
2 files changed, 17 insertions(+)
diff --git a/
From: Bharata B Rao
xscvqpdp: VSX Scalar round & Convert Quad-Precision format to
Double-Precision format
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 28
target/pp
From: Roman Kapl
If the DECAR register is set to 0, QEMU tries to reload the decrementer with
zero in an inifinite loop. According to PPC documentation, the decrementer is
triggered on 1->0 transition, so avoid reloading the decrementer if if is
already zero.
The problem does not manifest under
From: Nikunj A Dadhania
stxvll: Store VSX Vector Left-justified with Length
Vector (8-bit elements) in BE/LE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-
From: xiaoqiang zhao
Drop the old and empty SysBus init
Signed-off-by: xiaoqiang zhao
Signed-off-by: David Gibson
---
hw/ppc/spapr_vio.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index cc1e09c..8bfc5f9 100644
--- a/hw/ppc/spapr_vio.
From: Bharata B Rao
Use correct FP precision when setting FPRF in FP conversion helpers
instead of always assuming float64 precision.
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 4 ++--
target/ppc/internal.h | 1 +
From: Laurent Vivier
This will allow to use it with ppc64.
Signed-off-by: Laurent Vivier
Signed-off-by: David Gibson
---
tests/ivshmem-test.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/tests/ivshmem-test.c b/tests/ivshmem-test.c
index
From: xiaoqiang zhao
Drop the old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao
Signed-off-by: David Gibson
---
hw/ppc/ppce500_spin.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.
From: xiaoqiang zhao
Drop the old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao
Signed-off-by: David Gibson
---
hw/ppc/e500.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index cf8b122..792bd79
From: Bharata B Rao
Replace isden() by float64_is_zero_or_denormal() so that code in
helper_compute_fprf() can be reused to work with float128 argument.
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
target/ppc/fpu_hel
From: Nikunj A Dadhania
xxinsertw: VSX Vector Insert Word
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 25 +
target/ppc/translate/vsx-impl.inc.c | 5 +++--
target/ppc
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Signed-off-by: David Gibson
---
tests/libqos/pci-spapr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/libqos/pci-spapr.c b/tests/libqos/pci-spapr.c
index 1e5d015..2043f1e 100644
--- a/tests/libqos/pci-spapr.c
+
This rewrites the ppc_set_compat() function so that instead of open coding
the various compatibility modes, it reads the relevant data from a table.
This is a first step in consolidating the information on compatibility
modes scattered across the code into a single place.
It also makes one change
From: xiaoqiang zhao
* Drop the old SysBus init function and use instance_init
* Change mpc8xxx_gpio_reset to a DeviceClass::reset function
Signed-off-by: xiaoqiang zhao
Signed-off-by: David Gibson
---
hw/gpio/mpc8xxx.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(
To continue consolidation of compatibility mode information, this rewrites
the ppc_get_compat_smt_threads() function using the table of compatiblity
modes in target-ppc/compat.c.
It's not a direct replacement, the new ppc_compat_max_threads() function
has simpler semantics - it just returns the nu
From: Nikunj A Dadhania
stxvl: Store VSX Vector with Length
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bi
From: Nikunj A Dadhania
xxextractuw: VSX Vector Extract Unsigned Word
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 26 ++
target/ppc/translate/vsx-impl.inc.c | 30
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Signed-off-by: David Gibson
---
hw/ppc/prep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 054af1e..9fb89d3 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -339,13 +339,13 @@
From: Bharata B Rao
Use float64 argument instead of unit64_t in helper_compute_fprf()
This allows code in helper_compute_fprf() to be reused later to
work with float128 argument too.
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_
Current ppc_set_compat() will attempt to set any compatiblity mode
specified, regardless of whether it's available on the CPU. The caller is
expected to make sure it is setting a possible mode, which is awkwward
because most of the information to make that decision is at the CPU level.
This begin
Signed-off-by: David Gibson
Reviewed-by: Thomas Huth
Reviewed-by: Laurent Vivier
---
hw/ppc/spapr.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f2edbd0..a175609 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.
From: Thomas Huth
When passing through an USB storage device to a pseries guest, it
is currently not possible to automatically boot from the device
if the "bootindex" property has been specified, too (e.g. when using
"-device nec-usb-xhci -device usb-host,hostbus=1,hostaddr=2,bootindex=0"
at the
From: Laurent Vivier
Only enable for ppc64 in the Makefile, but added
code in the file to check cirrus card only on architectures
supporting it (alpha, mips, i386, x86_64).
Signed-off-by: Laurent Vivier
Reviewed-by: Thomas Huth
Reviewed-by: Greg Kurz
Tested-by: Greg Kurz
Signed-off-by: David
From: Bharata B Rao
xxperm: VSX Vector Permute
xxpermr: VSX Vector Permute Right-indexed
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 23 +++
target/ppc/helper.h | 2 +
From: Nikunj A Dadhania
lxvll: Load VSX Vector Left-justified with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Lo
From: Nikunj A Dadhania
lxvl: Load VSX Vector with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes r
From: Nikunj A Dadhania
xscpsgnqp: VSX Scalar Copy Sign Quad-Precision
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 12 +++-
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 12 insert
From: Jose Ricardo Ziviani
A function to check if all digits of a given BCD number is valid is
here presented because more instructions will need to reuse the
same code.
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/int_helper.c | 27 --
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Reviewed-by: Thomas Huth
Reviewed-by: Greg Kurz
Tested-by: Greg Kurz
Signed-off-by: David Gibson
---
tests/Makefile.include | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 33b4f88
The pseries machine type is a bit unusual in that it runs a paravirtualized
guest. The guest expects to interact with a hypervisor, and qemu
emulates the functions of that hypervisor directly, rather than executing
hypervisor code within the emulated system.
To implement this in TCG, we need to i
Currently the pseries machine has two paths for constructing CPUs. On
newer machine type versions, which support cpu hotplug, it constructs
cpu core objects, which in turn construct CPU threads. For older machine
versions it individually constructs the CPU threads.
This division is going to make
From: Nikunj A Dadhania
lxv: Load VSX Vector
lxvx: Load VSX Vector Indexed
Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Vector load results:
The 'cpu_version' field in PowerPCCPU is badly named. It's named after the
'cpu-version' device tree property where it is advertised, but that meaning
may not be obvious in most places it appears.
Worse, it doesn't even really correspond to that device tree property. The
property contains either
spapr_h_cas_compose_response() includes a cpu_update parameter which
controls whether it includes updated information on the CPUs in the device
tree fragment returned from the ibm,client-architecture-support (CAS) call.
Providing the updated information is essential when CAS has negotiated
compati
xsabsqp: VSX Scalar Absolute Quad-Precision
xsnabsqp: VSX Scalar Negative Absolute Quad-Precision
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 35 +++
target/ppc/translate/
From: Nikunj A Dadhania
xsnegqp: VSX Scalar Negate Quad-Precision
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 4
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/ppc/translate/vsx-i
From: Nikunj A Dadhania
stxsd: Store VSX Scalar Dword
stxssp: Store VSX Scalar SP
Moreover, DQ-Form/DS-FORM instructions shares the same primary
opcode(0x3D). For DQ-FORM bits 29:31 are used, for DS-FORM bits 30:31
are used. Common routine to decode primary opcode(0x3D) -
ds-form/dq-form instru
From: Nicholas Piggin
The H_SIGNAL_SYS_RESET hcall allows a guest CPU to raise a system reset
exception on CPUs within the same guest -- all CPUs, all-but-self, or a
specific CPU (including self).
This has not made its way to a PAPR release yet, but we have an hcall
number assigned.
H_SIGNAL_
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