Re: [Qemu-devel] [RFC PATCH v3 1/1] virtio crypto device specification: asymmetric crypto service

Hi, > > On Wednesday, January 18, 2017 10:04 AM, Gonglei (Arei) wrote: > > I update the virtio crypto spec to support non-session based crypto > > Operations and your asym service also needs change struct > > virtio_crypto_op_data_req which maybe cause the compatibility complaint > > with the pre

Re: [Qemu-devel] [RFC PATCH v3 1/1] virtio crypto device specification: asymmetric crypto service

On Wednesday, January 18, 2017 10:04 AM, Gonglei (Arei) wrote: > I update the virtio crypto spec to support non-session based crypto > Operations and your asym service also needs change struct > virtio_crypto_op_data_req which maybe cause the compatibility complaint > with the pre-existing code. >

Re: [Qemu-devel] Virtual Machine Generation ID

> On Jan 18, 2017, at 4:02 PM, Ben Warren wrote: > > Hi Michael, >> On Jan 17, 2017, at 9:45 AM, Michael S. Tsirkin wrote: >> >> On Mon, Jan 16, 2017 at 10:57:42AM -0800, Ben Warren wrote: >>> I think we have a misunderstanding here. I’m storing the VM >>> Generation ID __data__ (a GUID) in a

Re: [Qemu-devel] [PATCH RFC v3 14/14] intel_iommu: enable vfio devices

On Thu, Jan 19, 2017 at 06:44:06AM +, Liu, Yi L wrote: > > -Original Message- > > From: Qemu-devel [mailto:qemu-devel-bounces+yi.l.liu=intel@nongnu.org] > > On Behalf Of Tian, Kevin > > Sent: Wednesday, January 18, 2017 5:39 PM > > To: Peter Xu ; Jason Wang > > Cc: Lan, Tianyu ; Ra

Re: [Qemu-devel] [PATCH RFC v3 14/14] intel_iommu: enable vfio devices

On 2017年01月19日 14:44, Liu, Yi L wrote: -Original Message- From: Qemu-devel [mailto:qemu-devel-bounces+yi.l.liu=intel@nongnu.org] On Behalf Of Tian, Kevin Sent: Wednesday, January 18, 2017 5:39 PM To: Peter Xu ; Jason Wang Cc: Lan, Tianyu ; Raj, Ashok ; m...@redhat.com; jan.kis...@s

Re: [Qemu-devel] [PATCH RFC v3 14/14] intel_iommu: enable vfio devices

> -Original Message- > From: Qemu-devel [mailto:qemu-devel-bounces+yi.l.liu=intel@nongnu.org] > On Behalf Of Tian, Kevin > Sent: Wednesday, January 18, 2017 5:39 PM > To: Peter Xu ; Jason Wang > Cc: Lan, Tianyu ; Raj, Ashok ; > m...@redhat.com; jan.kis...@siemens.com; bd.a...@gmail.com

Re: [Qemu-devel] [PATCH RFC v3 14/14] intel_iommu: enable vfio devices

> From: Peter Xu [mailto:pet...@redhat.com] > Sent: Thursday, January 19, 2017 11:17 AM > > On Wed, Jan 18, 2017 at 09:38:55AM +, Tian, Kevin wrote: > > > From: Peter Xu [mailto:pet...@redhat.com] > > > Sent: Wednesday, January 18, 2017 4:46 PM > > > > > > On Wed, Jan 18, 2017 at 04:36:05PM +0

Re: [Qemu-devel] [PATCH RFC v11 0/4] vfio-pci: pass non-fatal error to guest

On 01/19/2017 05:43 AM, Alex Williamson wrote: > On Sat, 31 Dec 2016 17:13:04 +0800 > How can you know if he other function was affected if you don't even > have a cable connected? Will try ask for another cable for the other function. > How is testing on something that doesn't seem > to work

Re: [Qemu-devel] [PATCH RFC v11 0/4] vfio-pci: pass non-fatal error to guest

On 01/19/2017 05:43 AM, Alex Williamson wrote: > On Sat, 31 Dec 2016 17:13:04 +0800 > Cao jin wrote: > >> As previous discussion suggest, we could take a step back to handle non-fatal >> error first, this will make this patchset much more thinner, because we could >> drop all the configuration

[Qemu-devel] [RFC PATCH v0] softfloat: Add round-to-odd rounding mode

Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-add rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If Z can be represented exactly in the target form

Re: [Qemu-devel] [PATCH RFC v3 14/14] intel_iommu: enable vfio devices

On 2017年01月19日 11:32, Peter Xu wrote: On Wed, Jan 18, 2017 at 06:06:57PM +0800, Jason Wang wrote: [...] So I think we should implement DSI and GLOBAL for vfio in this case. We can first try to implement it through current VFIO API which can accepts a range of iova. If not possible, let's dis

Re: [Qemu-devel] [PULL 08/41] intel_iommu: support device iotlb descriptor

On 2017年01月19日 11:28, Peter Xu wrote: On Thu, Jan 19, 2017 at 10:50:59AM +0800, Jason Wang wrote: [...] +static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ +VTDAddressSpace *vtd_dev_as; +IOMMUTLBEntry entr

Re: [Qemu-devel] [PATCH RFC v3 14/14] intel_iommu: enable vfio devices

On Wed, Jan 18, 2017 at 06:06:57PM +0800, Jason Wang wrote: [...] > So I think we should implement DSI and GLOBAL for vfio in this case. We can > first try to implement it through current VFIO API which can accepts a range > of iova. If not possible, let's discuss for other possible solutions. D

Re: [Qemu-devel] [PULL 08/41] intel_iommu: support device iotlb descriptor

On 2017年01月19日 10:50, Jason Wang wrote: On 2017年01月18日 20:19, Paolo Bonzini wrote: On 10/01/2017 06:39, Michael S. Tsirkin wrote: From: Jason Wang This patch enables device IOTLB support for intel iommu. The major work is to implement QI device IOTLB descriptor processing and notify the

Re: [Qemu-devel] [PULL 08/41] intel_iommu: support device iotlb descriptor

On Thu, Jan 19, 2017 at 10:50:59AM +0800, Jason Wang wrote: [...] > >>+static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s, > >>+ VTDInvDesc *inv_desc) > >>+{ > >>+VTDAddressSpace *vtd_dev_as; > >>+IOMMUTLBEntry entry; > >>+struct VTDB

Re: [Qemu-devel] [PATCH RFC v3 14/14] intel_iommu: enable vfio devices

On Wed, Jan 18, 2017 at 09:38:55AM +, Tian, Kevin wrote: > > From: Peter Xu [mailto:pet...@redhat.com] > > Sent: Wednesday, January 18, 2017 4:46 PM > > > > On Wed, Jan 18, 2017 at 04:36:05PM +0800, Jason Wang wrote: > > > > > > > > > On 2017年01月18日 16:11, Peter Xu wrote: > > > >On Wed, Jan 18

Re: [Qemu-devel] [PATCH] virtio: force VIRTIO_F_IOMMU_PLATFORM

On 2017年01月19日 01:50, Michael S. Tsirkin wrote: On Wed, Jan 18, 2017 at 10:42:48AM +0800, Jason Wang wrote: On 2017年01月17日 22:44, Michael S. Tsirkin wrote: On Tue, Jan 17, 2017 at 12:01:00PM +0800, Jason Wang wrote: We allow vhost to clear VIRITO_F_IOMMU_PLATFORM which is wrong since VIRTIO

Re: [Qemu-devel] [PATCH v2] vfio/pci: Support error recovery

On 01/19/2017 05:32 AM, Alex Williamson wrote: > On Tue, 10 Jan 2017 17:11:01 +0200 > "Michael S. Tsirkin" wrote: > >> On Tue, Jan 10, 2017 at 07:46:17PM +0800, Cao jin wrote: >>> >>> >>> On 01/10/2017 07:04 AM, Michael S. Tsirkin wrote: On Sat, Dec 31, 2016 at 05:15:36PM +0800, Cao jin

Re: [Qemu-devel] [PULL 08/41] intel_iommu: support device iotlb descriptor

On 2017年01月18日 20:19, Paolo Bonzini wrote: On 10/01/2017 06:39, Michael S. Tsirkin wrote: From: Jason Wang This patch enables device IOTLB support for intel iommu. The major work is to implement QI device IOTLB descriptor processing and notify the device through iommu notifier. Cc: Paolo B

Re: [Qemu-devel] [PATCH RFC v2 1/6] docs/block-replication: Add description for shared-disk case

On 2017/1/13 21:41, Stefan Hajnoczi wrote: On Mon, Dec 05, 2016 at 04:34:59PM +0800, zhanghailiang wrote: +Issue qmp command: + { 'execute': 'blockdev-add', +'arguments': { +'driver': 'replication', +'node-name': 'rep', +'mode': 'primary', +'shared-disk-id':

Re: [Qemu-devel] [PATCH RFC v2 02/12] vfio: linux-headers update for vfio-ccw

* Alex Williamson [2017-01-18 13:43:32 -0700]: > On Wed, 18 Jan 2017 13:41:47 +0100 > Cornelia Huck wrote: > > > On Wed, 18 Jan 2017 10:51:17 +0800 > > Dong Jia Shi wrote: > > > > > * Alex Williamson [2017-01-17 14:51:42 > > > -0700]: > > > > > > > On Thu, 12 Jan 2017 08:25:03 +0100 > >

Re: [Qemu-devel] [PATCH v6 kernel 3/5] virtio-balloon: speed up inflate/deflate process

> On Wed, Jan 18, 2017 at 04:56:58AM +, Li, Liang Z wrote: > > > > - virtqueue_add_outbuf(vq, &sg, 1, vb, GFP_KERNEL); > > > > - virtqueue_kick(vq); > > > > +static void do_set_resp_bitmap(struct virtio_balloon *vb, > > > > + unsigned long base_pfn, int pages) > > > >

Re: [Qemu-devel] [virtio-dev] RE: [virtio-dev] Re: [PATCH v15 0/2] virtio-crypto: virtio crypto device specification

> > On 01/17/2017 03:49 AM, Gonglei (Arei) wrote: > > Hi Halil, > > > >> > >> On 01/16/2017 01:43 PM, Gonglei (Arei) wrote: > >>> Hi Michael and others, > >>> > >>> I'd like to redefine struct virtio_crypto_op_data_req is as below: > >>> > >>> struct virtio_crypto_op_data_req { > >>> struct vi

Re: [Qemu-devel] [virtio-dev] Re: [PATCH v6 kernel 2/5] virtio-balloon: define new feature bit and head struct

> > > > > > Signed-off-by: Liang Li > > > > > > Cc: Michael S. Tsirkin > > > > > > Cc: Paolo Bonzini > > > > > > Cc: Cornelia Huck > > > > > > Cc: Amit Shah > > > > > > Cc: Dave Hansen > > > > > > Cc: Andrea Arcangeli > > > > > > Cc: David Hildenbrand > > > > > > --- > > > > > > include/ua

Re: [Qemu-devel] [PATCH v3] hw/core/null-machine: Add the possibility to instantiate a CPU and RAM

On Wed, Jan 18, 2017 at 10:56 AM, Thomas Huth wrote: > On 18.01.2017 18:57, Alistair Francis wrote: >> On Wed, Jan 18, 2017 at 4:44 AM, Thomas Huth wrote: >>> Sometimes it is useful to have just a machine with CPU and RAM, without >>> any further hardware in it, e.g. if you just want to do some i

[Qemu-devel] [Bug 1256432] Re: qemu mingw 32bit windows crash

Oh sorry this has been working fine consider this resolved. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1256432 Title: qemu mingw 32bit windows crash Status in QEMU: Incomplete Bug descriptio

Re: [Qemu-devel] Virtual Machine Generation ID

Hi Michael, > On Jan 17, 2017, at 9:45 AM, Michael S. Tsirkin wrote: > > On Mon, Jan 16, 2017 at 10:57:42AM -0800, Ben Warren wrote: >> I think we have a misunderstanding here. I’m storing the VM >> Generation ID __data__ (a GUID) in a fw_cfg blob, not the address. > > Yes, I think I gathered t

[Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine

Remove the Niagara stub implementation from sun4u.c and add a machine, compatible with Legion simulator from the OpenSPARC T1 project. The machine uses the firmware supplied with the OpenSPARC T1 project, http://download.oracle.com/technetwork/systems/opensparc/OpenSPARCT1_Arch.1.5.tar.bz2 in the

[Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c

Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- hw/sparc64/Makefile.objs | 1 + hw/sparc64/sparc64.c | 378 + hw/sparc64/sun4u.c | 348 + hw/timer/sun4v-rtc.c | 2 +-

[Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC

Signed-off-by: Artyom Tarasenko --- MAINTAINERS | 6 +++ hw/timer/Makefile.objs | 2 + hw/timer/sun4v-rtc.c | 102 +++ include/hw/timer/sun4v-rtc.h | 1 + 4 files changed, 111 insertions(+) create mode 100644 hw/timer/s

[Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs

In OpenSPARC T1+ TWINX ASIs in store instructions are aliased with Block Initializing Store ASIs. "UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them in the chapter "5.9 Block Initializing Store ASIs" Integer stores of all sizes are allowed with these ASIs. Signed-off-by: Artyom Ta

[Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers

Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.h | 2 + target/sparc/ldst_helper.c | 124 + 2 files changed, 104 insertions(+), 22 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index c92bd25..9e9b22a 100644 --- a/tar

[Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21)

Signed-off-by: Artyom Tarasenko --- target/sparc/ldst_helper.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 4f55388..c69167e 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper

[Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode

Signed-off-by: Artyom Tarasenko --- target/sparc/ldst_helper.c | 32 ++-- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 2e6439a..ade4fb0 100644 --- a/target/sparc/ldst_helper.c +++ b/target

[Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu

Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- target/sparc/mmu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index fa70dc0..8b4664d 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @

[Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register

Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.c | 13 ++--- target/sparc/cpu.h | 2 ++ target/sparc/helper.h | 1 + target/sparc/int64_helper.c | 6 ++ target/sparc/translate.c| 3 +-- target/sparc/win_helper.c | 40

[Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register

Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- target/sparc/ldst_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index ade4fb0..d3747cf 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.

[Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs

Signed-off-by: Artyom Tarasenko --- linux-user/main.c | 2 +- target/sparc/cpu.h | 48 +- target/sparc/ldst_helper.c | 8 target/sparc/machine.c | 4 ++-- 4 files changed, 25 insertions(+), 37 deletions(-) diff --git a/

[Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions

Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- target/sparc/translate.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a40c974..399a8ac 100644 --- a/target/sparc/translate.c +++ b/target/spa

[Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs

Signed-off-by: Artyom Tarasenko --- target/sparc/ldst_helper.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index d4eee33..4f55388 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -21

[Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode

Please note that QEMU doesn't impelement Real->Physical address translation. The "Real Address" is always the "Physical Address". Suggested-by: Richard Henderson Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.h | 7 +++ target/sparc/translate.c | 2 +- 2 files changed, 4 inserti

[Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left

Implement the behavior described in the chapter 13.9.11 of UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005: "If a TLB Data-In replacement is attempted with all TLB entries locked and valid, the last TLB entry (entry 63) is replaced." Signed-off-by: Artyom Tarasenko --- target/spar

[Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode

As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005, outstanding disrupting exceptions that are destined for privileged mode can only cause a trap when the virtual processor is in nonprivileged or privileged mode and PSTATE.ie = 1. At all other times, they are held pending. Signed-o

[Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages

Signed-off-by: Artyom Tarasenko --- target/sparc/mmu_helper.c | 18 +- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 044e88c..fa70dc0 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c

[Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines

Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.h | 4 1 file changed, 4 insertions(+) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4c4c159..f65d8b5 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -336,6 +336,10 @@ enum { #define TTE_PGSIZE_UA2005(tte) ((

[Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode

Accordinf to UA2005, 9.3.3 "Address Space Identifiers", "In hyperprivileged mode, all instruction fetches and loads and stores with implicit ASIs use a physical address, regardless of the value of TL". Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.h | 4 ++-- target/sparc/translat

[Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE

Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- target/sparc/ldst_helper.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 20e202b..7a134b3 100644 --- a/target/sparc/ldst_helper.c +++ b/targ

[Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines

Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.h | 17 + 1 file changed, 17 insertions(+) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 10c9ac6..4c4c159 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -304,19 +304,36 @@ enum { #define TTE_W_OK_BIT

[Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer

Signed-off-by: Artyom Tarasenko --- target/sparc/ldst_helper.c | 51 ++ 1 file changed, 15 insertions(+), 36 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index aa6f77d..d4eee33 100644 --- a/target/sparc/ldst_helper.

[Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR

Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- target/sparc/translate.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 729f4e2..8902e44 100644 --- a/target/sparc/translate.c +++ b/target/sparc/transla

[Qemu-devel] [PULL 00/30] target-sparc sun4v support

58004df0: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-01-16' into staging (2017-01-17 13:53:50 +) are available in the git repository at: https://github.com/artyom-tarasenko/qemu/ tags/pull-sun4v-20170118 for you to fetch changes up to a2664ca0eced57dfc9f261

[Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers

Signed-off-by: Artyom Tarasenko --- target/sparc/asi.h | 1 + target/sparc/cpu.h | 1 + target/sparc/ldst_helper.c | 24 3 files changed, 26 insertions(+) diff --git a/target/sparc/asi.h b/target/sparc/asi.h index c9a1849..d8d6284 100644 --- a/target/sp

[Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps

Signed-off-by: Artyom Tarasenko --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 399a8ac..1099976 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3298,7 +3298,7 @@ st

[Qemu-devel] [PULL 02/30] target-sparc: store cpu super- and hypervisor flags in TB

Suggested-by: Richard Henderson Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.h | 17 + target/sparc/translate.c | 24 +++- 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index e815a19..1e65

[Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode

while IMMU/DMMU is disabled - ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor - signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.h | 2 ++ target/sparc/ldst_helper.c | 15 +++

[Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps

Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.h | 1 + target/sparc/int64_helper.c | 37 - target/sparc/win_helper.c | 6 ++ 3 files changed, 39 insertions(+), 5 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 00

[Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers

Use explicit register pointers while accessing D/I-MMU registers. Call cpu_unassigned_access on access to missing registers. Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- target/sparc/cpu.h | 4 +++ target/sparc/ldst_helper.c | 66 ++

Re: [Qemu-devel] [PATCH V4 1/7] nios2: Add disas entries

On 01/18/2017 02:01 PM, Marek Vasut wrote: Add nios2 disassembler support. This patch is composed from binutils files from commit "Opcodes and assembler support for Nios II R2". The files from binutils used in this patch are: include/opcode/nios2.h include/opcode/nios2r1.h include/op

Re: [Qemu-devel] [PATCH RFC v11 4/4] vfio: add 'aer' property to expose aercap

On Sat, 31 Dec 2016 17:13:08 +0800 Cao jin wrote: > From: Chen Fan > > Add 'aer' property, let user choose whether expose the aer capability > or not. But that's not what it does, it only controls the behavior in response to non-fatal errors, the capability is exposed regardless. > Should dis

Re: [Qemu-devel] [PATCH RFC v11 3/4] vfio-pci: pass the aer error to guest

On Sat, 31 Dec 2016 17:13:07 +0800 Cao jin wrote: > From: Chen Fan > > When physical device has uncorrectable error hanppened, the vfio_pci > driver will signal the uncorrectable error status register value to > corresponding QEMU's vfio-pci device via the eventfd registered by this > device, t

Re: [Qemu-devel] [PATCH RFC v11 2/4] vfio: new function to init aer cap for vfio device

On Sat, 31 Dec 2016 17:13:06 +0800 Cao jin wrote: > From: Chen Fan > > Introduce new function to initilize AER capability registers > for vfio-pci device. > > Signed-off-by: Chen Fan > Signed-off-by: Dou Liyang > Signed-off-by: Cao jin > --- > hw/vfio/pci.c | 87 >

Re: [Qemu-devel] [PATCH V9 2/7] nios2: Add architecture emulation support

On 01/18/2017 08:33 PM, Richard Henderson wrote: > On 01/16/2017 04:44 PM, Marek Vasut wrote: >> +TCGv_i32 tmp = tcg_const_i32(instr.imm5 + 32); >> +gen_helper_mmu_write(dc->cpu_env, tmp, load_gpr(dc, instr.a)); >> +tcg_temp_free_i32(tmp); >> +#endif >> +break; >> +

Re: [Qemu-devel] [PATCH v2 5/6] qmp/hmp: add set-vm-generation-id commands

> On Jan 18, 2017, at 12:55 AM, Igor Mammedov wrote: > > On Mon, 16 Jan 2017 11:20:57 -0800 > b...@skyportsystems.com wrote: > >> From: Igor Mammedov >> >> Add set-vm-generation-id command to set Virtual Machine >> Generation ID counter. >> >> QMP command exa

[Qemu-devel] [PATCH V4 1/7] nios2: Add disas entries

Add nios2 disassembler support. This patch is composed from binutils files from commit "Opcodes and assembler support for Nios II R2". The files from binutils used in this patch are: include/opcode/nios2.h include/opcode/nios2r1.h include/opcode/nios2r2.h opcodes/nios2-opc.c op

Re: [Qemu-devel] [PATCH V5 7/7] nios2: Add support for Nios-II R1

On 01/18/2017 08:35 PM, Richard Henderson wrote: > On 01/16/2017 04:44 PM, Marek Vasut wrote: >> +F: target-nios2/ > > Filename change. > > r~ OK -- Best regards, Marek Vasut

[Qemu-devel] [PATCH V10 2/7] nios2: Add architecture emulation support

From: Chris Wulff Add support for emulating Altera NiosII R1 architecture into qemu. This patch is based on previous work by Chris Wulff from 2012 and updated to latest mainline QEMU. Signed-off-by: Marek Vasut Cc: Chris Wulff Cc: Jeff Da Silva Cc: Ley Foon Tan Cc: Sandra Loosemore Cc: Yves

[Qemu-devel] [PATCH V6 7/7] nios2: Add support for Nios-II R1

Add remaining bits of the Altera NiosII R1 support into qemu, which is documentation, MAINTAINERS file entry, configure bits, arch_init and configuration files for both linux-user (userland binaries) and softmmu (hardware emulation). Signed-off-by: Marek Vasut Cc: Chris Wulff Cc: Jeff Da Silva

[Qemu-devel] [PATCH V6 6/7] nios2: Add Altera 10M50 GHRD emulation

Add the Altera 10M50 Nios2 GHRD model. This allows emulating the 10M50 development kit with the Nios2 GHRD loaded in the FPGA. It is possible to boot Linux kernel and run userspace, thus far only from initrd as storage support is not yet implemented. Signed-off-by: Marek Vasut Cc: Chris Wulff Cc

[Qemu-devel] [PATCH V5 5/7] nios2: Add periodic timer emulation

From: Chris Wulff Add the Altera timer model. Signed-off-by: Marek Vasut Cc: Chris Wulff Cc: Jeff Da Silva Cc: Ley Foon Tan Cc: Sandra Loosemore Cc: Yves Vandervennet Cc: Alexander Graf Cc: Richard Henderson Reviewed-by: Alexander Graf --- V3: Checkpatch cleanup V4: Rebase on top of qem

[Qemu-devel] [PATCH V5 3/7] nios2: Add usermode binaries emulation

Add missing bits for qemu-user required for emulating Altera Nios2 userspace binaries. Signed-off-by: Marek Vasut Cc: Chris Wulff Cc: Jeff Da Silva Cc: Ley Foon Tan Cc: Sandra Loosemore Cc: Yves Vandervennet Cc: Alexander Graf Cc: Richard Henderson Reviewed-by: Alexander Graf --- V3: Chec

[Qemu-devel] [PATCH 0/7] Nios2 architecture support

This patchset adds support for new Nios2 architecture as well as the initial set of models for hardware blocks and emulation of the Altera 10M50 GHRD devkit. Cc: Chris Wulff Cc: Jeff Da Silva Cc: Ley Foon Tan Cc: Sandra Loosemore Cc: Yves Vandervennet Cc: Alexander Graf Cc: Richard Henderson

[Qemu-devel] [PATCH V5 4/7] nios2: Add IIC interrupt controller emulation

From: Chris Wulff Add the Altera Nios2 internal interrupt controller model. Signed-off-by: Marek Vasut Cc: Chris Wulff Cc: Jeff Da Silva Cc: Ley Foon Tan Cc: Sandra Loosemore Cc: Yves Vandervennet Cc: Alexander Graf Cc: Richard Henderson Reviewed-by: Alexander Graf --- V3: Checkpatch cl

Re: [Qemu-devel] [PATCH v2 2/4] compiler: drop ; after BUILD_BUG_ON

On 18 January 2017 at 21:23, Michael S. Tsirkin wrote: > On Wed, Jan 18, 2017 at 11:16:07PM +0200, Michael S. Tsirkin wrote: >> On Wed, Jan 18, 2017 at 09:04:03PM +, Peter Maydell wrote: >> > On 18 January 2017 at 20:55, Michael S. Tsirkin wrote: >> > > All users include the trailing ;, let's

Re: [Qemu-devel] [PATCH RFC v11 0/4] vfio-pci: pass non-fatal error to guest

On Sat, 31 Dec 2016 17:13:04 +0800 Cao jin wrote: > As previous discussion suggest, we could take a step back to handle non-fatal > error first, this will make this patchset much more thinner, because we could > drop all the configuration restriction related patches. > > FYI: patch 1 has been ch

Re: [Qemu-devel] [PATCH 0/7] target-m68k: implement 680x0 FPU

On 01/18/2017 01:05 PM, Laurent Vivier wrote: This series modifies the original ColdFire FPU implementation to use floatx80 instead of float64 internally as this is the native datatype for 680x0. I didn't keep the float64 type for ColdFire, but if someone thinks it's required I can update this se

Re: [Qemu-devel] [PATCH v2] vfio/pci: Support error recovery

On Tue, 10 Jan 2017 17:11:01 +0200 "Michael S. Tsirkin" wrote: > On Tue, Jan 10, 2017 at 07:46:17PM +0800, Cao jin wrote: > > > > > > On 01/10/2017 07:04 AM, Michael S. Tsirkin wrote: > > > On Sat, Dec 31, 2016 at 05:15:36PM +0800, Cao jin wrote: > > >> Support serious device error recovery

Re: [Qemu-devel] [PATCH v2 2/4] compiler: drop ; after BUILD_BUG_ON

On Wed, Jan 18, 2017 at 11:16:07PM +0200, Michael S. Tsirkin wrote: > On Wed, Jan 18, 2017 at 09:04:03PM +, Peter Maydell wrote: > > On 18 January 2017 at 20:55, Michael S. Tsirkin wrote: > > > All users include the trailing ;, let's require that > > > so that uses such as if (a) QEMU_BUILD_BU

Re: [Qemu-devel] [PATCH 0/7] target-m68k: implement 680x0 FPU

Hi, Your series seems to have some coding style problems. See output below for more information: Message-id: 1484773521-16530-1-git-send-email-laur...@vivier.eu Subject: [Qemu-devel] [PATCH 0/7] target-m68k: implement 680x0 FPU Type: series === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 to

[Qemu-devel] [PATCH 4/7] target-m68k: use floatx80 internally

Coldfire uses float64, but 680x0 use floatx80. This patch introduces the use of floatx80 internally and enable FPU for 680x0. Signed-off-by: Laurent Vivier --- configure| 2 +- gdb-xml/m68k-fp.xml | 21 ++ target/m68k/cpu.c| 13 +- target/m68k/cpu.h| 74

Re: [Qemu-devel] [PATCH v2 2/4] compiler: drop ; after BUILD_BUG_ON

On Wed, Jan 18, 2017 at 09:04:03PM +, Peter Maydell wrote: > On 18 January 2017 at 20:55, Michael S. Tsirkin wrote: > > All users include the trailing ;, let's require that > > so that uses such as if (a) QEMU_BUILD_BUG_ON(); do not > > produce unexpected results. > > When would it ever make

[Qemu-devel] [PATCH 7/7] target-m68k: implements more FPU instructions

Add fmovecr, fsinh, flognp1, ftanh, fatan, fasin, fatanh, fsin, ftan, fetox, ftwotox, ftentox, flogn, flog10, facos, fcos, fgetexp, fgetman, fmod, fsgldiv, fscale, fsglmul, sin, cos, frestore, fsave. Signed-off-by: Laurent Vivier --- target/m68k/cpu.h| 1 + target/m68k/fpu_helper.c | 3

[Qemu-devel] [PATCH 5/7] target-m68k: add fmovem

Signed-off-by: Laurent Vivier --- target/m68k/fpu_helper.c | 6 +++ target/m68k/helper.h | 1 + target/m68k/translate.c | 99 +++- 3 files changed, 80 insertions(+), 26 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.

Re: [Qemu-devel] [PATCH v2 0/4] virtio: ARRAY_SIZE fixups

Hi, Your series seems to have some coding style problems. See output below for more information: Message-id: 1484772931-16272-1-git-send-email-...@redhat.com Subject: [Qemu-devel] [PATCH v2 0/4] virtio: ARRAY_SIZE fixups Type: series === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(g

[Qemu-devel] [PATCH 2/7] target-m68k: define ext_opsize

Signed-off-by: Laurent Vivier --- target/m68k/translate.c | 43 --- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 9f60fbc..d9ba735 100644 --- a/target/m68k/translate.c +++ b/target/m6

[Qemu-devel] [PATCH 6/7] target-m68k: introduce fscc.

use DisasCompare with FPU conditions in fscc and fbcc. Signed-off-by: Laurent Vivier --- target/m68k/translate.c | 228 1 file changed, 153 insertions(+), 75 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 49c0b0

[Qemu-devel] [PATCH 3/7] softfloat: define 680x0 specific values

Signed-off-by: Laurent Vivier --- fpu/softfloat-specialize.h | 30 +++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index f5aed72..8bd3fa9 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softflo

Re: [Qemu-devel] [PATCH v2 2/4] compiler: drop ; after BUILD_BUG_ON

On 18 January 2017 at 20:55, Michael S. Tsirkin wrote: > All users include the trailing ;, let's require that > so that uses such as if (a) QEMU_BUILD_BUG_ON(); do not > produce unexpected results. When would it ever make sense for a build-time assert to be the only thing inside a runtime conditi

[Qemu-devel] [PATCH 1/7] target-m68k: move FPU helpers to fpu_helper.c

Signed-off-by: Laurent Vivier --- target/m68k/Makefile.objs | 2 +- target/m68k/fpu_helper.c | 112 ++ target/m68k/helper.c | 88 3 files changed, 113 insertions(+), 89 deletions(-) create mode 100644 targe

[Qemu-devel] [PATCH 0/7] target-m68k: implement 680x0 FPU

This series modifies the original ColdFire FPU implementation to use floatx80 instead of float64 internally as this is the native datatype for 680x0. I didn't keep the float64 type for ColdFire, but if someone thinks it's required I can update this series in this way. The series also adds the FPU

[Qemu-devel] [PATCH v2 4/4] ARRAY_SIZE: check that argument is an array

It's a familiar pattern: some code uses ARRAY_SIZE, then refactoring changes the argument from an array to a pointer to a dynamically allocated buffer. Code keeps compiling but any ARRAY_SIZE calls now return the size of the pointer divided by element size. Let's add build time checks to ARRAY_SI

[Qemu-devel] [PATCH v2 2/4] compiler: drop ; after BUILD_BUG_ON

All users include the trailing ;, let's require that so that uses such as if (a) QEMU_BUILD_BUG_ON(); do not produce unexpected results. Not a huge problem for QEMU since our style requires the use of {} but seems cleaner nevertheless. Signed-off-by: Michael S. Tsirkin --- include/qemu/compiler

[Qemu-devel] [PATCH v2 3/4] compiler: expression version of QEMU_BUILD_BUG_ON

QEMU_BUILD_BUG_ON uses a typedef in order to be safe to use outside functions, but sometimes it's useful to have a version that can be used within an expression. Following what Linux does, introduce QEMU_BUILD_BUG_ON_ZERO that return zero after checking condition at build time. Signed-off-by: Mich

[Qemu-devel] [PATCH v2 0/4] virtio: ARRAY_SIZE fixups

Turns out virtio kept using ARRAY_SIZE on fields which stopped being arrays, this was noticed by a coverity scan. Fix this up, and fix up the ARRAY_SIZE macro so that this bug does not reappear in any other place. Michael S. Tsirkin (4): virtio: fix up max size checks compiler: drop ; after BU

[Qemu-devel] [PATCH v2 1/4] virtio: fix up max size checks

Coverity reports that ARRAY_SIZE(elem->out_sg) (and all the others too) is wrong because elem->out_sg is a pointer. However, the check is not in the right place and the max_size argument of virtqueue_map_iovec can be removed. The check on in_num/out_num should be moved to qemu_get_virtqueue_eleme

Re: [Qemu-devel] [PATCH 0/4] virtio: ARRAY_SIZE fixups

On Wed, Jan 18, 2017 at 12:40:50PM -0800, no-re...@patchew.org wrote: > Hi, > > Your series seems to have some coding style problems. See output below for > more information: Not sure we really do care as this matches existing code, but I'll fix it up. > Message-id: 1484771412-28024-1-git-send-

Re: [Qemu-devel] [PATCH] virtio: fix up max size checks

On Wed, Jan 18, 2017 at 11:42:57AM -0800, no-re...@patchew.org wrote: > Hi, > > Your series failed automatic build test. Posted a wrong patch. Pls ignore, will repost. > Please find the testing commands and > their output below. If you have docker installed, you can probably reproduce > it > lo

Re: [Qemu-devel] [PATCH RFC v2 02/12] vfio: linux-headers update for vfio-ccw

On Wed, 18 Jan 2017 13:41:47 +0100 Cornelia Huck wrote: > On Wed, 18 Jan 2017 10:51:17 +0800 > Dong Jia Shi wrote: > > > * Alex Williamson [2017-01-17 14:51:42 -0700]: > > > > > On Thu, 12 Jan 2017 08:25:03 +0100 > > > Dong Jia Shi wrote: > > > > > > > From: Xiao Feng Ren > > > > > >

Re: [Qemu-devel] [PATCH 0/4] virtio: ARRAY_SIZE fixups

Hi, Your series seems to have some coding style problems. See output below for more information: Message-id: 1484771412-28024-1-git-send-email-...@redhat.com Subject: [Qemu-devel] [PATCH 0/4] virtio: ARRAY_SIZE fixups Type: series === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git

[Qemu-devel] [PATCH 3/4] compiler: expression version of QEMU_BUILD_BUG_ON

QEMU_BUILD_BUG_ON uses a typedef in order to be safe to use outside functions, but sometimes it's useful to have a version that can be used within an expression. Following what Linux does, introduce QEMU_BUILD_BUG_ON_ZERO that return zero after checking condition at build time. Signed-off-by: Mich

[Qemu-devel] [PATCH 2/4] compiler: drop ; after BUILD_BUG_ON

All users include the trailing ;, let's require that so that uses such as if (a) QEMU_BUILD_BUG_ON(); do not produce unexpected results. Not a huge problem for QEMU since our style requires the use of {} but seems cleaner nevertheless. Signed-off-by: Michael S. Tsirkin --- include/qemu/compiler

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