Re: [Qemu-devel] [Bug 1653384] [NEW] Assertion failed with USB pass through with XHCI controller

Hi, > qemu-system-x86_64: hw/usb/core.c:623: usb_packet_cleanup: Assertion > `!usb_packet_is_inflight(p)' failed. We are trying to free a in-flight transfer. Hmm. > Bisected the issue to following commit: > first bad commit: [94b037f2a451b3dc855f9f2c346e5049a361bd55] xhci: use linked > list fo

[Qemu-devel] [Bug 622367] Re: No BIOS MPFP structure with smp=92 and more

QEMU 0.12 is quite outdated nowadays ... can you still reproduce this issue with the latest version of QEMU (currently version 2.8)? ** Changed in: qemu Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

[Qemu-devel] [Bug 1619438] Re: GTK+ UI, delete key deletes to the left in the monitor

Released with version 2.8 ** Changed in: qemu Status: Fix Committed => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1619438 Title: GTK+ UI, delete key deletes to the left in t

[Qemu-devel] [Bug 1624726] Re: Integrator/CP regression after QOM'ification of integratorcp.c

Patch has been included here: http://git.qemu.org/?p=qemu.git;a=commitdiff;h=e9d9ee234f852026d58 ... and been released with QEMU version 2.8 ** Changed in: qemu Status: New => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribe

Re: [Qemu-devel] qemu-2.8-rc4 is broken

> From: Stefan Hajnoczi [mailto:stefa...@gmail.com] > On Wed, Dec 21, 2016 at 5:57 AM, Pavel Dovgalyuk wrote: > >> -Original Message- > >> From: Stefan Hajnoczi [mailto:stefa...@gmail.com] > >> On Tue, Dec 20, 2016 at 11:10 AM, Pavel Dovgalyuk > >> wrote: > >> >> From: Stefan Hajnoczi [m

[Qemu-devel] [Bug 696834] Re: FP exception reporting not working on NetBSD host

Thanks for verifying! ** Changed in: qemu Status: Incomplete => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/696834 Title: FP exception reporting not working on NetBSD host S

[Qemu-devel] [Bug 1414293] Re: target-lm32/translate.c:336: bad ? : operator

Released with version 2.8 ** Changed in: qemu Status: Fix Committed => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1414293 Title: target-lm32/translate.c:336: bad ? : operato

[Qemu-devel] [Bug 1625295] Re: qemu-arm dies with libarmmem inside ld.so.preload

Released with version 2.8 ** Changed in: qemu Status: Fix Committed => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1625295 Title: qemu-arm dies with libarmmem inside ld.so.pr

[Qemu-devel] What the current status on using loadvm with read-only qcow2 image

Hello, Is there a way to use "-loadvm" loading an internal snapshot with a read-only "qcow2" image for the latest version of qemu? This seems to be a popular question, here are two "recent" ones: [1] https://bugs.launchpad.net/qemu/+bug/1184089 [2] https://lists.nongnu.org/archive/html/qemu-discu

[Qemu-devel] [Bug 1464611] Re: 4 * redundant conditions

Released with version 2.8 ** Changed in: qemu Status: Fix Committed => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1464611 Title: 4 * redundant conditions Status in QEMU:

[Qemu-devel] [Bug 1586756] Re: "-serial unix:" option of qemu-system-arm is broken in qemu 2.6.0

Fix has been committed here: http://git.qemu.org/?p=qemu.git;a=commitdiff;h=6ab3fc32ea640026726b ... and been released with QEMU version 2.8 ** Changed in: qemu Status: Incomplete => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is su

[Qemu-devel] [Bug 1611979] Re: GTK+ interface, backspace is broken in the monitor console

Released with version 2.8 ** Changed in: qemu Status: Fix Committed => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1611979 Title: GTK+ interface, backspace is broken in the m

[Qemu-devel] [Bug 1639322] Re: pasting into ppc64 serial console kills qemu

FWIW, the crash should be fixed by this commit here: http://git.qemu.org/?p=qemu.git;a=commitdiff;h=7bacfd7f7289192c83330 (but we still need to fix the gtk side, too, to only send as much characters at once as the receiving side can take) -- You received this bug notification because you are a m

[Qemu-devel] [Bug 1631625] Re: target-mips/dsp_helper.c: two possible bad shifts

Released with version 2.8 ** Changed in: qemu Status: Fix Committed => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1631625 Title: target-mips/dsp_helper.c: two possible bad s

[Qemu-devel] [Bug 1631773] Re: hw/dma/pl080.c:354: possible typo ?

Released with version 2.8. ** Changed in: qemu Status: Fix Committed => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1631773 Title: hw/dma/pl080.c:354: possible typo ? Status

Re: [Qemu-devel] [PATCH 1/4] ramblock-notifier: new

On Wed, 01/11 06:48, Stefan Weil wrote: > On 01/11/17 06:38, Stefan Weil wrote: > > Hi, > > > > this fails for me when building with XEN support. > > I noticed the failure when testing the latest HAXM patches. > > See compiler output below. > > > > Regards > > Stefan > > The patch compiles with

[Qemu-devel] [Bug 1637447] Re: VNC/RFB: QEMU reports incorrect name (length)

Fix has been committed: http://git.qemu.org/?p=qemu.git;a=commitdiff;h=97efe4f961dcf5a0126 ** Changed in: qemu Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/163744

Re: [Qemu-devel] [PATCH v2 0/2] memory: extend "info mtree" with flat view dump

On Wed, Dec 21, 2016 at 03:58:55PM +0800, Peter Xu wrote: > v2: > - fix a size error in patch 2 > - add r-b for Marc-André in patch 1 Ping? :) -- peterx

Re: [Qemu-devel] [PATCH 1/4] ramblock-notifier: new

On 01/11/17 06:38, Stefan Weil wrote: Hi, this fails for me when building with XEN support. I noticed the failure when testing the latest HAXM patches. See compiler output below. Regards Stefan The patch compiles with this modification: diff --git a/xen-mapcache.c b/xen-mapcache.c index dc9

Re: [Qemu-devel] [PATCH] Add DOS support for RTL8139

On 08/01/17 22:54, Gerhard Wiesinger wrote: > Signed-off-by: Gerhard Wiesinger > --- > hw/net/rtl8139.c | 288 > ++- > 1 file changed, 264 insertions(+), 24 deletions(-) > > diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c > index f05e59c..5241

Re: [Qemu-devel] [PATCH v4 4/4] migration: Fail migration blocker for --only-migratble

On Tue, Jan 10, 2017 at 10:45 PM, Peter Maydell wrote: > On 9 January 2017 at 17:02, Ashijeet Acharya > wrote: >> migrate_add_blocker should rightly fail if the '--only-migratable' >> option was specified and the device in use should not be able to >> perform the action which results in an unmig

Re: [Qemu-devel] [PATCH 1/4] ramblock-notifier: new

Hi, this fails for me when building with XEN support. I noticed the failure when testing the latest HAXM patches. See compiler output below. Regards Stefan On 12/20/16 17:31, Fam Zheng wrote: From: Paolo Bonzini This adds a notify interface of ram block additions and removals. Signed-off-b

[Qemu-devel] [kvm-unit-tests PATCH v5 1/2] run_tests: put logs into per-test file

We were using test.log before to keep all the test logs. This patch creates one log file per test case under logs/ directory with name "TESTNAME.log". Meanwhile, we will keep the last time log into logs.old/. Renaming scripts/functions.bash into scripts/common.bash to store some more global variab

[Qemu-devel] [kvm-unit-tests PATCH v5 0/2] run_tests: support concurrent test execution

v5: - add "/" at start/end of line where proper [Drew] - remove useless newline in Makefile [Drew] - don't check "mv" since it won't fail [Drew] - avoid using '"s in (( )) [Drew] - comment fix [Drew] v4: - add .gitignore for logs/ [Drew] - instead of create globals.bash, renaming function.bash int

[Qemu-devel] [kvm-unit-tests PATCH v5 2/2] run_tests: allow run tests in parallel

run_task.sh is getting slow. This patch is trying to make it faster by running the tests concurrently. We provide a new parameter "-j" for the run_tests.sh, which can be used to specify how many run queues we want for the tests. Default queue length is 1, which is the old behavior. Quick test on

Re: [Qemu-devel] [kvm-unit-tests PATCH v4 2/2] run_tests: allow run tests in parallel

On Tue, Jan 10, 2017 at 06:39:59PM +0100, Andrew Jones wrote: > On Mon, Jan 09, 2017 at 12:04:54PM +0800, Peter Xu wrote: > > run_task.sh is getting slow. This patch is trying to make it faster by > > running the tests concurrently. > > > > We provide a new parameter "-j" for the run_tests.sh, whi

Re: [Qemu-devel] [PATCH] migration: re-active images when migration fails to complete

ping .. ? Any comments ? Or should I send a for formal patch ? On 2016/12/22 10:56, Hailiang Zhang wrote: On 2016/12/9 4:02, Dr. David Alan Gilbert wrote: * Hailiang Zhang (zhang.zhanghaili...@huawei.com) wrote: Hi， On 2016/12/6 23:24, Dr. David Alan Gilbert wrote: * Kevin Wolf (kw...@redha

Re: [Qemu-devel] [kvm-unit-tests PATCH v4 1/2] run_tests: put logs into per-test file

On Tue, Jan 10, 2017 at 06:28:41PM +0100, Andrew Jones wrote: > On Mon, Jan 09, 2017 at 12:04:53PM +0800, Peter Xu wrote: > > We were using test.log before to keep all the test logs. This patch > > creates one log file per test case under logs/ directory with name > > "TESTNAME.log". Meanwhile, we

Re: [Qemu-devel] [PATCH V4 net-next] vhost_net: device IOTLB support

On 2017年01月11日 12:32, Jason Wang wrote: This patches implements Device IOTLB support for vhost kernel. This is done through: 1) switch to use dma helpers when map/unmap vrings from vhost codes 2) introduce a set of VhostOps to: - setting up device IOTLB request callback - processing de

[Qemu-devel] [PATCH V4 net-next] vhost_net: device IOTLB support

This patches implements Device IOTLB support for vhost kernel. This is done through: 1) switch to use dma helpers when map/unmap vrings from vhost codes 2) introduce a set of VhostOps to: - setting up device IOTLB request callback - processing device IOTLB request - processing device IOTL

Re: [Qemu-devel] [PATCH V5 2/2] Add a new qmp command to do checkpoint, query xen replication status

Hi~~ Eric: I have send the V6 to fix the issues below, Have any comments? Thanks Zhang Chen On 01/05/2017 04:40 AM, Eric Blake wrote: On 12/27/2016 03:38 AM, Zhang Chen wrote: We can call this qmp command to do checkpoint outside of qemu. Like Xen colo need this function. That sentenc

Re: [Qemu-devel] [PATCH] tap: fix memory leak on failure in net_init_tap()

On 2017年01月11日 03:21, Peter Maydell wrote: Commit 091a6b2ac fixed most of the memory leaks in failure paths in net_init_tap() reported by Coverity (CID 1356216), but missed one. Fix it by deferring the allocation of fds and vhost_fds until after the error check. Signed-off-by: Peter Maydell -

Re: [Qemu-devel] [PULL 00/65] tcg 2.9 patch queue

Hi, Your series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20170111021820.24416-1-...@twiddle.net Subject: [Qemu-devel] [PULL 00/65] tcg 2.9 patch queue === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log --oneline $

[Qemu-devel] [Bug 1626972] Re: QEMU memfd_create fallback mechanism change for security drivers

Xenial Verification (with 3.13 kernel from Trusty since a <= 3.17 kernel is needed). This verifies that Ubuntu Cloud Archive repositories will be alright with this new packages (from Xenial / Yakkety). ## CURRENT inaddy@(xkvm01):~$ apt-cache policy qemu-kvm qemu-kvm: Installed: 1:2.5+dfsg-5ubun

Re: [Qemu-devel] [PATCH v5 1/6] Pass generic CPUState to gen_intermediate_code()

On 12/28/2016 08:27 AM, Lluís Vilanova wrote: Needed to implement a target-agnostic gen_intermediate_code() in the future. Signed-off-by: Lluís Vilanova Reviewed-by: David Gibson --- Reviewed-by: Richard Henderson r~

Re: [Qemu-devel] [PATCH] hw/net/dp8393x: Avoid unintentional sign extensions on addresses

On 2017年01月10日 02:43, Peter Maydell wrote: The dp8393x has several 32-bit values which are formed by concatenating two 16 bit device register values. Attempting to do these inline with ((s->reg[HI] << 16) | s->reg[LO]) can result in an unintended sign extension because "x << 16" is of type 'int

[Qemu-devel] [PULL 62/65] tests: New test-bitcnt

From: Alex Bennée Add some unit tests for bit count functions (currently only ctpop). As the routines are based on the Hackers Delight optimisations I based the test patterns on their tests. Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- tests/.gitignore | 1 + tests/

Re: [Qemu-devel] [PATCH v5 3/6] target: [tcg] Add generic translation framework

On 12/28/2016 08:28 AM, Lluís Vilanova wrote: +typedef enum DisasJumpType { +DJ_NEXT, +DJ_TOO_MANY, +DJ_TARGET, +} DisasJumpType; I wonder if enums like DJ_TARGET_{0..N} wouldn't be better, rather than doing addition in the target-specific names. +typedef struct DisasContextBase

[Qemu-devel] [PULL 64/65] tcg/ppc: Handle ctpop opcode

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 5 +++-- tcg/ppc/tcg-target.inc.c | 12 +++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 57e66cf..abd8b3d 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/

[Qemu-devel] [PULL 61/65] qemu/host-utils.h: Reduce the operation count in the fallback ctpop

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/host-utils.h | 25 +++-- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 46187bb..96288d0 100644 --- a/include/qemu/host-util

[Qemu-devel] [PULL 59/65] target-tilegx: Use ctpop helper

Signed-off-by: Richard Henderson --- target/tilegx/helper.c| 5 - target/tilegx/helper.h| 1 - target/tilegx/translate.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c index b6f5e29..4964bb9 100644 --- a/target/til

[Qemu-devel] [PULL 48/65] tcg/i386: Handle ctz and clz opcodes

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 8 +-- tcg/i386/tcg-target.inc.c | 125 ++ 2 files changed, 120 insertions(+), 13 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index f2d9955..8fff287 100644 -

Re: [Qemu-devel] [PATCH V4 10/10] vhost_net: device IOTLB support

On 2017年01月10日 12:55, Michael S. Tsirkin wrote: On Fri, Dec 30, 2016 at 06:09:19PM +0800, Jason Wang wrote: This patches implements Device IOTLB support for vhost kernel. This is done through: 1) switch to use dma helpers when map/unmap vrings from vhost codes 2) introduce a set of VhostOps t

[Qemu-devel] [PULL 57/65] target-s390x: Avoid a loop for popcnt

Signed-off-by: Richard Henderson --- target/s390x/int_helper.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/s390x/int_helper.c b/target/s390x/int_helper.c index 5bc470b..f26f36a 100644 --- a/target/s390x/int_helper.c +++ b/target/s390x/int_helper.c @@

[Qemu-devel] [PULL 63/65] tcg: Use ctpop to generate ctz if needed

Particularly when andc is also available, this is two insns shorter than using clz to compute ctz. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 100 +++ 1 file changed, 60 insertions(+), 40 deletions(-) diff --git a/tcg/tcg-op.c b/t

[Qemu-devel] [PULL 46/65] tcg/i386: Hoist common arguments in tcg_out_op

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 197 ++ 1 file changed, 95 insertions(+), 102 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index e497bef..83572ac 100644 --- a/tcg/i386/tcg-target.inc.c

[Qemu-devel] [PULL 56/65] target-ppc: Use ctpop helper

Signed-off-by: Richard Henderson --- target/ppc/helper.h | 3 +-- target/ppc/int_helper.c | 18 +++--- target/ppc/translate.c | 6 +- 3 files changed, 9 insertions(+), 18 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 1ed1d2c..0a8fbba 100644 ---

[Qemu-devel] [PULL 60/65] target-i386: Use ctpop helper

Signed-off-by: Richard Henderson --- target/i386/cc_helper.c | 3 +++ target/i386/cpu.h| 1 + target/i386/ops_sse.h| 26 -- target/i386/ops_sse_header.h | 1 - target/i386/translate.c | 13 +++-- 5 files changed, 15 insertions(+), 2

[Qemu-devel] [PULL 43/65] tcg/mips: Handle clz opcode

Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 6 -- tcg/mips/tcg-target.inc.c | 47 +++ 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 06988cf..a680f16 100644 -

[Qemu-devel] [PULL 53/65] target-xtensa: Use clrsb helper

Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 5c719a4..5a93705 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -13

[Qemu-devel] [PULL 55/65] target-alpha: Use ctpop helper

Signed-off-by: Richard Henderson --- target/alpha/helper.h | 2 -- target/alpha/int_helper.c | 5 - target/alpha/translate.c | 2 +- 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/target/alpha/helper.h b/target/alpha/helper.h index eed3906..d60f208 100644 --- a/target/alph

[Qemu-devel] [PULL 42/65] tcg/arm: Handle ctz and clz opcodes

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 4 ++-- tcg/arm/tcg-target.inc.c | 27 +++ 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 02cc242..4cb94dc 100644 -

[Qemu-devel] [PULL 51/65] target-arm: Use clrsb helper

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper-a64.c| 10 -- target/arm/helper-a64.h| 2 -- target/arm/translate-a64.c | 8 3 files changed, 4 insertions(+), 16 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.

[Qemu-devel] [PULL 47/65] tcg/i386: Allow bmi2 shiftx to have non-matching operands

Previously we could not have different constraints for different ISA levels, which prevented us from eliding the matching constraint for shifts. We do now have to make sure that the operands match for constant shifts. We can also handle some small left shifts via lea. Signed-off-by: Richard Hende

[Qemu-devel] [PULL 39/65] target-i386: Use clz and ctz opcodes

Signed-off-by: Richard Henderson --- target/i386/helper.h | 2 -- target/i386/int_helper.c | 11 --- target/i386/translate.c | 31 ++- 3 files changed, 14 insertions(+), 30 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index bd9b2

[Qemu-devel] [PULL 65/65] tcg/i386: Handle ctpop opcode

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 5 +++-- tcg/i386/tcg-target.inc.c | 12 +++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b8f73f5..21d96ec 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg

[Qemu-devel] [PULL 50/65] tcg: Add helpers for clrsb

The number of actual invocations does not warrent an opcode, and the backends generating it. But at least we can eliminate redundant helpers. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg-runtime.c | 10 ++ tcg/tcg-op.c | 28 tc

[Qemu-devel] [PULL 32/65] target-ppc: Use clz and ctz opcodes

Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 target/ppc/int_helper.c | 20 target/ppc/translate.c | 20 3 files changed, 16 insertions(+), 28 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index da00f0a..1

[Qemu-devel] [PULL 37/65] target-xtensa: Use clz opcode

Signed-off-by: Richard Henderson --- target/xtensa/helper.h| 2 -- target/xtensa/op_helper.c | 13 - target/xtensa/translate.c | 13 +++-- 3 files changed, 11 insertions(+), 17 deletions(-) diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index 5ea9c5b..0c8ad

[Qemu-devel] [PULL 58/65] target-sparc: Use ctpop helper

Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/helper.c| 5 - target/sparc/helper.h| 1 - target/sparc/translate.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/sparc/helper.c b/target/sparc/helper.c index 359b0b1..1d85489

[Qemu-devel] [PULL 49/65] tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR

The ISA manual documents the output is undefined if the input was zero. However, we document in target-i386 that the behavior of real silicon is to preserve the contents of the output register. We also mention that there are real applications that depend on this. That this is baked into silicon

[Qemu-devel] [PULL 29/65] target-microblaze: Use clz opcode

Signed-off-by: Richard Henderson --- target/microblaze/helper.h| 1 - target/microblaze/op_helper.c | 5 - target/microblaze/translate.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index bd13826..71a6c08 100

[Qemu-devel] [PULL 31/65] target-openrisc: Use clz and ctz opcodes

Signed-off-by: Richard Henderson --- target/openrisc/helper.h | 2 -- target/openrisc/int_helper.c | 19 --- target/openrisc/translate.c | 6 -- 3 files changed, 4 insertions(+), 23 deletions(-) diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index f53

[Qemu-devel] [PULL 54/65] tcg: Add opcode for ctpop

The number of actual invocations of ctpop itself does not warrent an opcode, but it is very helpful for POWER7 to use in generating an expansion for ctz. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg-runtime.c| 10 ++ tcg/aarch64/tcg-target.h | 2 ++ tcg

[Qemu-devel] [PULL 45/65] tcg/i386: Fuly convert tcg_target_op_def

Use a switch instead of searching a table. Share constraints between 32-bit and 64-bit, when at all possible. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 340 +++--- 1 file changed, 198 insertions(+), 142 deletions(-) diff --git a/tc

[Qemu-devel] [PULL 52/65] target-tricore: Use clrsb helper

Tested-by: Bastian Koppelmann Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/tricore/helper.h| 1 - target/tricore/op_helper.c | 5 - target/tricore/translate.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/tricore/helper.h b/t

[Qemu-devel] [PULL 25/65] disas/i386.c: Handle tzcnt

Signed-off-by: Richard Henderson --- disas/i386.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/disas/i386.c b/disas/i386.c index 57145d0..07f871f 100644 --- a/disas/i386.c +++ b/disas/i386.c @@ -682,6 +682,7 @@ fetch_data(struct disassemble_info *info, bfd_byt

[Qemu-devel] [PULL 30/65] target-mips: Use clz opcode

Signed-off-by: Richard Henderson --- target/mips/helper.h| 7 --- target/mips/op_helper.c | 22 -- target/mips/translate.c | 23 --- 3 files changed, 16 insertions(+), 36 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index

[Qemu-devel] [PULL 41/65] tcg/aarch64: Handle ctz and clz opcodes

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 8 tcg/aarch64/tcg-target.inc.c | 48 2 files changed, 52 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 976f493..9d6b0

[Qemu-devel] [PULL 21/65] tcg: Transition flat op_defs array to a target callback

This will allow the target to tailor the constraints to the auto-detected ISA extensions. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 14 ++-- tcg/arm/tcg-target.inc.c | 14 ++-- tcg/i386/tcg-target.inc.c| 14 ++-- tcg/ia64/tc

[Qemu-devel] [PULL 24/65] tcg: Add clz and ctz opcodes

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg-runtime.c| 20 +++ tcg/README | 8 +++ tcg/aarch64/tcg-target.h | 4 ++ tcg/arm/tcg-target.h | 2 + tcg/i386/tcg-target.h| 4 ++ tcg/ia64/tcg-target.h| 4 ++ tcg/mips/tcg-target

[Qemu-devel] [PULL 44/65] tcg/s390: Handle clz opcode

Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.inc.c | 36 +++- 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 3ac2dc9..22500ba 100644 --- a/tcg/s390/t

[Qemu-devel] [PULL 40/65] tcg/ppc: Handle ctz and clz opcodes

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 10 +--- tcg/ppc/tcg-target.inc.c | 67 2 files changed, 73 insertions(+), 4 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 698a599..c798c9c 100644 --

[Qemu-devel] [PULL 28/65] target-cris: Use clz opcode

Signed-off-by: Richard Henderson --- target/cris/helper.h| 1 - target/cris/op_helper.c | 5 - target/cris/translate.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/cris/helper.h b/target/cris/helper.h index ff35956..20d21c4 100644 --- a/target/cris/helper.h

[Qemu-devel] [PULL 35/65] target-tricore: Use clz opcode

Tested-by: Bastian Koppelmann Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/tricore/helper.h| 2 -- target/tricore/op_helper.c | 10 -- target/tricore/translate.c | 5 +++-- 3 files changed, 3 insertions(+), 14 deletions(-) diff --git a/target/tricor

[Qemu-devel] [PULL 20/65] tcg: Add markup for output requires new register

This is the same concept as, and same markup as, the early clobber markup in gcc. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 34 ++ tcg/tcg.h | 1 + 2 files changed, 23 insertions(+), 12 deletions(-) diff --git a/tcg/tcg.c b/tcg/t

[Qemu-devel] [PULL 38/65] target-arm: Use clz opcode

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper-a64.c| 10 -- target/arm/helper-a64.h| 2 -- target/arm/helper.c| 5 - target/arm/helper.h| 1 - target/arm/translate-a64.c | 8 target/arm/translate.c | 6 +++---

[Qemu-devel] [PULL 15/65] target-i386: Use new deposit and extract ops

A couple of places where it was easy to identify a right-shift followed by an extract or and-with-immediate, and the obvious sign-extract from a high byte register. Acked-by: Eduardo Habkost Signed-off-by: Richard Henderson --- target/i386/translate.c | 45 +++---

[Qemu-devel] [PULL 27/65] target-alpha: Use the ctz and clz opcodes

Signed-off-by: Richard Henderson --- target/alpha/helper.h | 2 -- target/alpha/int_helper.c | 10 -- target/alpha/translate.c | 4 ++-- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/target/alpha/helper.h b/target/alpha/helper.h index 004221d..eed3906 100644 --- a

[Qemu-devel] [PULL 33/65] target-s390x: Use clz opcode

Signed-off-by: Richard Henderson --- target/s390x/helper.h | 1 - target/s390x/int_helper.c | 6 -- target/s390x/translate.c | 2 +- 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 207a6e7..9102071 100644 --- a/target/s390

[Qemu-devel] [PULL 36/65] target-unicore32: Use clz opcode

Signed-off-by: Richard Henderson --- target/unicore32/helper.c| 10 -- target/unicore32/helper.h| 3 --- target/unicore32/translate.c | 6 +++--- 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index d603bde..

[Qemu-devel] [PULL 11/65] tcg/s390: Implement field extraction opcodes

Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 4 ++-- tcg/s390/tcg-target.inc.c | 11 +++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index d650a72..e9ac12e 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s

[Qemu-devel] [PULL 26/65] disas/ppc: Handle popcnt and cnttz

Signed-off-by: Richard Henderson --- disas/ppc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/disas/ppc.c b/disas/ppc.c index bd05623..ed7e0d0 100644 --- a/disas/ppc.c +++ b/disas/ppc.c @@ -1955,6 +1955,9 @@ extract_tbr (unsigned long insn, #define POWER4 PPC_OPCODE_POWER4 #d

[Qemu-devel] [PULL 23/65] tcg: Allow an operand to be matching or a constant

This allows an output operand to match an input operand only when the input operand needs a register. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/README | 13 + tcg/tcg.c | 63 +++--- 2 files changed, 41

[Qemu-devel] [PULL 34/65] target-tilegx: Use clz and ctz opcodes

Signed-off-by: Richard Henderson --- target/tilegx/helper.c| 10 -- target/tilegx/helper.h| 2 -- target/tilegx/translate.c | 4 ++-- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c index b4fba9c..b6f5e29 100644 ---

[Qemu-devel] [PULL 09/65] tcg/ppc: Implement field extraction opcodes

Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 4 ++-- tcg/ppc/tcg-target.inc.c | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index c765d3e..b42c57a 100644 --- a/tcg/ppc/tcg

[Qemu-devel] [PULL 12/65] tcg/s390: Support deposit into zero

Since we can no longer use matching constraints, this does mean we must handle that data movement by hand. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 30 ++ 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c

[Qemu-devel] [PULL 22/65] tcg: Pass the opcode width to target_parse_constraint

This will let us choose how to interpret a given constraint depending on whether the opcode is 32- or 64-bit. Which will let us share more constraint combinations between opcodes. At the same time, change the interface to return the advanced pointer instead of passing it in/out by reference. Rev

[Qemu-devel] [PULL 17/65] target-ppc: Use the new deposit and extract ops

Use the new primitives for RDWINM and RLDICL. Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/translate.c | 35 +++ 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 59e

[Qemu-devel] [PULL 07/65] tcg/i386: Implement field extraction opcodes

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 12 +--- tcg/i386/tcg-target.inc.c | 38 ++ 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7625188..dc19c47 100644 ---

[Qemu-devel] [PULL 19/65] tcg/optimize: Fold movcond 0/1 into setcond

Signed-off-by: Richard Henderson --- tcg/optimize.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index f41ed2c..9e26bb7 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1105,6 +1105,21 @@ void tcg_optimize(TCGContext *s)

[Qemu-devel] [PULL 01/65] tcg: Add field extraction primitives

Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of fixed position bitfields, much like we already have for deposit. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/README | 20 ++- tcg/aarch64/tcg-target.h | 4 + tcg/arm/tcg-target.h | 2 +

[Qemu-devel] [PULL 14/65] target-arm: Use new deposit and extract ops

Use the new primitives for UBFX and SBFX. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 81 +- target/arm/translate.c | 37 + 2 files changed, 37 insertions(+), 81 deletions(-) diff --git a/target/arm/transl

[Qemu-devel] [PULL 18/65] target-s390x: Use the new deposit and extract ops

Use the new primitives for RISBG. Signed-off-by: Richard Henderson --- target/s390x/translate.c | 34 ++ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 02bc705..6cebb7e 100644 --- a/target/

[Qemu-devel] [PULL 08/65] tcg/mips: Implement field extraction opcodes

Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 4 +++- tcg/mips/tcg-target.inc.c | 9 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index fcc2986..92d203a 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/t

[Qemu-devel] [PULL 06/65] tcg/arm: Implement field extraction opcodes

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 4 ++-- tcg/arm/tcg-target.inc.c | 24 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index d1fe12b..4e30728 100644 ---

[Qemu-devel] [PULL 13/65] target-alpha: Use deposit and extract ops

Signed-off-by: Richard Henderson --- target/alpha/translate.c | 67 ++-- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 114927b..5ac2277 100644 --- a/target/alpha/translate.c +++

[Qemu-devel] [PULL 16/65] target-mips: Use the new extract op

Use extract for EXT and DEXT. Reviewed-by: Yongbok Kim Signed-off-by: Richard Henderson --- target/mips/translate.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 57b824f..8deffa1 100644 --- a/target/mips/

[Qemu-devel] [PULL 05/65] tcg/arm: Move isa detection to tcg-target.h

This allows us to use this detection within the TCG_TARGET_HAS_* macros, instead of requiring a function call into tcg-target.inc.c. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 36 tcg/arm/tcg-target.inc.c | 41 +-

[Qemu-devel] [PULL 03/65] tcg: Add deposit_z expander

While we don't require a new opcode, it is handy to have an expander that knows the first source is zero. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 143 +++ tcg/tcg-op.h | 6 +++ 2 files changed, 149 insertions(+) diff --git a/

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