[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/584514
Title:
Qemu-KVM 0.1
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/589231
Title:
cirrus vga i
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/712337
Title:
connecthon b
From: Caoxinhua
(gdb) bt
#0 0x7f9a68b095d7 in __GI_raise (sig=sig@entry=6) at
../nptl/sysdeps/unix/sysv/linux/raise.c:56
#1 0x7f9a68b0acc8 in __GI_abort () at abort.c:90
#2 0x7f9a69cda389 in PAT_abort () from /usr/lib64/libuvpuserhotfix.so
#3 0x7f9a69cdda0d in patchIllInsHandler
On 12/16/2016 07:02 AM, Michael S. Tsirkin wrote:
>
>> 1) We need to do the right thing for the guest, I don't think we
>> should be presuming that different reset types are equivalent,
>> leaving gaps where we expect the guest/host to do a reset and don't
>> follow through on other
>
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Wednesday, December 28, 2016 1:29 AM
> To: Gonglei (Arei)
> Cc: QEMU Developers
> Subject: Re: [PULL 0/4] cryptodev patches
>
> On 24 December 2016 at 06:12, Gonglei wrote:
> > The following changes since commit
> a470b33259bf82ef2
Hi Vladimir,
On Mon, Dec 26, 2016 at 05:52:54PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Shouldn't we add some flags to REP_META_CONTEXT, for client to be insure, is
> returned string a direct context name or some kind of wildcard? Just a flags
> field, with one flag defined for now: NBD_REP_M
The patch fixes dead code in pl080_read() and pl080_write() as reported
in bug #1637974. According to ARM's official Technical Reference Manual,
offsets handled by the switch statement are 0x100, 0x104, 0x108, 0x10C
and 0x110, so the solution suggested by the guy who reported the bug is
right.
Sig
On 27 December 2016 at 21:45, Adeel Mujahid wrote:
> For instance, consider a C/C++ project with couple of .asm/.S files
> containing Intel or ATT flavored assembly code for AMD64, and the
> aim is to port to AARCH64 -- is it even a deterministic problem
> to transpile precise and bug free AARCH64
On 27 December 2016 at 19:50, Дмитрий Смирнов wrote:
> I haven't tried QEMU 2.8.0, because the job-task requires use QEMU 2.5.1.1.
> So I need to decide this problem on 2.5.1.1 version:(
You haven't really explained what the job-task is or why
it requires 2.5.1.1 in particular. Does this RTOS not
Hello,
[sorry in advance -- this is bit of an off-topic / academic question w.r.t
qemu-devel]
Given the userspace virtualization capability of qemu, is it possible to ship
the code that deals with source-to-source mapping of assembly code (say MIPS64
<-> AMD64) as a separate library, so we c
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Message-id: 20161227165947.20184-1-sergio.g.delr...@gmail.com
Type: series
Subject: [Qemu-devel] [PATCH] hw/dma: Fix dead code in pl080.c
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(
I haven't tried QEMU 2.8.0, because the job-task requires use QEMU 2.5.1.1.
So I need to decide this problem on 2.5.1.1 version:(
2016-12-27 22:32 GMT+03:00 Programmingkid :
> I experience a similar situation with ReactOS. Have you tried it in QEMU
> 2.8.0 yet? If you haven't, it is possible the
An old RealTime-OS. The requirements -- use QEMU 2.5.1.1
2016-12-27 22:18 GMT+03:00 Programmingkid :
>
> On Dec 27, 2016, at 2:16 PM, Дмитрий Смирнов wrote:
>
> > Unfortunately, I have to use version 2.5.1.1. Can I do something in this
> case?
>
> Why do you need to use it? What is the guest oper
The patch fixes dead code in pl080_read() and pl080_write() as reported
in bug #1637974. According to ARM's official Technical Reference Manual,
offsets handled by the switch statement are 0x100, 0x104, 0x108, 0x10C
and 0x110, so the solution suggested by the guy who reported the bug is
right.
Sig
Unfortunately, I have to use version 2.5.1.1. Can I do something in this
case?
2016-12-27 22:01 GMT+03:00 G 3 :
> The version of qemu-system-ppc you are using is kind of old. Version 2.8.0
> is the newest version. I suggest trying the newest version before trying to
> fix a broken feature in an o
qemu-system-ppc version: 2.5.1.1
Ubuntu 14.04
gcc version 4.8.4 (Ubuntu 4.8.4-2ubuntu1~14.04)
GTK 2.0, libsdl1.2-dev
./configure --target-list="ppc-softmmu" --disable-xfsctl
By zero meaning, do you mean this: decr = 0
Yes.
2016-12-27 21:16 GMT+03:00 G 3 :
> When I type 'info registers', I see
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Message-id: 1482869621-24808-1-git-send-email-nutar...@ornl.gov
Type: series
Subject: [Qemu-devel] [PATCH v4] qqq: module for synchronizing with a
simulation clock
=== TEST SCRIPT BEGIN ===
#!/bin/b
This patch adds an interface for pacing the execution of QEMU to match
an external simulation clock. Its aim is to permit QEMU to be used
as a module within a larger simulation system.
Signed-off-by: James J. Nutaro
---
Makefile.objs| 1 +
Makefile.target | 3 +
cpus.c
Le 27/12/2016 à 20:55, OGAWA Hirofumi a écrit :
With "ps2: use QEMU qcodes instead of scancodes", key handling was
changed to qcode base. But all scancodes are not converted to new one.
This adds some missing qcodes/scancodes what I found in using.
[set1 and set3 are from ]
Signed-off-by: OGAW
With "ps2: use QEMU qcodes instead of scancodes", key handling was
changed to qcode base. But all scancodes are not converted to new one.
This adds some missing qcodes/scancodes what I found in using.
[set1 and set3 are from ]
Signed-off-by: OGAWA Hirofumi
---
hw/input/ps2.c| 10 +++
Hervé Poussineau writes:
> [from hw/input/ps2.c]
>>> Can you also add the keycodes for scancode set 1:
>>> +[Q_KEY_CODE_HIRAGANA] = 0x70,
>>> +[Q_KEY_CODE_HENKAN] = 0x79,
>>> +[Q_KEY_CODE_YEN] = 0x7d,
>>
>> Current linux can't use set1, so untested.
>
> Note that those are the same as
I experience a similar situation with ReactOS. Have you tried it in QEMU 2.8.0
yet? If you haven't, it is possible the RealTime-OS might work.
On Dec 27, 2016, at 2:25 PM, Дмитрий Смирнов wrote:
> An old RealTime-OS. The requirements -- use QEMU 2.5.1.1
>
> 2016-12-27 22:18 GMT+03:00 Programmi
Instead of blocking migration on the source when invtsc is
enabled, rely on the migration destination to ensure there's no
TSC frequency mismatch.
We can't allow migration unconditionally because we don't know if
the destination is a QEMU version that is really going to ensure
there's no TSC frequ
This series makes QEMU accept migration with invtsc if:
a) The destination host has a matching TSC frequency; or
b) The destination host has TSC scaling available.
There are two cases where we can ensure the above conditions.
This series implements both:
1) tsc-khz explicitly set on the configur
We can safely allow a VM to be migrated with invtsc enabled if
tsc-khz is set explicitly, because QEMU already refuses to start
if it can't set the TSC frequency to the configured value.
Signed-off-by: Eduardo Habkost
---
target/i386/kvm.c | 19 ++-
1 file changed, 10 insertions(
Cc: "Michael S. Tsirkin"
Cc: Laszlo Ersek
Cc: Igor Mammedov
Signed-off-by: Eduardo Habkost
---
include/hw/i386/pc.h | 1 +
hw/i386/pc_piix.c| 15 ---
hw/i386/pc_q35.c | 13 +++--
3 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/include/hw/i386/pc.h b
Instead of searching the table we have just built, we can check
the env->features field directly.
Signed-off-by: Eduardo Habkost
---
target/i386/kvm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 10a9cd8..a26290f 100644
--- a
On Dec 27, 2016, at 2:16 PM, Дмитрий Смирнов wrote:
> Unfortunately, I have to use version 2.5.1.1. Can I do something in this case?
Why do you need to use it? What is the guest operating system you are using?
Version 2.8 has a lot more bug fixes in it. You might find it easier to use.
>
> 20
no-reply writes:
> Hi,
> Your series failed automatic build test. Please find the testing commands and
> their output below. If you have docker installed, you can probably reproduce
> it
> locally.
I did try to compile all targets and it worked for me... I'll check again just
in case.
Cheers,
no-reply writes:
> Hi,
> Your series seems to have some coding style problems. See output below for
> more information:
Sorry for the noise. I'll resend after checking the style problems.
Cheers,
Lluis
Peter Maydell writes:
> On 27 December 2016 at 15:37, Lluís Vilanova wrote:
>> Adds macro QTAILQ_FOREACH_CONTINUE to support incremental list
>> traversal.
>>
>> Signed-off-by: Lluís Vilanova
>> ---
>> include/qemu/queue.h |5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/incl
The version of qemu-system-ppc you are using is kind of old. Version
2.8.0 is the newest version. I suggest trying the newest version
before trying to fix a broken feature in an older version.
http://wiki.qemu.org/Download
On Dec 27, 2016, at 1:57 PM, Дмитрий Смирнов wrote:
qemu-system-ppc
When I type 'info registers', I see 'DECR 3919147695' at the top of
the screen, so it appears to be working. I think we need more
information from you.
qemu-system-ppc version:
gcc version (gcc -v):
Host info: Ubuntu
Front-end (GTK, SDL, ...):
Compile command: ./configure
Note: ple
From: Richard Henderson
Also manage word and byte operands and fix the computation of
overflow in the case of M68000 arithmetic shifts.
Signed-off-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <1478699171-10637-4-git-send-email-...@twiddle.net>
---
target/m68k/helper.c|
From: Richard Henderson
Report this properly via exception and, importantly, allow
the disassembler the chance to tell us what insn is not handled.
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <1478699171-10637-3-git-send-email-...@twiddle.net>
Signed-off-by: Lauren
680x0 movem can load/store words and long words and can use more
addressing modes. Coldfire can only use long words with (Ax) and
(d16,Ax) addressing modes.
Signed-off-by: Laurent Vivier
Signed-off-by: Richard Henderson
Message-Id: <1478699171-10637-2-git-send-email-...@twiddle.net>
---
target
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
Message-Id: <1477604609-2206-2-git-send-email-laur...@vivier.eu>
Signed-off-by: Richard Henderson
Message-Id: <1478206203-4606-4-git-send-email-...@twiddle.net>
---
target/m68k/translate.c | 16
1 file changed, 16 ins
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-Id: <1478206203-4606-2-git-send-email-...@twiddle.net>
---
target/m68k/translate.c | 84 +
1 file changed, 64 insertions(+), 20 deletions(-)
diff --git a/target/m68k/translate.c b/t
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/translate.c | 391
1 file changed, 391 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 76c77ee..bb5a299 100644
--- a/target/m68k/trans
From: Richard Henderson
Provide gen_lea_mode and gen_ea_mode, where the mode can be
specified manually, rather than taken from the instruction.
Signed-off-by: Richard Henderson
Message-Id: <1478206203-4606-3-git-send-email-...@twiddle.net>
---
target/m68k/translate.c | 112
This is a cleanup patch. It adds call to tcg_temp_free()
when it is missing.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/translate.c | 41 -
1 file changed, 32 insertions(+), 9 deletions(-)
diff --git a/target/m68k/transl
Update helper to set the throwing location in case of div-by-0.
Cleanup divX.w and add quad word variants of divX.l.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
[laurent: modified to clear Z on overflow, as found with risu]
---
linux-user/main.c | 7 ++
target/m68k/cpu.
The following changes since commit e5fdf663cf01f824f0e29701551a2c29554d80a4:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20161223' into
staging (2016-12-27 14:56:47 +)
are available in the git repository at:
git://github.com/vivier/qemu-m68k.git tags/m68k-for-2.9-pull-reques
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/translate.c | 220
1 file changed, 220 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 737009e..1567647 100644
--- a/target/m68k/trans
Implement CAS using cmpxchg.
Implement CAS2 using helper and either cmpxchg when
the 32bit addresses are consecutive, or with
parallel_cpus+cpu_loop_exit_atomic() otherwise.
Suggested-by: Richard Henderson
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/helper.h
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/translate.c | 62 +++--
1 file changed, 50 insertions(+), 12 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 97edb7b..6678b57 100644
--- a/t
On 24 December 2016 at 06:12, Gonglei wrote:
> The following changes since commit a470b33259bf82ef2336bfcd5d07640562d3f63b:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2016-12-22 19:23:51 +)
>
> are available in the git repository at:
>
>
> https:/
nzini/tags/for-upstream' into
> staging (2016-12-22 19:23:51 +)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20161227
>
> for you to fetch changes up to 91db4642f868cf2e591b62d31a19d35b02
On 27 December 2016 at 17:19, Marc-André Lureau wrote:
> Hi,
>
> - Original Message -
>> phew. sounds too complicated.. sitting on wrong machine, wrong email
>> addresses and want to keep my personal footprint out there as small as
>> possible.
>> And hey, this are just typo-fixes, no rock
Hi,
- Original Message -
> Hi,
>
> I used misspell_fixer [1], [2] on qemu sources. (used
> http://git.qemu.org/qemu.git )
> found a bunch of typos, patches with spelling-fixes attached.
>
Nice tool, thanks for the links.
> so.. i did all these stuff, before read and fully understood th
You can have a more detailed procedure on how to run Xvisor on Qemu
Sabrelite (with Linux guests if you wish) at the following URL.
https://github.com/avpatel/xvisor-next/blob/master/docs/arm/imx6-sabrelite.txt
You don't need to start the guest to see the crash. Just boot Xvisor ...
JC
Le 24/
On 24 December 2016 at 11:40, Laurent Vivier wrote:
> The following changes since commit a470b33259bf82ef2336bfcd5d07640562d3f63b:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2016-12-22 19:23:51 +)
>
> are available in the git repository at:
>
> gi
On Tue, Dec 27, 2016 at 10:27:25AM -0500, Christopher Covington wrote:
> On 12/09/2016 07:15 AM, Andrew Jones wrote:
> > On Fri, Dec 09, 2016 at 11:41:06AM +, Andre Przywara wrote:
> >> Hi,
> >>
> >> On 08/12/16 17:50, Andrew Jones wrote:
> >>> Allow a thread to wait some specified amount of ti
On 24 December 2016 at 03:46, Richard Henderson wrote:
> One bug fix, one cleanup.
>
>
> r~
>
>
>
> The following changes since commit a470b33259bf82ef2336bfcd5d07640562d3f63b:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2016-12-22 19:23:51 +)
>
> ar
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Subject: [Qemu-devel] [RFC PATCH v3 0/6] translate: [tcg] Generic translation
framework
Message-id: 148285303159
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Message-id: 148285303159.12721.5833400768046299304.st...@fimbulvetr.bsc.es
Type: series
Subject: [Qemu-devel] [RFC PATCH v3 0/6] translate: [tcg] Generic translation
framework
=== TEST SCRIPT BEGIN
On 12/27/2016 08:09 AM, Vladimir Sementsov-Ogievskiy wrote:
> A bit out of topic, but...
>
>> structured replies via `NBD_OPT_STRUCTURED_REPLY`. Conversely, if
>> structured replies are negotiated, the server MUST use a
>> structured reply for any response with a payload, and MUST NOT use
>> a si
On 27 December 2016 at 15:37, Lluís Vilanova wrote:
> Adds macro QTAILQ_FOREACH_CONTINUE to support incremental list
> traversal.
>
> Signed-off-by: Lluís Vilanova
> ---
> include/qemu/queue.h |5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/qemu/queue.h b/include/qemu/qu
On 12/09/2016 07:15 AM, Andrew Jones wrote:
> On Fri, Dec 09, 2016 at 11:41:06AM +, Andre Przywara wrote:
>> Hi,
>>
>> On 08/12/16 17:50, Andrew Jones wrote:
>>> Allow a thread to wait some specified amount of time. Can
>>> specify in cycles, usecs, and msecs.
>>> +++ b/lib/arm/asm/delay.h
>>>
Needed to implement a target-agnostic gen_intermediate_code() in the
future.
Signed-off-by: Lluís Vilanova
Reviewed-by: David Gibson
---
include/exec/exec-all.h |2 +-
target-alpha/translate.c | 11 +--
target-arm/translate.c| 24
targ
Signed-off-by: Lluís Vilanova
---
target-arm/translate-a64.c | 348 ++---
target-arm/translate.c | 718 ++--
target-arm/translate.h | 42 ++-
3 files changed, 554 insertions(+), 554 deletions(-)
diff --git a/target-arm/translate
Signed-off-by: Lluís Vilanova
---
target-i386/translate.c | 303 ++-
1 file changed, 139 insertions(+), 164 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 61d73e286f..34c44b7686 100644
--- a/target-i386/translate.c
+
Signed-off-by: Lluís Vilanova
---
include/exec/gen-icount.h |2
include/exec/translate-all_template.h | 76
include/qom/cpu.h | 21 +++
translate-all_template.h | 202 +
4 files changed, 300 insert
This series proposes a generic (target-agnostic) instruction translation
framework.
It basically provides a generic main loop for instruction disassembly, which
calls target-specific functions when necessary. This generalization makes
inserting new code in the main loop easier, and helps in keepin
From: Cédric Le Goater
ARM1176 CPUs have TrustZone support and can use the Vector Base
Address Register, but currently, qemu only adds VBAR support to ARMv7
CPUs. Fix this by adding a new feature ARM_FEATURE_VBAR which can used
for ARMv7 and ARM1176 CPUs.
The VBAR feature is always set for ARMv7
Temporarily redefine DISAS_* values based on DJ_TARGET. They should
disappear as targets get ported to the generic framework.
Signed-off-by: Lluís Vilanova
---
include/exec/exec-all.h | 11 +++
target-arm/translate.h | 15 ---
target-cris/translate.c |
From: Cédric Le Goater
Add a new configuration field at the board level and propagate the
value using the "num-cs" property of the FMC controller model.
Signed-off-by: Cédric Le Goater
Message-id: 1480434248-27138-14-git-send-email-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/arm/aspeed.c
From: Alastair D'Silva
Add a NULL check for i2c slave init callbacks, so that we no longer
need to implement empty init functions.
Signed-off-by: Alastair D'Silva
Message-id: 20161202054617.6749-4-alast...@au1.ibm.com
Reviewed-by: Peter Maydell
[PMM: squashed in later tweak from Alistair to if
In the ARMCPRegInfo definitions for the GICv3 CPU interface
registers, we were trying to use .fieldoffset to specify
the locations of data fields within the GICv3CPUState struct.
This is completely broken, because .fieldoffset is for offsets
into the CPUARMState struct. We didn't notice because we
From: Cédric Le Goater
The size of the SRAM depends on the SoC model, so use a per-soc
definition when creating the region.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Reviewed-by: Andrew Jeffery
Message-id: 1480434248-27138-9-git-send-email-...@kaod.org
Signed-off-by: Peter May
Adds macro QTAILQ_FOREACH_CONTINUE to support incremental list
traversal.
Signed-off-by: Lluís Vilanova
---
include/qemu/queue.h |5 +
1 file changed, 5 insertions(+)
diff --git a/include/qemu/queue.h b/include/qemu/queue.h
index 342073fb4d..0d709016f4 100644
--- a/include/qemu/queue.h
From: Cédric Le Goater
The HW does not enforce all the rules in the specs and allows a few
"curious" setups like zero size segments and overlaps. So change the
model to be in sync but keep the warnings which are always interesting
for debug.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Sta
From: Cédric Le Goater
There is not much differences with the A0 revision apart from the DDR
calibration.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Reviewed-by: Andrew Jeffery
Message-id: 1480434248-27138-10-git-send-email-...@kaod.org
Signed-off-by: Peter Maydell
---
includ
From: Cédric Le Goater
The Romulus machine is an OpenPOWER system with an AST2500 SoC for
the BMC and a POWER9 chip for the host. It does not make much
difference for qemu a part from the fact that the FMC controller has
two SPI flash module.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel St
We already log exception entry; add logging of the AArch64 exception
return path as well.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
---
target/arm/op_helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index cd9
From: Alastair D'Silva
Remove trailing whitespace in hw/arm/pxa2xx.c
Signed-off-by: Alastair D'Silva
Message-id: 20161202054617.6749-3-alast...@au1.ibm.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/pxa2xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Reviewed-by: Andrew Jeffery
Message-id: 1480434248-27138-12-git-send-email-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/misc/aspeed_scu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/h
From: Cédric Le Goater
Future machine will use different flash models for the FMC and the SPI
controllers.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Reviewed-by: Andrew Jeffery
Message-id: 1480434248-27138-7-git-send-email-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/arm
From: Cédric Le Goater
The palmetto BMC machine uses a AST2400 revision A1 SoC.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Reviewed-by: Andrew Jeffery
Message-id: 1480434248-27138-11-git-send-email-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/arm/aspeed.c | 2 +-
1 file c
From: Andrew Jones
Signed-off-by: Andrew Jones
Message-id: 20161209143703.29457-1-drjo...@redhat.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/int
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Message-id: 1480434248-27138-6-git-send-email-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/arm/aspeed_soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/a
Signed-off-by: Peter Maydell
Reviewed-by: Andrew Jones
---
include/hw/compat.h | 3 +++
hw/arm/virt.c | 19 +--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/include/hw/compat.h b/include/hw/compat.h
index 8dfc7a3..4fe44d1 100644
--- a/include/hw/compat.h
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Marcin Krzeminski
Reviewed-by: Joel Stanley
Reviewed-by: Andrew Jeffery
Message-id: 1480434248-27138-3-git-send-email-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/block/m25p80.c | 1 +
1 file changed, 1 insertion(+)
di
From: Richard Henderson
We add s->be_data within do_vec_ld/st. Adding it here means that
we have the wrong bits set in SIZE for a big-endian host, leading
to g_assert_not_reached in write_vec_element and read_vec_element.
Signed-off-by: Richard Henderson
Message-id: 1481085020-2614-3-git-send-
From: Cédric Le Goater
With commit ce5b1bbf624b ("exec: move cpu_exec_init() calls to realize
functions"), we can now remove cannot_destroy_with_object_finalize_yet.
Suggested-by: Andrew Jeffery
Signed-off-by: Cédric Le Goater
Message-id: 1480434248-27138-5-git-send-email-...@kaod.org
Reviewed
The GICv3 requires that we only signal Pending interrupts to
the CPU. This category does not include Pending+Active interrupts,
which means we need to check whether the interrupt is Active in
the gicr_int_pending() and gicd_int_pending() functions.
Interrupts are rarely in the Active+Pending state
From: Richard Henderson
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used
for a big-endian host doesn't do what's intended. Fix this by adding
in the vfp.regs offset after computing the inter-register offset.
Signed-off-by: Richard Henderson
Message-id: 1481085020-2614-2-gi
From: Andrew Gacek
When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to
0, the receiver timeout counter should be disabled. See page 1801 of
"Zynq-7000 AP SoC Technical Reference Manual". This commit adds a
such a check before setting the receive timeout interrupt.
Signed-off-by:
in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20161227
for you to fetch changes up to 91db4642f868cf2e591b62d31a19d35b02ea791e:
target-arm: Add VBAR support to ARM1176 CPUs (2016-12-27 14:5
From: Julian Brown
The value of the MVFR1 (Media and VFP Feature Register 1) register for
the Cortex-A8 appears to be incorrect (according to the TRM, DDI0344K),
with the "full denormal arithmetic" and "propagation of NaN" fields
holding both 0 instead of both 1.
I had a go tracing the history o
From: Alistair Francis
The Cadence UART device emulator calculates speed by dividing the
baud rate by a 'baud rate generator' & 'baud rate divider' value.
The device specification defines these register values to be
non-zero and within certain limits. Checks were recently added when
writing to th
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Reviewed-by: Andrew Jeffery
Message-id: 1480434248-27138-4-git-send-email-...@kaod.org
Signed-off-by: Peter Maydell
---
include/hw/arm/aspeed_soc.h | 2 +-
hw/arm/aspeed_soc.c | 17 ++---
2
On 20 December 2016 at 15:31, Andrew Jones wrote:
> Should we output both the destination PC (ELR) and the source PC (where
> the eret was)? Otherwise if there are many erets to the same entry point,
> then the logs won't fully enlighten us.
We don't really conveniently have the source PC, becaus
Le 23/12/2016 à 23:49, OGAWA Hirofumi a écrit :
Hi,
Hervé Poussineau writes:
[from ui/input-keymap.c]
[Q_KEY_CODE_RO] = 0x73,
+[Q_KEY_CODE_HIRAGANA] = 0x70,
+[Q_KEY_CODE_HENKAN] = 0x79,
+[Q_KEY_CODE_YEN] = 0x7d,
[Q_KEY_CODE_KP_COMMA] = 0x7e,
[Q_KEY_CODE__MAX] = 0,
A bit out of topic, but...
structured replies via `NBD_OPT_STRUCTURED_REPLY`. Conversely, if
structured replies are negotiated, the server MUST use a
structured reply for any response with a payload, and MUST NOT use
a simple reply for `NBD_CMD_READ` (even for the case of an early
`EINVAL` due
Am Tue, 27 Dec 2016 12:52:30 +0100
schrieb Laurent Vivier :
> Le 20/12/2016 à 15:32, Thomas Huth a écrit :
> > You can get an empty machine with "-M none" nowadays, so the
> > m68k dummy board (introduced in 2007) seems to be pretty
> > redundant since the "none" machine has been added in 2012.
>
Le 20/12/2016 à 15:32, Thomas Huth a écrit :
> You can get an empty machine with "-M none" nowadays, so the
> m68k dummy board (introduced in 2007) seems to be pretty
> redundant since the "none" machine has been added in 2012.
>
> Signed-off-by: Thomas Huth
> ---
> MAINTAINERS | 4 --
On 2016/12/22 10:56, Hailiang Zhang wrote:
On 2016/12/9 4:02, Dr. David Alan Gilbert wrote:
* Hailiang Zhang (zhang.zhanghaili...@huawei.com) wrote:
Hi，
On 2016/12/6 23:24, Dr. David Alan Gilbert wrote:
* Kevin Wolf (kw...@redhat.com) wrote:
Am 19.11.2016 um 12:43 hat zhanghailiang geschrieb
We can call this qmp command to do checkpoint outside of qemu.
Like Xen colo need this function.
Signed-off-by: Zhang Chen
Signed-off-by: Wen Congyang
---
docs/qmp-commands.txt | 24
migration/colo.c | 17 +
qapi-schema.json | 50 ++
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