On Tue, 27 Sep 2016 20:55:56 +0200
Laurent Vivier wrote:
> Machine specific shutdown function can be registered by
> the machine specific qtest_XXX_boot() if needed.
>
> So we will not have to test twice the architecture (on boot and on
> shutdown) if the test can be run on several architectures
On Tue, 27 Sep 2016 20:55:55 +0200
Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier
> ---
Just a minor remark below, but anyway:
Reviewed-by: Greg Kurz
Cheers.
--
Greg
> tests/e1000e-test.c | 2 +-
> tests/i440fx-test.c | 2 +-
> tests/ide-test.c| 2 +-
Hi Greg,
What about this patch?
It seems you have forget it.
2016-09-27 12:44 GMT+08:00 Li Qiang :
> From: Li Qiang
>
> 9pfs uses g_malloc() to allocate the xattr memory space, if the guest
> reads this memory before writing to it, this will leak host heap
> memory to the guest. This patch avo
On 28.09.2016 03:59, David Gibson wrote:
> On Tue, Sep 27, 2016 at 09:17:19AM +0200, Thomas Huth wrote:
>> On 27.09.2016 06:17, David Gibson wrote:
>>> On Mon, Sep 26, 2016 at 10:17:46PM +0200, Thomas Huth wrote:
[...]
diff --git a/tests/pxe-test.c b/tests/pxe-test.c
index b2cc355..0bdb7a
I also had this problem. You can try to configure the VM with core=1 and
thread=1. See if the "intr->er_full" assertion still exist.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1587970
Title:
QEM
On Wed, 28 Sep 2016 10:14:00 +0800
李强 wrote:
> On 2016-09-28 0:40 GMT+08:00 Greg Kurz wrote:
>
> >
> > Talking about robustness was appropriate for your previous patches, but
> > it does not really apply here since v9fs_iov_vunmarshal() does not have
> > any issue with empty strings actually.
>
On Tue, Sep 20, 2016 at 10:53 PM, Jeff Cody wrote:
> On Tue, Sep 20, 2016 at 06:07:45PM -0700, Ashish Mittal wrote:
>> This patch adds support for a new block device type called "vxhs".
>> Source code for the library that this code loads can be downloaded from:
>> https://github.com/MittalAshish/l
The following vector instructions are added from ISA 3.0.
vclzlsbb - Vector Count Leading Zero Least-Significant Bits Byte
vctzlsbb - Vector Count Trailing Zero Least-Significant Bits Byte
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/helper.h |2 ++
target-ppc
From: Avinesh Kumar
cmpl: invalid bit mask should be 0x0041
bctar: invalid bit mask should be 0xE000
Signed-off-by: Avinesh Kumar
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/translate.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target
From: Vasant Hegde
vmul10uq : Vector Multiply-by-10 Unsigned Quadword VX-form
vmul10euq : Vector Multiply-by-10 Extended Unsigned Quadword VX-form
vmul10cuq : Vector Multiply-by-10 & write Carry Unsigned Quadword VX-form
vmul10ecuq: Vector Multiply-by-10 Extended & write Carry Unsigned Quadword
This series contains 15 new instructions for POWER9 described in ISA3.0.
Patches:
01: Adds vector multiply instructions.
vmul10uq : Vector Multiply-by-10 Unsigned Quadword
vmul10euq : Vector Multiply-by-10 Extended Unsigned Quadword
vmul10cuq : Vector M
From: Hariharan T.S
vextubrx: Vector Extract Unsigned Byte Right-Indexed VX-form
vextuhrx: Vector Extract Unsigned Halfword Right-Indexed VX-form
vextuwrx: Vector Extract Unsigned Word Right-Indexed VX-form
Signed-off-by: Hariharan T.S.
Signed-off-by: Avinesh Kumar
Signed-off-by: Rajalakshmi
From: Avinesh Kumar
vextublx: Vector Extract Unsigned Byte Left
vextuhlx: Vector Extract Unsigned Halfword Left
vextuwlx: Vector Extract Unsigned Word Left
Signed-off-by: Avinesh Kumar
[ Remove else part in helper ]
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/helper.h
The following vector compare not equal instructions are added from ISA 3.0.
vcmpneb - Vector Compare Not Equal Byte
vcmpneh - Vector Compare Not Equal Halfword
vcmpnew - Vector Compare Not Equal Word
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/helper.h |6 +++
Signed-off-by: Wen Congyang
Signed-off-by: Changlong Xie
Signed-off-by: Wang WeiWei
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
Reviewed-by: Eric Blake
---
qapi/block-core.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/block-core.json b/qapi/block-core.
Nikunj A Dadhania writes:
> This series contains 7 new instructions for POWER9 ISA3.0
> Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x.
>
> GCC was adding epilogue for every VSX instructions causing change in
> behaviour. For testing the load vector instructions used mfvsr
lxvh8x: Load VSX Vector Halfword*8
Big-Endian Storage
+---+---+---+---+---+---+---+---+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+---+---+---+---+---+---+---+---+
Little-Endian Storage
+---+---+-
stxvb16x: Store VSX Vector Byte*16
Vector:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Store results in following:
Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
lxvb16x: Load VSX Vector Byte*16
Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Vector load results in:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F
Manipulate data and store 8bytes instead of 4bytes.
Vector:
+-+-+-+-+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-+-+-+-+
Store results in following:
Big-Endian Storage
+-+
Load 8byte at a time and manipulate.
Big-Endian Storage
+-+-+-+-+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-+-+-+-+
Little-Endian Storage
+-+-+-+--
stxvh8x: Store VSX Vector Halfword*8
Vector:
+---+---+---+---+---+---+---+---+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+---+---+---+---+---+---+---+---+
Store results in following:
Big-Endian Storage
+
From: Ravi Bangoria
mtvsrdd: Move To VSR Double Doubleword
Signed-off-by: Ravi Bangoria
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate/vsx-impl.inc.c | 23 +++
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 24 insertions(+)
diff --git a/target-ppc
This series contains 7 new instructions for POWER9 ISA3.0
Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x.
GCC was adding epilogue for every VSX instructions causing change in
behaviour. For testing the load vector instructions used mfvsrld/mfvsrd
for loading vsr to registe
From: Ravi Bangoria
mfvsrld: Move From VSR Lower Doubleword
Signed-off-by: Ravi Bangoria
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate/vsx-impl.inc.c | 17 +
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 18 insertions(+)
diff --git a/target-ppc/tran
From: Ravi Bangoria
mtvsrws: Move To VSR Word & Splat
Signed-off-by: Ravi Bangoria
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate/vsx-impl.inc.c | 23 +++
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 24 insertions(+)
diff --git a/target-ppc/tran
From: Wanpeng Li
Commit 96193c22a "target-i386: Move xsave component mask to features array"
leverages features array to handle XCR0 processor state component bits,
however, it introduces a regression:
warning: host doesn't support requested feature: CPUID.0DH:EAX [bit 0]
warning: host doesn't
On Wed, Sep 21, 2016 at 8:03 AM, Paolo Bonzini wrote:
>
>
> On 21/09/2016 03:07, Ashish Mittal wrote:
>> +int32_t vxhs_qnio_iio_writev(void *qnio_ctx, uint32_t rfd, struct iovec
>> *iov,
>> +int iovcnt, uint64_t offset,
>> +
Le 28/09/2016 à 03:37, David Gibson a écrit :
On Tue, Sep 27, 2016 at 08:49:47PM +0200, Hervé Poussineau wrote:
Le 27/09/2016 à 06:11, David Gibson a écrit :
On Mon, Sep 26, 2016 at 10:23:24PM +0200, Hervé Poussineau wrote:
Signed-off-by: Hervé Poussineau
---
hw/intc/i8259.c | 37 +++
On Wed, Sep 28, 2016 at 3:58 AM, John Snow wrote:
>
>
> On 09/27/2016 12:53 PM, Ashijeet Acharya wrote:
>>
>> Fix a memory leak in ide_register_restart_cb() in hw/ide/core.c and add
>> idebus_unrealize() in hw/ide/qdev.c to have calls to
>> qemu_del_vm_change_state_handler() to deal with the dangl
This patch adds support for a new block device type called "vxhs".
Source code for the library that this code loads can be downloaded from:
https://github.com/MittalAshish/libqnio.git
Sample command line using JSON syntax:
./qemu-system-x86_64 -name instance-0008 -S -vnc 0.0.0.0:0 -k en-us -vg
Hello，recently I study qemu source code ,and I have some questions ,can you
help me ?
> 1、what is the meaning of queues in structure NICConf ? I think it is the
> number of queues to a NIC,and I do not where it is.
> 2、In NICConf init Function，I do not found it initulize the queues of
> NICC
On Tue, Sep 27, 2016 at 09:43:27AM +0200, Laurent Vivier wrote:
>
>
> On 27/09/2016 05:53, David Gibson wrote:
> > On Mon, Sep 26, 2016 at 04:10:49PM +0200, Laurent Vivier wrote:
>
> >> void qusb_pci_init_one(QPCIBus *pcibus, struct qhc *hc, uint32_t devfn,
> >> int bar)
> >> {
> >> hc->
On Tue, Sep 27, 2016 at 06:11:59AM -0400, Paolo Bonzini wrote:
>
> > I think we should keep it as it is, because Jason's patchset will only
> > support intel-iommu, not amd-iommu. For now, it won't have problem
> > (just like Intel IOMMU one). But after Jason's patch is merged, people
> > will be
On Tue, Sep 27, 2016 at 06:13:29AM -0400, Paolo Bonzini wrote:
>
> > Take my example: IOMMU unit test would want the guest to send DMA/IRQ
> > request from the device's perspective. In that case, we would like to
> > "tell" the pci-testdev about where to write the DMA, and what data to
> > write s
On Tue, 09/27 19:55, Roman Penyaev wrote:
> > The bug is 100% deterministic. Just boot up a guest with -drive
> > format=qcow2,aio=native.
>
> It turns out to be that everything is broken. I started all my
> tests with format=raw,aio=native and immediately got coroutine
> recursive. That is com
On Tue, Sep 27, 2016 at 08:55:58PM +0200, Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier
> ---
> tests/libqtest.h | 57
>
> 1 file changed, 57 insertions(+)
>
> diff --git a/tests/libqtest.h b/tests/libqtest.h
> index 4be1f77..4c47
On Tue, Sep 27, 2016 at 08:55:59PM +0200, Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier
> ---
> tests/Makefile.include| 8 +++-
> tests/libqos/usb.c| 2 +-
> tests/usb-hcd-uhci-test.c | 24
> 3 files changed, 24 insertions(+), 10 deletions(-)
>
On Tue, 09/27 16:18, Stefan Hajnoczi wrote:
> Commit 0ed93d84edabc7656f5c998ae1a346fe8b94ca54 ("linux-aio: process
> completions from ioq_submit()") added an optimization that processes
> completions each time ioq_submit() returns with requests in flight.
> This commit introduces a "Co-routine re-e
On Tue, 09/27 16:18, Stefan Hajnoczi wrote:
> Signed-off-by: Stefan Hajnoczi
> ---
> tests/test-coroutine.c | 42 ++
> 1 file changed, 42 insertions(+)
>
> diff --git a/tests/test-coroutine.c b/tests/test-coroutine.c
> index 6431dd6..abd97c2 100644
> --- a
On Tue, Sep 27, 2016 at 09:17:19AM +0200, Thomas Huth wrote:
> On 27.09.2016 06:17, David Gibson wrote:
> > On Mon, Sep 26, 2016 at 10:17:46PM +0200, Thomas Huth wrote:
> >> The firmware of the pseries machine, SLOF, is able to load files via
> >> IPv6 networking, too. So to test both, network boot
On Tue, Sep 27, 2016 at 07:54:37AM +0200, Cédric Le Goater wrote:
> On 09/27/2016 04:35 AM, David Gibson wrote:
> > On Mon, Sep 26, 2016 at 06:11:36PM +0200, Cédric Le Goater wrote:
> >> On 09/23/2016 04:46 AM, David Gibson wrote:
> >>> On Thu, Sep 22, 2016 at 10:25:59AM +0200, Cédric Le Goater wro
On Tue, Sep 27, 2016 at 08:49:47PM +0200, Hervé Poussineau wrote:
> Le 27/09/2016 à 06:11, David Gibson a écrit :
> > On Mon, Sep 26, 2016 at 10:23:24PM +0200, Hervé Poussineau wrote:
> > > Signed-off-by: Hervé Poussineau
> > > ---
> > > hw/intc/i8259.c | 37 +
On Tue, Sep 27, 2016 at 10:56:40PM +0300, Michael S. Tsirkin wrote:
> On Tue, Sep 27, 2016 at 11:11:58AM +0800, Yuanhan Liu wrote:
> > On Mon, Sep 26, 2016 at 10:24:55PM +0300, Michael S. Tsirkin wrote:
> > > On Mon, Sep 26, 2016 at 11:01:58AM -0700, Stephen Hemminger wrote:
> > > > I assume that i
On Tue, 09/27 16:18, Stefan Hajnoczi wrote:
> See the doc comments for a description of this new coroutine API.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> include/qemu/coroutine.h | 13 +
> util/qemu-coroutine.c| 5 +
> 2 files changed, 18 insertions(+)
>
> diff --git a/inc
John Snow writes:
> On 09/27/2016 02:56 PM, Dr. David Alan Gilbert (git) wrote:
>> From: "Dr. David Alan Gilbert"
>>
>> At the moment if you use a VMSTATE_*_EQUAL macro and the value
>> doesn't match you just get an error about the section that failed
>>
>> e.g.
>> qemu-system-ppc64: error whi
On 2016-09-28 0:40 GMT+08:00 Greg Kurz wrote:
>
> Talking about robustness was appropriate for your previous patches, but
> it does not really apply here since v9fs_iov_vunmarshal() does not have
> any issue with empty strings actually.
>
> I've changed the title to:
>
> 9pfs: allocate space for
On Wed, 09/28 01:54, Gonglei (Arei) wrote:
> What do you mean about the realpath? Can we use it to set the environment
> variable?
Basically just guess where QTEST_QEMU_BINARY is based on argv[0].
Fam
Alistair Francis writes:
> On Tue, Sep 27, 2016 at 8:40 AM, Markus Armbruster wrote:
>> Paolo Bonzini writes:
>>
>>> It does whatever cpu_physical_memory_write_rom (and hence
>>> cpu_memory_rw_debug, which has more callers) do.
>>>
What happens when you try to monkey-patch and address that
> -Original Message-
> From: Fam Zheng [mailto:f...@redhat.com]
> Sent: Wednesday, September 28, 2016 9:45 AM
> To: Gonglei (Arei)
> Cc: Daniel P. Berrange; pbonz...@redhat.com; John Snow;
> qemu-devel@nongnu.org; Wubin (H)
> Subject: Re: [Qemu-devel] [PATCH RFC] tests: Run qtest cases in
在 2016年09月12日 22:01, Stefan Hajnoczi 写道:
On Mon, Aug 15, 2016 at 05:32:19PM +0800, Changlong Xie wrote:
On 08/15/2016 04:37 PM, Kevin Wolf wrote:
Am 15.08.2016 um 03:49 hat Changlong Xie geschrieben:
On 08/09/2016 05:08 PM, Kevin Wolf wrote:
Am 27.07.2016 um 09:01 hat Changlong Xie geschriebe
On Wed, 09/28 01:31, Gonglei (Arei) wrote:
> # ./tests/virtio-net-test
> **
> ERROR:tests/libqtest.c:561:qtest_get_arch: assertion failed: (qemu != NULL)
> Aborted (core dumped)
>
> # ./tests/virtio-blk-test
> **
> ERROR:tests/libqtest.c:561:qtest_get_arch: assertion failed: (qemu != NULL)
> Abort
> -Original Message-
> From: Daniel P. Berrange [mailto:berra...@redhat.com]
> Sent: Tuesday, September 27, 2016 8:52 PM
> To: Gonglei (Arei)
> Cc: qemu-devel@nongnu.org
> Subject: Re: Questions about gcc linker errors in crypto sub-directory
>
> On Mon, Sep 26, 2016 at 09:19:36AM +, G
From: Paulina Szubarczyk
Copy data operated on during request from/to local buffers to/from
the grant references.
Before grant copy operation local buffers must be allocated what is
done by calling ioreq_init_copy_buffers. For the 'read' operation,
first, the qemu device invokes the read operati
t tags/xen-20160927-tag
for you to fetch changes up to b6eb9b45f7307638ff166401721ae6d0401e1d67:
qdisk - hw/block/xen_disk: grant copy implementation (2016-09-27 18:18:55
-0700)
Xen
On 28/09/16 10:22, Peter Maydell wrote:
> On 27 September 2016 at 16:49, Greg Ungerer wrote:
>> On 27/09/16 23:27, Laurent Vivier wrote:
>>> It is better because 166.67 MHZ is clearly a rounded value computed from
>>> the period: 10/600 = 166....
>>
>> Perhaps i
> -Original Message-
> From: Daniel P. Berrange [mailto:berra...@redhat.com]
> Sent: Tuesday, September 27, 2016 6:15 PM
> To: Fam Zheng
> Cc: Gonglei (Arei); pbonz...@redhat.com; John Snow; qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH RFC] tests: Run qtest cases in parallel
>
在 2016年09月12日 22:11, Stefan Hajnoczi 写道:
On Mon, Aug 08, 2016 at 03:50:27PM +0100, Stefan Hajnoczi wrote:
On Wed, Jul 27, 2016 at 03:01:41PM +0800, Changlong Xie wrote:
Block replication is a very important feature which is used for
continuous checkpoints(for example: COLO).
You can get the de
> -Original Message-
> From: Daniel P. Berrange [mailto:berra...@redhat.com]
> Sent: Tuesday, September 27, 2016 8:50 PM
> To: Gonglei (Arei)
> Cc: qemu-devel@nongnu.org; Wubin (H)
> Subject: Re: [PATCH v3 0/3] crypto: add ctr mode support and little
> inprovement
>
> On Tue, Sep 27, 20
> -Original Message-
> From: Stefan Hajnoczi [mailto:stefa...@gmail.com]
> Sent: Wednesday, September 28, 2016 12:27 AM
> To: Stefan Hajnoczi
> Cc: Gonglei (Arei); Cornelia Huck; qemu-devel@nongnu.org; Gerd Hoffmann;
> Wubin (H); m...@redhat.com
> Subject: Re: [Qemu-devel] Qtest virtio in
On 09/27/2016 04:32 PM, Alex Bennée wrote:
Richard Henderson writes:
On 09/27/2016 03:29 PM, Emilio G. Cota wrote:
What's a quick-and-dirty way to disable the fast-path TLB lookups?
Alex: you told me the monitor has an option for this, but I can't
find it. I'm looking for something that'd go
On 27 September 2016 at 16:49, Greg Ungerer wrote:
> On 27/09/16 23:27, Laurent Vivier wrote:
>> It is better because 166.67 MHZ is clearly a rounded value computed from
>> the period: 10/600 = 166....
>
> Perhaps it is, but again it is not documented that way.
The shipping default setting for the Freescale M5208EVB board is to run
the CPU at 166.67MHz. The current qemu emulation code for this board is
defaulting to 66MHz. This results in time appearing to run way to slowly.
So a "sleep 5" in a standard ColdFire Linux build takes almost 15
seconds in real
On 27/09/16 23:27, Laurent Vivier wrote:
> Le 27/09/2016 à 15:22, Greg Ungerer a écrit :
>> Hi Laurent,
>>
>> On 27/09/16 18:11, Laurent Vivier wrote:
>>> Le 27/09/2016 à 09:33, Thomas Huth a écrit :
On 27.09.2016 03:29, Greg Ungerer wrote:
> The shipping default setting for the Freescale
On 19 September 2016 at 01:24, Marc-André Lureau
wrote:
> tests/tcg/mmap test fails with values other than default target page
> size. When creating a map beyond EOF, extra anonymous pages are added up
> to the target page boundary. Currently, this operation is performed only
> when qemu_real_host
Add nios2 disassembler support. This patch is composed from binutils files
from commit "Opcodes and assembler support for Nios II R2". The files from
binutils used in this patch are:
include/opcode/nios2.h
include/opcode/nios2r1.h
include/opcode/nios2r2.h
opcodes/nios2-opc.c
op
From: Chris Wulff
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
Cc: Ley Foon Tan
Cc: Sandra Loosemore
Cc: Yves
Add the Altera 10M50 Nios2 GHRD model. This allows emulating the
10M50 development kit with the Nios2 GHRD loaded in the FPGA. It
is possible to boot Linux kernel and run userspace, thus far only
from initrd as storage support is not yet implemented.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc
Richard Henderson writes:
> On 09/27/2016 03:29 PM, Emilio G. Cota wrote:
>> What's a quick-and-dirty way to disable the fast-path TLB lookups?
>> Alex: you told me the monitor has an option for this, but I can't
>> find it. I'm looking for something that'd go in tcg/i386 to simply
>> bypass the
Add missing bits for qemu-user required for emulating Altera Nios2
userspace binaries.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
Cc: Ley Foon Tan
Cc: Sandra Loosemore
Cc: Yves Vandervennet
---
include/elf.h | 2 +
linux-user/elfload.c |
On 27 September 2016 at 13:12, Eduardo Habkost wrote:
> The following changes since commit 333ec4ca6a9f604331e2349cb91e9635f65d6462:
>
> Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into
> staging (2016-09-27 16:23:08 +0100)
>
> are available in the git repository at:
>
Add remaining bits of the Altera NiosII R1 support into qemu, which
is documentation, MAINTAINERS file entry, configure bits, arch_init
and configuration files for both linux-user (userland binaries) and
softmmu (hardware emulation).
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
From: Chris Wulff
Add the Altera Nios2 internal interrupt controller model.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
Cc: Ley Foon Tan
Cc: Sandra Loosemore
Cc: Yves Vandervennet
---
hw/intc/Makefile.objs | 1 +
hw/intc/nios2_iic.c | 103 +
From: Chris Wulff
Add the Altera timer model.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
Cc: Ley Foon Tan
Cc: Sandra Loosemore
Cc: Yves Vandervennet
---
hw/timer/Makefile.objs | 1 +
hw/timer/altera_timer.c | 236
2 fil
On Tue, 27 Sep 2016 11:11:58 +0800
Yuanhan Liu wrote:
> On Mon, Sep 26, 2016 at 10:24:55PM +0300, Michael S. Tsirkin wrote:
> > On Mon, Sep 26, 2016 at 11:01:58AM -0700, Stephen Hemminger wrote:
> > > I assume that if using Version 1 that the bit will be ignored
>
> Yes, but I will just quot
On 09/27/2016 03:29 PM, Emilio G. Cota wrote:
What's a quick-and-dirty way to disable the fast-path TLB lookups?
Alex: you told me the monitor has an option for this, but I can't
find it. I'm looking for something that'd go in tcg/i386 to simply
bypass the fast path.
There is no easy way. If y
Emilio G. Cota writes:
> On Tue, Sep 27, 2016 at 18:16:45 +0200, Paolo Bonzini wrote:
>> Anyhow, the next step is to merge either cmpxchg-based atomics
>> or iothread-free single-threaded TCG. Either will do. :)
>>
>> I think that even iothread-free single-threaded TCG requires this
>> TLB stuf
On Tue, Sep 27, 2016 at 18:16:45 +0200, Paolo Bonzini wrote:
> Anyhow, the next step is to merge either cmpxchg-based atomics
> or iothread-free single-threaded TCG. Either will do. :)
>
> I think that even iothread-free single-threaded TCG requires this
> TLB stuff, because the iothread's addres
On 09/27/2016 12:53 PM, Ashijeet Acharya wrote:
Fix a memory leak in ide_register_restart_cb() in hw/ide/core.c and add
idebus_unrealize() in hw/ide/qdev.c to have calls to
qemu_del_vm_change_state_handler() to deal with the dangling change
state handler during hot-unplugging ide devices which
Paolo Bonzini writes:
> On 02/08/2016 08:37, Alex Bennée wrote:
>>> - in notdirty_mem_write, care must be put in the ordering of
>>> tb_invalidate_phys_page_fast (which itself calls tlb_unprotect_code and
>>> takes the tb_lock in tb_invalidate_phys_page_range) and tlb_set_dirty.
>>> At least it
On 09/27/2016 05:10 PM, Eric Blake wrote:
> On 09/27/2016 08:13 AM, Daniel P. Berrange wrote:
>> The input_visitor_test_add() method was accepting an instance
>> of 'TestInputVisitorData' and passing it as the 'user_data'
>> parameter to test functions. The main 'TestInputVisitorData'
>> instance t
On 09/27/2016 08:13 AM, Daniel P. Berrange wrote:
> The input_visitor_test_add() method was accepting an instance
> of 'TestInputVisitorData' and passing it as the 'user_data'
> parameter to test functions. The main 'TestInputVisitorData'
> instance that was actually used, was meanwhile being alloc
On 09/27/2016 08:13 AM, Daniel P. Berrange wrote:
> Allow tracing of the operation of visitors
Ooooh, shiny!
>
> Signed-off-by: Daniel P. Berrange
> ---
> Makefile.objs | 1 +
> qapi/qapi-visit-core.c | 27 +++
> qapi/trace-events | 33 +++
On 09/27/2016 08:13 AM, Daniel P. Berrange wrote:
> If given an option string such as
>
> size=1024,nodes=10,nodes=4-5,nodes=1-2,policy=bind
>
> the qemu_opts_to_qdict() method will currently overwrite
> the values for repeated option keys, so only the last
> value is in the returned dict:
>
>
- Original Message -
> From: "Radim Krčmář"
> To: "Paolo Bonzini"
> Cc: qemu-devel@nongnu.org, "Peter Xu" , "Igor Mammedov"
> , "Richard Henderson"
> , "Eduardo Habkost" , "Michael S.
> Tsirkin"
> Sent: Tuesday, September 27, 2016 4:01:39 PM
> Subject: Re: [PATCH 5/5] intel_iommu: do
This multiply has one signed input and one unsigned input,
producing the full double-width result.
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 43 +++
tcg/tcg-op.h | 4
2 files changed, 47 insertions(+)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op
While reviewing the recent riscv patch set, I made a suggestion to copy
some of the bits from tcg_gen_muls2_i64 in order to implement the mulhsu
instruction.
However, I noticed that the same operation is present in another target,
so I thought that it would be better to have this as a standard ope
Use tcg_gen_mul_tl for muli and mul instructions.
Use tcg_gen_muls2_tl for mulh instruction.
Use tcg_gen_mulu2_tl for mulhu instruction.
Use tcg_gen_mulsu2_tl for mulhsu instruction.
Note that this last fixes a bug, in that mulhsu was
previously treating both operands as signed, instead
of treatin
On 09/27/2016 08:13 AM, Daniel P. Berrange wrote:
> The qdict_flatten() method will take a dict whose elements are
> further nested dicts/lists and flatten them by concatenating
> keys.
>
> The qdict_crumple() method aims to do the reverse, taking a flat
> qdict, and turning it into a set of neste
On 09/27/2016 02:56 PM, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
At the moment if you use a VMSTATE_*_EQUAL macro and the value
doesn't match you just get an error about the section that failed
e.g.
qemu-system-ppc64: error while loading state for instance 0x0 of
On 09/27/2016 10:51 PM, Eduardo Habkost wrote:
> On Thu, Sep 22, 2016 at 02:49:35PM -0500, Corey Minyard wrote:
>> On 09/22/2016 01:42 PM, Eduardo Habkost wrote:
> [...]
>>> In the case of the inject-nmi QMP command, I need to understand
>>> what "default CPU" is supposed to mean in the inject-nmi
On Tue, Sep 27, 2016 at 02:24:22PM -0400, James Hanley wrote:
> > On Sep 27, 2016, at 2:16 PM, Jeff Cody wrote:
> >
> >> On Tue, Sep 27, 2016 at 12:17:31PM -0400, James Hanley wrote:
> >> Well - it's acting differently... It just hangs now...
> >
> > Let it run a bit longer, it most likely is
Emilio G. Cota writes:
> On Thu, Sep 22, 2016 at 11:13:14 +0100, Alex Bennée wrote:
>> ThreadSanitizer detects a possible race between reading/writing the
>> hashes. As ordering semantics are already documented for qht we just
>> need to ensure a race can't tear the hash value so we can use the
On Thu, Sep 22, 2016 at 02:49:35PM -0500, Corey Minyard wrote:
> On 09/22/2016 01:42 PM, Eduardo Habkost wrote:
[...]
> > In the case of the inject-nmi QMP command, I need to understand
> > what "default CPU" is supposed to mean in the inject-nmi
> > documentation. Maybe it can be changed to use th
The global variables are not necessary because we can check KVM
feature flags in X86CPU directly.
Reviewed-by: Paolo Bonzini
Signed-off-by: Eduardo Habkost
---
target-i386/kvm.c | 21 ++---
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/target-i386/kvm.c b/target
The global variable is not necessary because we can check
cpu->hyperv_time directly.
We just need to ensure cpu->hyperv_time will be cleared if the
feature is not really being exposed to the guest due to missing
KVM_CAP_HYPERV_TIME capability.
Reviewed-by: Paolo Bonzini
Signed-off-by: Eduardo Ha
This will reuse the existing check/enforce logic in
x86_cpu_filter_features() to check the xsave component bits
against GET_SUPPORTED_CPUID.
Reviewed-by: Richard Henderson
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 42 --
target-i386/cpu.h |
The global variable is not necessary because we can check
cpu->hyperv_vapic directly.
Reviewed-by: Paolo Bonzini
Signed-off-by: Eduardo Habkost
---
target-i386/kvm.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 5118562..
Move the xsave area size calculation from cpu_x86_cpuid() inside
its own function. While doing it, change it to use the XSAVE area
struct sizes for the initial size, instead of the magic 0x240
number.
Reviewed-by: Richard Henderson
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 22 +
From: David Gibson
Functions of type FindSysbusDeviceFunc currently return an integer.
However, this return value is always ignored by the caller in
find_sysbus_device().
This changes the function type to return void, to avoid confusion over
the function semantics.
Signed-off-by: David Gibson
1 - 100 of 433 matches
Mail list logo
