Manipulate data and store 8bytes instead of 4bytes.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate/vsx-impl.inc.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.
Being a 16byte operation, qemu_ld/st still does not support this. Move
this out so other store operation can use qemu_ld/st in the following
patch. Also, convert it to two MO_Q operations for stqcx.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 69
stxsibx - Store VSX Scalar as Integer Byte Indexed
stxsihx - Store VSX Scalar as Integer Halfword Indexed
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 3 +++
target-ppc/translate/vsx-ops.inc.c | 2 ++
3 files changed, 7 i
lxsibzx - Load VSX Scalar as Integer Byte & Zero Indexed
lxsihzx - Load VSX Scalar as Integer Halfword & Zero Indexed
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 2 ++
target-ppc/translate/vsx-ops.inc.c | 2 ++
3 files c
Use macro for ld64 as well, this changes the function signature from
gen_qemu_ld64 => gen_qemu_ld64_i64. Replace this at all the call sites.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 39 +++---
target-ppc/translate/fp-impl.inc.c | 42
Use tcg_gen_qemu_ld in the load with reservation instructions.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 60668c2..72e78ff 100644
--
Use tcg_gen_qemu_st store conditional instructions.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 58 +-
1 file changed, 24 insertions(+), 34 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 618fe43..
xxspltib: VSX Vector Splat Immediate Byte
Copy the immediate byte in each byte of target VSR
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 20
target-ppc/translate/vsx-ops.inc.c | 5 +
3 files c
Implement macro to consolidate store operations using newer
tcg_gen_qemu_st function.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 35 ---
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translat
Make byte-swap routines use the common GEN_QEMU_LOAD macro
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 32 ++--
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 254ad40..60668c2 100
1) Consolidate Load/Store operations using tcg_gen_qemu_ld/st functions
2) This series contains 10 new instructions for POWER9 ISA3.0
Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x.
Patches:
01-09: Cleanup load/store operations in ppc translator
10: xxspltib: VSX
Make byte-swap routines use the common GEN_QEMU_LOAD macro
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 27 ++-
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d36d45e..0d27067 100644
-
Implement macro to consolidate store operations using newer
tcg_gen_qemu_ld functions.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 58 +-
1 file changed, 20 insertions(+), 38 deletions(-)
diff --git a/target-ppc/translate.c b/tar
kvm_setup_guest_memory only does "madvise to QEMU_MADV_DONTFORK" and
is only called by ram_block_add, which actually is duplicate code.
Bonus: add simple comment for kvm_has_sync_mmu to make life easier.
Suggested-by: Paolo Bonzini
Signed-off-by: Cao jin
---
v2 changelog:
1. Fix building failur
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 1473591360-13163-1-git-send-email-caoj.f...@cn.fujitsu.com
Subject: [Qemu-devel] [PATCH] kvm-all: dro
Benjamin Herrenschmidt writes:
> On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote:
>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
>> index 5026804..d96ff66 100644
>> --- a/target-ppc/translate.c
>> +++ b/target-ppc/translate.c
>> @@ -4448,6 +4448,7 @@ static void gen_tl
Benjamin Herrenschmidt writes:
> On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote:
>> PowerPC targets should do tlb invalidation on other cpus on
>> instructions that expect a global effect.
>>
>> * ptesync for BookS
>> * tlbsync primarily for BookE
>> (for BookS make it a nop, as i
Benjamin Herrenschmidt writes:
> On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote:
>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
>> index 5026804..d96ff66 100644
>> --- a/target-ppc/translate.c
>> +++ b/target-ppc/translate.c
>> @@ -4448,6 +4448,7 @@ static void gen_tl
On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote:
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 5026804..d96ff66 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -4448,6 +4448,7 @@ static void gen_tlbie(DisasContext *ctx)
> #if defined(CO
On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote:
> PowerPC targets should do tlb invalidation on other cpus on
> instructions that expect a global effect.
>
> * ptesync for BookS
> * tlbsync primarily for BookE
> (for BookS make it a nop, as it always come along with ptesync)
> * tlb
On Mon, Sep 12, 2016 at 11:17:37AM +1000, David Gibson wrote:
[...]
> > I think now I understand the point... Then I'd prefer to use David's
> > suggestion. A single notify_changed() looks cleaner. To be more
> > explicit, I would prefer to rename it to notifier_flag_changed(),
> > since notify_c
tlbie (H_REMOVE, H_PROTECT and H_BULK_REMOVE for pseries) should have a
global effect.
Introduces TLB_NEED_GLOBAL_FLUSH flag. During delayed flush, once taking
care of local flush, check broadcast flush(ptesync, tlbsync, etc) is
needed. Depending on the bitmask state of the tlb_need_flush, tlb is
Signed-off-by: Nikunj A Dadhania
---
target-ppc/cpu.h | 1 +
target-ppc/helper_regs.h | 4 ++--
target-ppc/mmu-hash64.c | 4 ++--
target-ppc/mmu_helper.c | 6 +++---
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 1e808c8..7dc
The flag will be used to indicate whether broadcast tlb flush is needed
or not.
Moreover, BookS does both ptesync and tlbsync, so make that a nop for
the server and tlbsync would generate a check flush for BookE
Signed-off-by: Nikunj A Dadhania
---
hw/ppc/spapr_hcall.c | 4 ++--
target-ppc
PowerPC targets should do tlb invalidation on other cpus on
instructions that expect a global effect.
* ptesync for BookS
* tlbsync primarily for BookE
(for BookS make it a nop, as it always come along with ptesync)
* tlbivax for other ppc tragets
* H_REMOVE, H_BULK_REMOVE and H_PROTECT hcalls
On Fri, Sep 09, 2016 at 07:05:04PM +0200, Markus Armbruster wrote:
[...]
> You effectively propose to revise this coding rule from error.h:
>
> * Please don't error_setg(&error_fatal, ...), use error_report() and
> * exit(), because that's more obvious.
> * Likewise, don't error_setg(&error_a
On Mon, Sep 12, 2016 at 11:26:04AM +1000, David Gibson wrote:
> On Thu, Sep 08, 2016 at 05:07:32PM +0800, Peter Xu wrote:
> > On Wed, Sep 07, 2016 at 04:41:54PM +1000, David Gibson wrote:
> > > On Wed, Sep 07, 2016 at 02:34:19PM +0800, Peter Xu wrote:
> > > > On Wed, Sep 07, 2016 at 03:44:19PM +100
On 09/10/2016 03:55 AM, Kirti Wankhede wrote:
> On 9/10/2016 12:12 AM, Alex Williamson wrote:
>> On Fri, 9 Sep 2016 23:18:45 +0530
>> Kirti Wankhede wrote:
>>
>>> On 9/8/2016 1:39 PM, Jike Song wrote:
On 08/25/2016 11:53 AM, Kirti Wankhede wrote:
>>>
> +---+
> |
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 147342618684.13303.1583142856242164602.st...@fimbulvetr.bsc.es
Subject: [Qemu-devel] [RFC PATCH v2 0/6] translate: [tcg] Generic translation
framework
=== TEST SCRIPT BEGIN
Benjamin Herrenschmidt writes:
> On Fri, 2016-09-09 at 18:44 +0530, Nikunj A Dadhania wrote:
>> +static inline void tlb_clear_flag(CPUState *cs)
>> +{
>> + PowerPCCPU *cpu = POWERPC_CPU(cs);
>> + CPUPPCState *env = &cpu->env;
>> +
>> + env->tlb_need_flush = 0;
>> +}
>
> What is the point
On Thu, Sep 08, 2016 at 09:00:07PM +0200, Laurent Vivier wrote:
> Add a first test to validate the protocol:
>
> - rtas/get-time-of-day compares the time
> from the guest with the time from the host.
>
> Signed-off-by: Laurent Vivier
> ---
> v6:
> - rebase
>
> v5:
> - use qtest_spapr_boot() i
On Thu, Sep 08, 2016 at 09:00:06PM +0200, Laurent Vivier wrote:
> Define spapr_alloc_init()/spapr_alloc_init_flags()/spapr_alloc_uninit()
>
> to allocate and use SPAPR guest memory
>
> Define qtest_spapr_vboot()/qtest_spapr_boot()/qtest_spapr_shutdown()
>
> to start SPAPR guest with QOSState
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 147342618684.13303.1583142856242164602.st...@fimbulvetr.bsc.es
Subject: [Qemu-devel] [RFC PATCH v2 0/
On Sat, Sep 10, 2016 at 09:03:56AM +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2016-09-09 at 18:44 +0530, Nikunj A Dadhania wrote:
> > +static inline void tlb_clear_flag(CPUState *cs)
> > +{
> > + PowerPCCPU *cpu = POWERPC_CPU(cs);
> > + CPUPPCState *env = &cpu->env;
> > +
> > + env->tl
When I try to run QEMU on Ubuntu Mate, I see these error messages:
pulseaudio: set_sink_input_volume() failed
pulseaudio: Reason: Invalid argument
pulseaudio: set_sink_input_mute() failed
pulseaudio: Reason: Invalid argument
Trying to play an audio file in the guest fails. The guest freezes for a
On Thu, Sep 08, 2016 at 09:56:31AM +0530, Bharata B Rao wrote:
> On Thu, Sep 08, 2016 at 11:51:32AM +1000, David Gibson wrote:
> > On Fri, Sep 02, 2016 at 03:06:38PM +0530, Bharata B Rao wrote:
> > > Each spapr cpu core type defines an instance_init routine which just
> > > populates the CPU class
On Wed, Aug 03, 2016 at 10:38:51PM +1000, Benjamin Herrenschmidt wrote:
> There were a number of bugs in the implementation:
>
> - The structure alignment was wrong for 64-bit.
>
> - Also 64-bit only does RT signals.
>
> - On 64-bit, we need to put a pointer to the (aligned) vector registers
Ejected devices cannot complete the IO, so we can fail it early.
This is also a fix to a crash for dataplane in that case, since the
assert(blk_get_aio_context(d->conf.blk) == s->ctx);
below won't hold because blk_get_aio_context will return qemu_aio_ctx
for ejected devices, where as s->ctx
On Tue, Sep 06, 2016 at 10:34:05AM +0530, Rajalakshmi Srinivasaraghavan wrote:
> This series contains 14 new instructions for POWER9 described in ISA3.0.
>
> Patches:
> 01: Adds vector insert instructions.
> vinsertb - Vector Insert Byte
> vinserth - Vector Insert H
On Thu, Sep 08, 2016 at 09:32:42AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> Power ISA 2.x has deleted the rfi instruction and rfid shoud be used
> instead on cpus following this instruction set or later.
>
> This will raise an invalid exception when rfi is used on such
>
On Fri, Sep 09, 2016 at 02:31:55PM +0200, Laurent Vivier wrote:
>
>
> On 09/09/2016 14:25, Greg Kurz wrote:
> > On Thu, 8 Sep 2016 09:50:31 +0200
> > Laurent Vivier wrote:
> >
> >> On 08/09/2016 04:04, David Gibson wrote:
> >>> On Tue, Sep 06, 2016 at 03:17:56PM +0200, Laurent Vivier wrote:
>
On Wed, Sep 07, 2016 at 08:13:31AM +0100, Alex Bennée wrote:
>
> David Gibson writes:
>
> > On Wed, Sep 07, 2016 at 10:17:42AM +0530, Nikunj A Dadhania wrote:
> >> David Gibson writes:
> >>
> >> > [ Unknown signature status ]
> >> > On Fri, Sep 02, 2016 at 12:02:55PM +0530, Nikunj A Dadhania wr
On Mon, Sep 05, 2016 at 10:03:36PM +0200, Thomas Huth wrote:
> There are some powerpc related files in the QEMU source tree
> which are currently not covered by the MAINTAINERS file and
> thus not properly classified by the get_maintainer.pl script.
> So let's add them to the proper sections.
>
>
On Thu, Sep 08, 2016 at 05:07:32PM +0800, Peter Xu wrote:
> On Wed, Sep 07, 2016 at 04:41:54PM +1000, David Gibson wrote:
> > On Wed, Sep 07, 2016 at 02:34:19PM +0800, Peter Xu wrote:
> > > On Wed, Sep 07, 2016 at 03:44:19PM +1000, David Gibson wrote:
> > > > > For "CHANGE", it sounds like a unmap(
On Thu, Sep 08, 2016 at 06:22:40PM +0800, Peter Xu wrote:
> On Wed, Sep 07, 2016 at 12:54:23PM +0200, Paolo Bonzini wrote:
> >
> >
> > On 07/09/2016 08:05, David Gibson wrote:
> > > On Wed, Sep 07, 2016 at 01:32:23PM +0800, Peter Xu wrote:
> > >> Considering that we may have multiple IOMMU notifi
> On 14 June 2016 at 14:43, Xuetao Guan wrote:
>>> On 20 May 2016 at 13:48, Riku Voipio wrote:
On torstaina 12. toukokuuta 2016 17.34.42 EEST, Peter Maydell wrote:
> We should either fix our unicore32 support to use the real
> syscall numbers, or just drop it; since nobody has touche
Matthew Garrett wrote on 08/17/2016 03:48:52 PM:
> From: Matthew Garrett
> To: qemu-devel@nongnu.org
> Cc: dgilb...@redhat.com, berra...@redhat.com, Stefan Berger/Watson/
> IBM@IBMUS, Matthew Garrett
> Date: 08/17/2016 03:49 PM
> Subject: [PATCH v4] hw/misc: Add simple measurement hardware
>
>
On 2016-09-09 20:20, Michael S. Tsirkin wrote:
> On Wed, Aug 31, 2016 at 07:17:39PM +0300, David Kiarie wrote:
>> Hi all,
>>
>> This patchset adds basic AMD IOMMU emulation support to Qemu.
>
> Jan, Igor, any comments on this one?
> I suspect it's time we merged this and followed-up upstream.
>
On 14 June 2016 at 14:43, Xuetao Guan wrote:
>> On 20 May 2016 at 13:48, Riku Voipio wrote:
>>> On torstaina 12. toukokuuta 2016 17.34.42 EEST, Peter Maydell wrote:
We should either fix our unicore32 support to use the real
syscall numbers, or just drop it; since nobody has touched
Signed-off-by: Alistair Francis
---
As the migration framework is not included in user mode this needs to be a
new file.
V7:
- Use the standard QEMU init/realise functions
V6:
- Make the OR IRQ device a TYPE_DEVICE
- Add vmstate
hw/core/Makefile.objs | 1 +
hw/core/or-irq.c | 117
Add the STM32F2xx SPI device.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Maydell
---
V4:
- Add VMState
- Small fixes
V2:
- Address Peter C's comments
default-configs/arm-softmmu.mak | 1 +
hw/ssi/Makefile.objs| 1 +
hw/ssi/stm32f2xx_spi.c | 225 +
Connect the ADC devices to the STM32F205 SoC.
Signed-off-by: Alistair Francis
---
V7:
- Create the new ADC device
V5:
- Use the new irq ORing function
V4:
- Connect all the interrupt lines correctly
V2:
- Fix up the device/devices commit message
hw/arm/stm32f205_soc.c | 36 +
Add Alistair Francis as the maintainer for the Netduino 2
and SMM32F205 SoC.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
MAINTAINERS | 15 +++
1 file changed, 15 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b6fb84e..ea10510 100644
--- a/MAINTAI
Cleanup the individual DeviceState and SysBusDevice
variables to re-use the same variable for each
device.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
hw/arm/stm32f205_soc.c | 35 +--
1 file changed, 17 insertions(+), 18 deletions(-)
diff
If correctly configured allow the STM32F2xx timer to print
out the PWM duty cycle information.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
V3:
- Use OR instead of + for masking
- Improve clarity of print statement
V2:
- Fix up if statement braces
- Remove stm32f2xx_tim
Connect the SPI devices to the STM32F205 SoC.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
V2:
- Fix up the device/devices commit message
hw/arm/stm32f205_soc.c | 22 ++
include/hw/arm/stm32f205_soc.h | 3 +++
2 files changed, 25 insertions(+
Add the STM32F2xx ADC device. This device randomly
generates values on each read.
This also includes creating a hw/adc directory.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Maydell
---
V4:
- Remove the rand() function
- Add VMState
- Small cleanups
V2:
- Address Peter C's comments
This patchset continues with the Netduino 2 and STM32F205 SoC
work.
This patch series makes a small change to the STM32F2xx
SoC to tidy up the code.
Next a feature is added to the STM32F2xx timer to display the
PWM duty cycle, when debugging is enabled.
Then the STM32F2xx SPI and ADC devices are
> get_maintainer.pl now properly recognizes that the file in
> include/hw/unicore32/ belongs to UniCore32.
>
> Signed-off-by: Thomas Huth
Looks ok to me.
Acked-by: Guan Xuetao
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9d17cb3
kvm_setup_guest_memory only does "madvise to QEMU_MADV_DONTFORK" and
is only called by ram_block_add, which actually is duplicate code.
Bonus: add simple comment for kvm_has_sync_mmu to make life easier.
Suggested-by: Paolo Bonzini
Signed-off-by: Cao jin
---
exec.c | 4 +---
incl
On 09/09/2016 08:47 PM, Michael S. Tsirkin wrote:
On Fri, Sep 09, 2016 at 08:00:31PM +0300, Marcel Apfelbaum wrote:
On 09/09/2016 04:10 PM, Maxime Coquelin wrote:
This patch adds virtio_test_backend_virtio_1() function to
check whether backend supports VIRTIO_F_VERSION_1 before the
negociation
I retried with ubuntu 16.04, qemu-img version 2.5.0 (Debian 1:2.5+dfsg-
5ubuntu10.4).
While the original file (freetz vmdk) is not available (they use .ova now), I
got another .vmdk file from
http://www.osboxes.org/debian/#debian-8-5-vmware
qemu-img convert Debian\ 8.5\ \(64bit\).vmdk -O raw tes
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