On 2016年09月05日 09:26, Michael S. Tsirkin wrote:
On Mon, Sep 05, 2016 at 09:24:37AM +0800, Wei Xu wrote:
Looks this patch includes quite a few misc changes from upstream, it's a bit
confused to find out which one is related to virtio/vhost dmar support,
while the upstream header shows a separat
On 2016年09月06日 13:49, Peter Xu wrote:
On Tue, Sep 06, 2016 at 03:06:17PM +1000, David Gibson wrote:
On Mon, Sep 05, 2016 at 03:21:18PM +0800, Peter Xu wrote:
In the thread:
https://lists.gnu.org/archive/html/qemu-devel/2016-09/msg00254.html
Alex proposed a way for vhost DMAR to be enable
On Tue, Sep 06, 2016 at 03:12:26PM +1000, David Gibson wrote:
> > /**
> > @@ -611,9 +613,11 @@ uint64_t
> > memory_region_iommu_get_min_page_size(MemoryRegion *mr);
> > * @entry: the new entry in the IOMMU translation table. The entry
> > * replaces all old entries for the same virtu
On Mon, Sep 05, 2016 at 03:21:20PM +0800, Peter Xu wrote:
> When there are active IOMMU notify registers, the iommu_notify_flag will
> cache existing notify flag. When notifiers are triggered, flag will be
> checked against the cached result.
>
> Signed-off-by: Peter Xu
> ---
> hw/ppc/spapr_iomm
On Tue, 2016-09-06 at 10:23 +0530, Nikunj A Dadhania wrote:
> >
> > No there isn't. You can start qemu with --smp 4 and have 4 CPUs.
>
> That case was prevented to even start in case of TCG. That is why I had
> to add "target-ppc: with MTTCG report more threads"
No, it works, you are confusing co
On 09/05/2016 06:27 AM, David Gibson wrote:
> On Wed, Aug 31, 2016 at 06:34:15PM +0200, Cédric Le Goater wrote:
>> On PowerNV, CPU ids start at 0x8 or 0x20, we don't have a CPU 0
>> anymore. So let's use the first_cpu index to initialize the monitor.
>>
>> Signed-off-by: Cédric Le Goater
>
> So w
On Mon, Sep 05, 2016 at 04:38:04PM +0800, Peter Xu wrote:
> On Mon, Sep 05, 2016 at 10:04:42AM +0200, Paolo Bonzini wrote:
> >
> >
> > On 05/09/2016 09:21, Peter Xu wrote:
> > > void memory_region_notify_iommu(MemoryRegion *mr,
> > > -IOMMUTLBEntry entry)
> > > +
The following vector extract instructions are added from ISA 3.0.
vextractub - Vector Extract Unsigned Byte
vextractuh - Vector Extract Unsigned Halfword
vextractuw - Vector Extract Unsigned Word
vextractd - Vector Extract Unsigned Doubleword
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
tar
On 09/06/2016 02:49 AM, David Gibson wrote:
> On Mon, Sep 05, 2016 at 06:28:10PM +1000, Benjamin Herrenschmidt wrote:
>> On Mon, 2016-09-05 at 09:41 +0200, Cédric Le Goater wrote:
>>> yeah. I have not found a clear definition of all the bits.
>>>
>>> I will try to make a macro with what I can colle
The following vector count trailing zeros instructions are
added from ISA 3.0.
vctzb - Vector Count Trailing Zeros Byte
vctzh - Vector Count Trailing Zeros Halfword
vctzw - Vector Count Trailing Zeros Word
vctzd - Vector Count Trailing Zeros Doubleword
Signed-off-by: Rajalakshmi Srinivasaraghavan
On 09/05/2016 06:02 AM, David Gibson wrote:
> On Wed, Aug 31, 2016 at 06:34:13PM +0200, Cédric Le Goater wrote:
>> This is largy inspired by sPAPRCPUCore with some simplification, no
>> hotplug for instance. But the differences are small and the objects
>> could possibly be merged.
>>
>> A set of P
From: Thomas Huth
Some of the machines that we have got a firmware image for write
some output to the serial console while booting up. We can use
this output to make sure that the machine is basically working,
so this adds a test that checks the output of these machines
for some well-known "magic
On Tue, Sep 06, 2016 at 03:18:46PM +1000, David Gibson wrote:
> > Maybe here naming the flags as IOMMU_{RW_NONE} is a little bit
> > confusing (just to leverage existing access flags), but what I was
> > trying to do is to make the two things not overlapped at all, since I
> > didn't find a mixture
On 2016年09月05日 10:26, Wei Xu wrote:
On 2016年08月30日 11:06, Jason Wang wrote:
@@ -1587,6 +1595,11 @@ static void
virtio_pci_device_plugged(DeviceState *d, Error **errp)
}
if (legacy) {
+if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
+error_setg(er
From: Benjamin Herrenschmidt
Mostly turn "store" type of helpers into TCG_CALL_NO_WG because
they can take exceptions. Also fixup_thrm doesn't read nor write
the tracked environment.
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-p
On Tue, Sep 06, 2016 at 03:06:17PM +1000, David Gibson wrote:
> On Mon, Sep 05, 2016 at 03:21:18PM +0800, Peter Xu wrote:
> > In the thread:
> >
> > https://lists.gnu.org/archive/html/qemu-devel/2016-09/msg00254.html
> >
> > Alex proposed a way for vhost DMAR to be enabled without breaking
> >
From: Swapnil Bokade
Adds following instructions:
vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
vcmpnezw[.]: Vector Compare Not Equal or Zero Word
Signed-off-by: Swapnil Bokade
[ collapse switch case ]
Signed-off-by: Nikunj A Dadhania
From: Laurent Vivier
Since kernel v4.0, linux uses H_CHANGE_LOGICAL_LAN_MAC to change lively
the MAC address of an ibmveth interface.
As QEMU doesn't implement this h_call, we can't change anymore the
MAC address of an spapr-vlan interface.
Signed-off-by: Laurent Vivier
Signed-off-by: David Gi
From: Benjamin Herrenschmidt
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 1205 +---
target-ppc/translate/fp-impl.c | 1098
tar
On Mon, Sep 05, 2016 at 03:21:18PM +0800, Peter Xu wrote:
> In the thread:
>
> https://lists.gnu.org/archive/html/qemu-devel/2016-09/msg00254.html
>
> Alex proposed a way for vhost DMAR to be enabled without breaking
> existing protections on vIOMMU and device assignments. This series
> tried t
From: Benjamin Herrenschmidt
Those helpers never load from or store to the TCG tracked environment,
not do they generate synchronous exceptions (they might generate an
asynchronous interrupt but that's not an issue here).
So we can make them all use TCG_CALL_NO_RWG
Signed-off-by: Benjamin Herre
From: Vivek Andrew Sha
vslv: Vector Shift Left Variable
Signed-off-by: Vivek Andrew Sha
Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 14 +++
From: Benjamin Herrenschmidt
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 994 +---
target-ppc/translate/vsx-impl.c | 721 +
target-ppc
Add vbpermd instruction from ISA 3.0.
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/helper.h |1 +
target-ppc/int_helper.c | 20
target-ppc/translate/vmx-impl.inc.c |1 +
target-ppc/translate/vmx-ops.inc.c |1 +
4 file
From: Benjamin Herrenschmidt
Use a single translate when not crossing a page boundary and avoid
going through layers of helpers. MacOS uses those instructions
a lot, so does OpenBIOS.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/mem_helper.c | 69 ++
From: Benjamin Herrenschmidt
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 1068 +--
target-ppc/translate/vmx-impl.c | 829 ++
target-p
This series contains 14 new instructions for POWER9 described in ISA3.0.
Patches:
01: Adds vector insert instructions.
vinsertb - Vector Insert Byte
vinserth - Vector Insert Halfword
vinsertw - Vector Insert Word
vinsertd - Vector Insert Doub
From: Benjamin Herrenschmidt
We were one instruction off
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ac2c79b..bc5b
Benjamin Herrenschmidt writes:
> On Tue, 2016-09-06 at 07:25 +0530, Nikunj A Dadhania wrote:
>> > Benjamin Herrenschmidt writes:
>>
>> >
>> > On Sun, 2016-09-04 at 18:00 +0100, Alex Bennée wrote:
>> >
>> > >
>> > > When is the synchronisation point? On ARM we end the basic block on
>> > > sy
From: Cédric Le Goater
The exact same routine will be used in PowerNV.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/Makefile.objs | 2 +-
hw/ppc/fdt.c | 49 +
hw/ppc/spapr.c | 36 +
From: Nikunj A Dadhania
While implementing modulo instructions figured out that the
implementation uses many branches. Change the logic to achieve the
branch-less code. Undefined value is set to dividend in case of invalid
input.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
On Mon, Sep 05, 2016 at 11:56:12AM +0200, Paolo Bonzini wrote:
> Yeah, if you really want to have these semantics, you need to define an
> enum like this:
>
> IOMMU_NOTIFIER_NONE = -1,
> IOMMU_NOTIFIER_FLUSH = 0,
> IOMMU_NOTIFIER_CHANGED_ENTRY = 1,
>
> But I'm still not convinc
From: Benjamin Herrenschmidt
The current alignment exception generation tries to load the opcode
to put in DSISR from a context where a cpu_ldl_code() is really not
a good idea. It might fault and longjmp out and that's not something
we want happening here.
Instead, pass the releavant opcode bit
From: Benjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve
the return address when needed.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/mmu_helper.c | 12 ++--
target-ppc/translate.c | 1 -
2 files changed, 6 in
From: Benjamin Herrenschmidt
Move the NIP update to after the conditional branch so that we
don't do it if we aren't going to take the alignment exception
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 de
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/66] ppc-for-2.8 queue 20160906
Type: series
Message-id: 1473133253-17598-1-git-send-email-da...@gibson.dropbear.id.au
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n
From: Benjamin Herrenschmidt
Other archs don't do it, some programs catch signals just fine
and those dumps just clutter the output. Keep the dumps for cases
that aren't supposed to happen such as unknown codes.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
linux-user/
From: Nikunj A Dadhania
Similar to divw, implement branch-less divd.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/translate.c | 48 ++--
1 file changed, 26 insertions(+), 22 deletions(-)
From: Benjamin Herrenschmidt
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 1328 +--
target-ppc/translate/spe-impl.c | 1229
ta
From: Benjamin Herrenschmidt
Instead of relying on NIP having been updated already.
Signed-off-by: Benjamin Herrenschmidt
[dwg: Fold in fix to mark function always_inline]
Signed-off-by: David Gibson
---
target-ppc/fpu_helper.c | 67 +
1 file ch
Add vpermr instruction from ISA 3.0.
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/helper.h |1 +
target-ppc/int_helper.c | 23 +++
target-ppc/translate/vmx-impl.inc.c | 18 ++
target-ppc/translate/vmx-ops.inc.
From: Benjamin Herrenschmidt
We make env->nip almost always point to the faulting instruction,
thus avoiding a mess of "store_current" vs "store_next" in the
exception handling. The syscall exception knows to move the PC by
4 and that's really about it.
This actually fixes a number of cases wher
From: Benjamin Herrenschmidt
Instead, pass GETPC() result to the corresponding helpers. This
requires a bit of fiddling to get the PC (hopefully) right in
the case where we generate a program check, though the hacks there
are temporary, a subsequent patch will clean this all up by always
having t
From: Benjamin Herrenschmidt
They generate exceptions, but they don't update the environment
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/helper.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target
The following vector insert instructions are added from ISA 3.0.
vinsertb - Vector Insert Byte
vinserth - Vector Insert Halfword
vinsertw - Vector Insert Word
vinsertd - Vector Insert Doubleword
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/helper.h |4
ta
From: Benjamin Herrenschmidt
Just generate an alignment interrupt
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
ind
From: Benjamin Herrenschmidt
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 365 +---
target-ppc/translate/dfp-impl.c | 212 +++
target-ppc/trans
Hi!
I am trying DHCP between 2 guests. So I am running first guest with:
-netdev tap,id=TAP0,helper=/home/aik/qemu-bridge-helper \
-device "virtio-net-pci,id=vnet0,mac=C0:41:49:4b:ee:ee,netdev=TAP0"
and second one with:
-netdev tap,id=TAP0,vhost=on,helper=/home/aik/qemu-bridge-helper \
-device
From: Vivek Andrew Sha
Adds Vector Shift Right Variable instruction.
Signed-off-by: Vivek Andrew Sha
[ reverse the order of computation to avoid temporary array ]
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/helper.h
From: Benjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve
the return address when needed. Also remove gen_update_current_nip()
which didn't seem to make much sense to me.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/cpu.
From: Benjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve
the return address when needed
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/timebase_helper.c | 23 +--
target-ppc/translate.c | 12
From: Thomas Huth
The rather random list of check-qtest-xxx entries caused some
confusion in the past, where to use "=" and where to use "+="
(see commits 0ccac16f59462b8e2b9afbc1 and 1f5c1cfbaec0792cd2e5da
for example).
Sorting the check-qtest-xxx entries by architecure instead and
using some em
From: Benjamin Herrenschmidt
Instead of using the same helpers called from translate.c, let's have
a bunch of functions that take the various argument combinations,
especially the retaddr which will be needed in subsequent patches,
and leave the helpers to be just that, helpers for translate.c
W
From: Benjamin Herrenschmidt
We don't implement imprecise FP exceptions and using store_current
which sets SRR1 to the *previous* instruction never makes sense
for these. So let's be truthful and make them precise, which is
allowed by the architecture.
Signed-off-by: Benjamin Herrenschmidt
Sign
From: Sandipan Das
DFP Test Significance Immediate [Quad]
Signed-off-by: Sandipan Das
Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
target-ppc/dfp_helper.c | 35 +++
target-ppc/helper.h | 2 ++
From: Nikunj A Dadhania
Search a byte in the stream of 8bytes provided in the register
Suggested-by: Richard Henderson
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 22 +++
From: Nikunj A Dadhania
Add ISA3.0: Count trailing zeros word instruction.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +
target-ppc/translate.c | 11 +++
3 files cha
From: Sandipan Das
Adds following instructions:
vabsdub: Vector Absolute Difference Unsigned Byte
vabsduh: Vector Absolute Difference Unsigned Halfword
vabsduw: Vector Absolute Difference Unsigned Word
Signed-off-by: Sandipan Das
[ use ISA300 define. Drop etype ]
Signed-off-by: Nikunj A Dadhan
From: Nikunj A Dadhania
ISA 3.0 instruction for adding immediate value shifted with next
instruction address and return the result in the target register.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
target-ppc/translate.c | 26 ++
From: Benjamin Herrenschmidt
We are always generating the "else" case of the condition even when
generating an unconditional branch that will never hit it.
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/translate.c | 14 +++
The following changes since commit e87d397e5ef66276ccc49b829527d605ca07d0ad:
Open 2.8 development tree (2016-09-05 11:38:54 +0100)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.8-20160906
for you to fetch changes up to 2ccbe3e29adb7c016bc5525d38d2a
From: Benjamin Herrenschmidt
We don't use it so let's not generate the updates.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
i
From: Nikunj A Dadhania
maddhd: Multiply-Add High Doubleword
maddhdu: Multiply-Add High Doubleword Unsigned
Above two instruction are dual form and differ by 1 bit
(31st bit)
Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and returns the higher dword
From: Nikunj A Dadhania
Adding following instructions:
moduw: Modulo Unsigned Word
modsw: Modulo Signed Word
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/translate.c | 48
1 file c
From: Nikunj A Dadhania
extswsli : Extend Sign Word & Shift Left Immediate
Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/translate.c | 28
1 file changed, 28 insertions(+)
di
From: Benjamin Herrenschmidt
Some operations aren't allowed in LE mode, use a helper rather than
open coding the exception generation.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
From: Cédric Le Goater
spapr_pci would also be a good candidate but the macro _FDT is
slightly different. It returns and does not exit.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr.c| 11 +--
hw/ppc/spapr_events.c | 11 +--
include/hw/pp
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 12 ++--
hw/ppc/spapr_drc.c | 8
hw/ppc/spapr_iommu.c | 4 ++--
hw/ppc/spapr_rtas.c | 13 +++--
hw/ppc/spapr_vio.c | 3 ++-
include/hw/ppc/fdt.h | 8 +
From: Vivek Andrew Sha
The CR number is provided in the opcode as - BFA (11:13)
Returns:
-1 if bit 0 of CR field is set
1 if bit 1 of CR field is set
0 otherwise.
Signed-off-by: Vivek Andrew Sha
[ reworded commit, used 32bit ops as crf is 32bits ]
Signed-off-by: Nikunj A Dadhania
Revi
From: Benjamin Herrenschmidt
Instead, pass GETPC() result to the corresponding helpers.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/mem_helper.c | 11 ++-
target-ppc/translate.c | 6 --
2 files changed, 6 insertions(+), 11 deletions(-)
diff
From: Sandipan Das
Add ISA3.0 Count trailing zeros double word
Signed-off-by: Sandipan Das
[ added ISA300 flag ]
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +
target-ppc/tra
From: "Aneesh Kumar K.V"
The patch adds CPU PVR definition for POWER9 and enables QEMU to launch
guests/linux-user in TCG mode.
Signed-off-by: Aneesh Kumar K.V
[ Added POWER9 alias, POWER9 SPAPR core and dropped MMU defines ]
Signed-off-by: Nikunj A Dadhania
[dwg: Dropped sPAPR core type again
From: Benjamin Herrenschmidt
Also while at it, group the #include statements in translate.c
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 40 +++---
.../translate/{dfp-impl.c => dfp-impl.inc.c}
From: Benjamin Herrenschmidt
We need to pass it to the raise helper since we don't update it
before the calls.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/mmu-hash64.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tar
From: Nikunj A Dadhania
This flag will be used for POWER9 instructions.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
target-ppc/cpu.h| 5 -
target-ppc/translate_init.c | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff
From: Benjamin Herrenschmidt
The usermode "translate" code generates an error code value that
has the "is_write" bit set, which causes our switch/case to miss
and display "Invalid segfault errno" and a spurrious second state
dump. Fix it.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Dav
From: Greg Kurz
We abort a few lines above if kernel_xics_fd == -1.
This is only code cleanup.
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/intc/xics_kvm.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xi
From: Benjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/mmu_helper.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 737f338..692398c 100644
--- a/target-ppc
From: Benjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve
the return address when needed.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/excp_helper.c | 6 --
target-ppc/translate.c | 8
2 files changed, 4 i
From: Benjamin Herrenschmidt
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 1328 +--
target-ppc/translate/spe-impl.c | 1229
ta
From: Nikunj A Dadhania
ISA 3.0 Compare Ranged Byte instruction useful for
isupper/islower/isaplha kind of operation.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/translate.c | 39 +++
1 file ch
From: Benjamin Herrenschmidt
Use tlb_vaddr_to_host to do a fast path single translate for
the whole cache line. Also make the reservation check match
the entire range.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/mem_helper.c | 46 +-
From: Benjamin Herrenschmidt
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 1068 +--
target-ppc/translate/vmx-impl.c | 829 ++
target-p
From: Benjamin Herrenschmidt
Instead of relying on NIP having been updated already
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/fpu_helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_h
From: Benjamin Herrenschmidt
The current mapping, while correct for the base ports (which is all the
driver uses these days), is wrong for the extended registers.
I suspect the bugs come from incorrect tables in the CHRP IO Ref document,
I have verified the new values here match Apple's MacTech.
From: Thomas Huth
Some of the machines that we have got a firmware image for write
some output to the serial console while booting up. We can use
this output to make sure that the machine is basically working,
so this adds a test that checks the output of these machines
for some well-known "magic
From: Benjamin Herrenschmidt
They generate exceptions, but they don't update the environment
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/helper.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target
From: Benjamin Herrenschmidt
Makes things a bit more manageable
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate.c | 994 +---
target-ppc/translate/vsx-impl.c | 721 +
target-ppc
From: Benjamin Herrenschmidt
We don't need to call a helper for trap always and trap never
which are used by Linux under some circumstances.
Signed-off-by: Benjamin Herrenschmidt
--
v2. Don't generate the helper call when trapping always
Signed-off-by: David Gibson
---
target-ppc/translate.c
From: Swapnil Bokade
Adds following instructions:
vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
vcmpnezw[.]: Vector Compare Not Equal or Zero Word
Signed-off-by: Swapnil Bokade
[ collapse switch case ]
Signed-off-by: Nikunj A Dadhania
From: Laurent Vivier
Since kernel v4.0, linux uses H_CHANGE_LOGICAL_LAN_MAC to change lively
the MAC address of an ibmveth interface.
As QEMU doesn't implement this h_call, we can't change anymore the
MAC address of an spapr-vlan interface.
Signed-off-by: Laurent Vivier
Signed-off-by: David Gi
From: Benjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve
the return address.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/translate/fp-impl.c | 28
target-ppc/translate/vsx-impl.c | 6
From: Thomas Huth
The rather random list of check-qtest-xxx entries caused some
confusion in the past, where to use "=" and where to use "+="
(see commits 0ccac16f59462b8e2b9afbc1 and 1f5c1cfbaec0792cd2e5da
for example).
Sorting the check-qtest-xxx entries by architecure instead and
using some em
From: Cédric Le Goater
The exact same routine will be used in PowerNV.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/Makefile.objs | 2 +-
hw/ppc/fdt.c | 49 +
hw/ppc/spapr.c | 36 +
From: Benjamin Herrenschmidt
Use tlb_vaddr_to_host to do a fast path single translate for
the whole cache line. Also make the reservation check match
the entire range.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/mem_helper.c | 46 +-
From: Benjamin Herrenschmidt
No other change
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/fpu_helper.c | 122
1 file changed, 61 insertions(+), 61 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-p
From: Nikunj A Dadhania
Similar to divw, implement branch-less divd.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-ppc/translate.c | 48 ++--
1 file changed, 26 insertions(+), 22 deletions(-)
From: Benjamin Herrenschmidt
Mostly turn "store" type of helpers into TCG_CALL_NO_WG because
they can take exceptions. Also fixup_thrm doesn't read nor write
the tracked environment.
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target-p
From: Benjamin Herrenschmidt
Other archs don't do it, some programs catch signals just fine
and those dumps just clutter the output. Keep the dumps for cases
that aren't supposed to happen such as unknown codes.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
linux-user/
From: Benjamin Herrenschmidt
Instead, pass GETPC() result to the corresponding helpers.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: David Gibson
---
target-ppc/mem_helper.c | 9 +
target-ppc/translate.c | 4
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a
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