We will rewrite tcp packet secondary received and sent.
When colo guest is a tcp server.
Firstly, client start a tcp handshake. the packet's seq=client_seq,
ack=0,flag=SYN. COLO primary guest get this pkt and mirror(filter-mirror)
to secondary guest, secondary get it use filter-redirector.
Then,pr
We use colo-base.h to track connection and parse packet
Signed-off-by: Zhang Chen
Signed-off-by: Li Zhijian
Signed-off-by: Wen Congyang
---
net/filter-rewriter.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a/net/filter-rewriter.c b/net
Filter-rewriter is a part of COLO project.
It will rewrite some of secondary packet to make
secondary guest's connection established successfully.
usage:
colo secondary:
-object filter-redirector,id=f1,netdev=hn0,queue=tx,indev=red0
-object filter-redirector,id=f2,netdev=hn0,queue=rx,outdev=red1
Filter-rewriter is a part of COLO project.
So this patch set depend on colo-compare.
It will rewrite some of secondary packet to make
secondary guest's connection established successfully.
v2:
- add more comments about packet flows
- add some trace-event
- add seq offset ( = secondary_seq -
This looks like a command line / configuration issue which results in a
name collision as Dave predicted above.
I had to piece this together out of bits of information since documentation is
a bit sparse but the following works. Note the explicit ID and LUN values on
the -device declarations:
s
Signed-off-by: Alistair Francis
---
V8:
- Improve documentation
V6:
- Fixup documentation
V4:
- Re-write to be more comprehensive
docs/generic-loader.txt | 60 +
1 file changed, 60 insertions(+)
create mode 100644 docs/generic-loader.txt
diff
Add a new function load_elf_as() that allows the caller to specify an
AddressSpace to use when loading the ELF. The original load_elf()
function doesn't have any change in functionality.
Signed-off-by: Alistair Francis
---
V8:
- Introduce an RFC version of AddressSpace support
hw/core/loader.c
Add a generic loader to QEMU which can be used to load images or set
memory values.
Signed-off-by: Alistair Francis
---
V8:
- Code corrections
- Rebase
V7:
- Rebase
V6:
- Add error checking
V5:
- Rebase
V4:
- Allow the loader to work with every architecture
- Move the file to hw/core
- In
When loading ROMs allow the caller to specify an AddressSpace to use for
the load.
Signed-off-by: Alistair Francis
---
V8:
- Introduce an RFC version of AddressSpace loading support
hw/core/loader.c | 18 --
include/hw/elf_ops.h | 2 +-
include/hw/loader.h | 10 ++
This work is based on the original work by Li Guang with extra
features added by Peter C and myself.
The idea of this loader is to allow the user to load multiple images
or values into QEMU at startup.
Memory values can be loaded like this: -device
loader,addr=0xfd1a0104,data=0x800e,data-len
If the caller didn't specify an architecture for the ELF machine
the load_elf() function will auto detect it based on the ELF file.
Signed-off-by: Alistair Francis
---
V8:
- Move into load_elf64/load_elf32
V7:
- Fix typo
include/hw/elf_ops.h | 5 +
1 file changed, 5 insertions(+)
diff --
Hey Guys,
We just tested the patch on QEMU 2.6.0 and confirmed that both 2.6.0 ->
2.6.0 and 2.4.0 -> 2.6.0 migrations work properly.
We will be leaving a migration loop running over the weekend to verify
that everything works as expected, but I don't expect any surprises from
that. Thanks fo
On Fri, Jul 01, 2016 at 17:16:08 +0100, Alex Bennée wrote:
(snip)
> run 1: ret=0 (PASS), time=4.755824 (1/1)
> run 2: ret=0 (PASS), time=4.756076 (2/2)
> run 3: ret=0 (PASS), time=4.755916 (3/3)
> run 4: ret=0 (PASS), time=4.755853 (4/4)
> run 5: ret=0 (PASS), time=4.755929 (5/5)
> Results summary:
I got a bug report yesterday that seems to be related to how CPUs
are ordered 'lscpu' and /proc/cpuinfo:
https://bugzilla.redhat.com/show_bug.cgi?id=1351160
It's not an actual bug, but it's not the first time I see people
confused by CPU numbers not following socket/core/thread IDs in
lscpu and /p
On Fri, Jul 01, 2016 at 17:16:10 +0100, Alex Bennée wrote:
> Lock contention in the hot path of moving between existing patched
> TranslationBlocks is the main drag in multithreaded performance. This
> patch pushes the tb_lock() usage down to the two places that really need
> it:
>
> - code gene
On 07/01/2016 05:17 PM, Emilio G. Cota wrote:
On Fri, Jul 01, 2016 at 17:16:09 +0100, Alex Bennée wrote:
From: Sergey Fedorov
(snip)
@@ -333,7 +338,7 @@ static inline TranslationBlock *tb_find_fast(CPUState *cpu,
is executed. */
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
On Fri, Jul 01, 2016 at 17:16:09 +0100, Alex Bennée wrote:
> From: Sergey Fedorov
(snip)
> @@ -333,7 +338,7 @@ static inline TranslationBlock *tb_find_fast(CPUState
> *cpu,
> is executed. */
> cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
> tb_lock();
> -tb = cpu->tb_jmp
On 06/27/2016 02:20 PM, Sergey Fedorov wrote:
On 03/06/16 23:40, Alex Bennée wrote:
diff --git a/cpus.c b/cpus.c
index 1694ce9..12e04c9 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1208,9 +1208,29 @@ static int tcg_cpu_exec(CPUState *cpu)
return ret;
}
+/* Single-threaded TCG
+ *
+ * In the singl
On 06/03/2016 01:40 PM, Alex Bennée wrote:
+bool qemu_tcg_mttcg_enabled(void)
+{
+return mttcg_enabled;
+}
Is there a good reason to expose this via function call, rather than just test
the variable?
r~
On 06/03/2016 01:40 PM, Alex Bennée wrote:
In preparation for multi-threaded TCG we remove tcg_exec_all and move
all the CPU cycling into the main thread function. When MTTCG is enabled
we shall use a separate thread function which only handles one vCPU.
Signed-off-by: Alex Bennée
Reviewed-by
On 06/03/2016 01:40 PM, Alex Bennée wrote:
From: KONRAD Frederic
This protects TBContext with tb_lock to make tb_* thread safe.
We can still have issue with tb_flush in case of multithread TCG:
another CPU can be executing code during a flush.
This can be fixed later by making all other TCG t
On Mon, Jun 13, 2016 at 9:27 AM, wrote:
> From: KONRAD Frederic
>
> This adds the pll to the zynqmp_crf and the dp_video clock output.
>
> Signed-off-by: KONRAD Frederic
> ---
> hw/misc/xilinx_zynqmp_crf.c | 440
>
> 1 file changed, 440 insertions(
On 06/03/2016 01:40 PM, Alex Bennée wrote:
This adds asserts to check the locking on the various translation
engines structures. There are two sets of structures that are protected
by locks.
The first the l1map and PageDesc structures used to track which
translation blocks are associated with wh
On 07/01/2016 09:16 AM, Alex Bennée wrote:
Lock contention in the hot path of moving between existing patched
TranslationBlocks is the main drag in multithreaded performance. This
patch pushes the tb_lock() usage down to the two places that really need
it:
- code generation (tb_gen_code)
- j
On 07/01/2016 09:16 AM, Alex Bennée wrote:
From: Sergey Fedorov
First, ensure atomicity of CPU's 'tb_jmp_cache' access by:
* using atomic_read() to look up a TB when not holding 'tb_lock';
* using atomic_write() to remove a TB from each CPU's local cache on
TB invalidation.
Second, add so
On Mon, Jun 13, 2016 at 9:27 AM, wrote:
> From: KONRAD Frederic
>
> This adds the zynqmp_crf to the zynqmp platform.
>
> Signed-off-by: KONRAD Frederic
> ---
> hw/arm/xlnx-zynqmp.c | 7 +++
> include/hw/arm/xlnx-zynqmp.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/hw
On Mon, Jun 13, 2016 at 9:27 AM, wrote:
> From: KONRAD Frederic
>
> This is a fixed clock device.
> It justs behave as an empty device with a parametrable output rate.
>
> Signed-off-by: KONRAD Frederic
> ---
> hw/misc/Makefile.objs | 2 +
> hw/misc/fixed-clock.c | 87
> +
On 06/16/2016 08:33 AM, Markus Armbruster wrote:
> Eric Blake writes:
>
>> Recent commits added support for an anonymous type as the base
>> of a flat union; with a bit more work, we can also allow an
>> anonymous struct as a branch of a flat union. This probably
>> most useful when a branch add
This patch introduces the ppc_set_vcpu_dt_id() function. It is
currently empty but it will be used to generate cpu_dt_id out of
a cpu_index provided by the machine.
It also changes the machine types to provide cpu_index. Since all
of them keep the cpus in an array, cpu_index is simply the index
in
If we want to generate cpu_dt_id in the machine code, this must occur
before the cpu gets realized. We must open code the cpu creation to be
able to do this.
This patch just does that. It borrows some lines from previous work
from Bharata to handle the feature parsing.
Signed-off-by: Greg Kurz
-
Now that every supported machine type is able to provide a cpu_index, we
can safely move all the cpu_dt_id bits to the machine code.
TODO: the cpu_dt_id logic remains the same wannabe generic one as before
because of its target code background: machine types should provide their
own cpu_dt_id logi
The machine code currently uses the same cpu_ppc_init() function to
create cpus as the user mode. This function also triggers the cpu
realization.
It is okay for user mode but with system mode we may want to do other
things between initialization and realization, like generating cpu
ids for the DT
From: Bharata B Rao
During CPU core realization, we create all the thread objects and parent
them to the core object in a loop. However, the realization of thread
objects is done separately by walking the threads of a core using
object_child_foreach(). With this, there is no guarantee on the orde
Starting with version 2.7, pseries machine now support hotplug of
cpu cores. The implementation requires to open code cpu creation
and thus does not call ppc_cpu_init().
This patch does all the plumbing to allow pseries machine types
with version >= 2.7 to generate cpu DT ids out of the indexes
of
kvmppc_smt_threads() returns 1 if KVM is not enabled.
Signed-off-by: Greg Kurz
---
target-ppc/translate_init.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 843f19b748fb..a06bf50b65d4 100644
--- a/target-ppc
This series is a sequel to the discussion on a patch from Ben's powernv
patchset:
http://patchwork.ozlabs.org/patch/597153/
Indeed, since the DT is a machine abstraction, it should definitely sit
under hw/ppc and not in the target code:
- all machine types are forced to share the same num
We may be saying the same thing, but I'd word it differently. If a
"device" has a "path" then it gets a se->compat (compatibility?) record.
- Within that record each device gets an instance_id value based on its
name. Multiple IDs for the same name are allowed.
- At the "se" level each d
On 06/30/2016 11:13 AM, Shuang Zhai wrote:
We wonder if there exists any optimization, e.g., directly mapping the
frontend flags to that of the backend? Any suggestions are appreciated.
Directly mapping frontend to backend flags is a non-starter, since not all
backends have those flags.
Ther
On 06/30/2016 06:45 AM, Peter Maydell wrote:
On 29 June 2016 at 09:47, wrote:
From: Vijay
Use Neon instructions to perform zero checking of
buffer. This is helps in reducing total migration time.
diff --git a/util/cutils.c b/util/cutils.c
index 5830a68..4779403 100644
--- a/util/cutils.c
On Fri, 1 Jul 2016 19:30:30 +0200
Cédric Le Goater wrote:
> On 07/01/2016 07:18 PM, Peter Maydell wrote:
> > On 28 June 2016 at 19:24, Cédric Le Goater wrote:
> >> This test uses the palmetto platform and the AST2400 SPI controller to
> >> test the m25p80 flash module device model. The flash m
On 06/29/2016 09:55 AM, Markus Armbruster wrote:
> Tracked down with an ugly, brittle and probably buggy Perl script.
>
> Also move includes converted to <...> up so they get included before
> ours where that's obviously okay.
>
> Signed-off-by: Markus Armbruster
> ---
> +++ b/qga/vss-win32/pro
On 06/30/2016 12:37 AM, Peter Lieven wrote:
evaluation with the recently introduced maximum stack usage monitoring revealed
that the actual used stack size was never above 4kB so allocating 1MB stack
for each coroutine is a lot of wasted memory. So reduce the stack size to
64kB which should still
On 06/30/2016 12:37 AM, Peter Lieven wrote:
Signed-off-by: Peter Lieven
---
util/coroutine-sigaltstack.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 06/30/2016 12:37 AM, Peter Lieven wrote:
+for (ptr2 = ptr; ptr2 < ptr + sz; ptr2 += sizeof(u_int32_t)) {
+*(u_int32_t *)ptr2 = 0xdeadbeaf;
+}
s/u_int32_t/uint32_t/g
r~
On 06/30/2016 12:37 AM, Peter Lieven wrote:
Signed-off-by: Peter Lieven
---
util/coroutine-ucontext.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On 06/30/2016 12:37 AM, Peter Lieven wrote:
Signed-off-by: Peter Lieven
---
include/qemu/coroutine_int.h | 2 ++
util/coroutine-sigaltstack.c | 2 +-
util/coroutine-ucontext.c| 2 +-
util/coroutine-win32.c | 2 +-
4 files changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Richard
On 07/01/2016 01:12 PM, Richard Henderson wrote:
On 06/30/2016 12:37 AM, Peter Lieven wrote:
+void *qemu_alloc_stack(size_t sz)
+{
+/* allocate sz bytes plus one extra page for a guard
+ * page at the bottom of the stack */
+void *ptr = mmap(NULL, sz + getpagesize(), PROT_NONE,
+
On 06/30/2016 12:37 AM, Peter Lieven wrote:
+void *qemu_alloc_stack(size_t sz)
+{
+/* allocate sz bytes plus one extra page for a guard
+ * page at the bottom of the stack */
+void *ptr = mmap(NULL, sz + getpagesize(), PROT_NONE,
+ MAP_PRIVATE | MAP_ANONYMOUS, -1,
On 06/29/2016 08:55 AM, Markus Armbruster wrote:
This series takes a good swing at two annoyances:
* We sometimes use #include "..." even for system headers, and <...>
for our own headers. Makes spotting the system headers harder, and
can be confusing. PATCH 01 cleans this up. You've seen
Conflicting experimental packages in that ppa, trying ubuntu-virt/ppa
instead.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1297218
Title:
guest hangs after live migration due to tsc jump
Status
Thank you. I'm doing a test build in ppa:serge-hallyn/virt, and will
run a full regression test from there. I'll push for SRU if that
passes.
Would you mind putting in the bug Description (at top) a concise summary
of the test case, for the SRU process?
--
You received this bug notification be
On 07/01/2016 07:47 AM, Michael Rolnik wrote:
5. translation bug fixes for ADIW, SBIW, XOR instructions
6. propper handling of cpu register writes though memory
I don't see these changes in the patch set.
r~
* Gerd Hoffmann (kra...@redhat.com) wrote:
> > So that's mapped at an address beyond host phys-bits.
> > And it hasn't failed/crashed etc - but I guess maybe nothing is using that
> > 2G space?
>
> root@fedora ~# dmesg | grep Surface
> [4.830095] [drm] qxl: 2048M of Surface memory size
>
> q
On 06/30/2016 09:03 AM, Alberto Garcia wrote:
> On Wed 29 Jun 2016 07:20:55 PM CEST, Max Reitz wrote:
> I thought adding a new 'ID' field was simpler. The device name is
> still a device name (where it makes sense). The default ID is
> guaranteed to be valid and guaranteed not to clas
Add some new blk ioctls (these are 0x12,119 through
to 0x12,127). Several of these are used by mke2fs; this silences
the warnings:
mke2fs 1.42.12 (29-Aug-2014)
Unsupported ioctl: cmd=0x127b
Unsupported ioctl: cmd=0x127a
warning: Unable to get device geometry for /dev/loop5
Unsupported ioctl: cmd=0
On Fri, Jul 01, 2016 at 01:07:39PM -0400, Kevin O'Connor wrote:
> If I understand correctly, most keys are sent on the serial port as
> single bytes, but there are a few keys that are sent as multi-byte
> sequences. There's a lot of complexity to implement buffering for
> that unusual case. I won
From: Sergey Sorokin
Some architectures (e.g. ARMv8) need the address which is aligned
to a size more than the size of the memory access.
To support such check it's enough the current costless alignment
check implementation in QEMU, but we need to support
an alignment size specifying.
Signed-off
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 254427b..154ffe8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -557,7 +557,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_
While we can store constants via constrants on INDEX_op_st_i32 et al,
we weren't able to spill constants to backing store.
Add a new backend interface, tcg_out_sti, which may store the constant
(and is allowed to fail). Rearrange the temp_* helpers so that we only
attempt to directly store a cons
available in the git repository at:
git://github.com/rth7680/qemu.git tags/pull-tcg-20160701
for you to fetch changes up to 15dab9abdedb1657ace1b3169617852299b5063f:
tcg: Improve the alignment check infrastructure (2016-07-01 10:13:22 -0700
On 01.07.2016 19:36, Peter Maydell wrote:
> On 30 June 2016 at 20:01, Dmitry Osipenko wrote:
>> On 30.06.2016 18:02, Peter Maydell wrote:
>>> What I meant was: ptimer_get_count() is typically called to generate
>>> a value to return from a register. That's a separate thing, conceptually,
>>> from
We fail to pass to $(AS) all of the different flags that may be required
for a given set of CFLAGS. Rather than figuring out the host-specific
mapping, it's better to allow the compiler driver to do that.
However, simply using $(CC) runs afoul of clang trying to build the
option roms. C.f. 3dd46
On 06/30/2016 06:53 AM, Markus Armbruster wrote:
> Got lost in commit b93b63f.
>
> Signed-off-by: Markus Armbruster
> ---
> tests/Makefile.include | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Eric Blake
>
> diff --git a/tests/Makefile.include b/tests/Makefile.include
On 28 June 2016 at 19:24, Cédric Le Goater wrote:
> This test uses the palmetto platform and the AST2400 SPI controller to
> test the m25p80 flash module device model. The flash model is defined
> by the platform (n25q256a) and it would be nice to find way to control
> it, using a property probabl
From: "Emilio G. Cota"
Emulating LL/SC with cmpxchg is not correct, since it can
suffer from the ABA problem. Portable parallel code, however,
is written assuming only cmpxchg--and not LL/SC--is available.
This means that in practice emulating LL/SC with cmpxchg is
a viable alternative.
The appe
From: "Emilio G. Cota"
Emulating LL/SC with cmpxchg is not correct, since it can
suffer from the ABA problem. Portable parallel code, however,
is written assuming only cmpxchg--and not LL/SC--is available.
This means that in practice emulating LL/SC with cmpxchg is
a viable alternative.
The appe
On Fri, Jul 01, 2016 at 12:54:31PM +0200, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> ---
> src/clock.c | 1 +
> src/serial.c | 255
> +++
> src/util.h | 1 +
> 3 files changed, 257 insertions(+)
>
> diff --git a/src/clock
On 07/01/2016 10:04 AM, Richard Henderson wrote:
> I spent a couple evenings this week tweaking Emilio's patch set.
>
> The first major change is to "qemu/int128.h", so that we can use
> that type in the context of a 16-byte cmpxchg. I have yet to teach
> TCG code generation about this type, so i
From: "Emilio G. Cota"
The exception is not emitted anymore.
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-29-git-send-email-c...@braap.org>
---
linux-user/main.c | 93 ---
1 file changed, 93 deletions(-)
diff --git a/linux-use
From: "Emilio G. Cota"
The exception is not emitted anymore; remove it and the associated
TCG variables.
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-31-git-send-email-c...@braap.org>
---
target-arm/cpu.h | 17 ++---
target-arm/internals.h | 4 +---
target-arm
Add all of cmpxchg, op_fetch, fetch_op, and xchg.
Handle both endian-ness, and sizes up to 8.
Handle expanding non-atomically, when emulating in serial.
Signed-off-by: Richard Henderson
---
Makefile.objs | 1 -
Makefile.target| 1 +
atomic_template.h | 220 +
From: "Emilio G. Cota"
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-25-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-arm/translate.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/target-arm/translate.
On 07/01/2016 07:18 PM, Peter Maydell wrote:
> On 28 June 2016 at 19:24, Cédric Le Goater wrote:
>> This test uses the palmetto platform and the AST2400 SPI controller to
>> test the m25p80 flash module device model. The flash model is defined
>> by the platform (n25q256a) and it would be nice to
From: "Emilio G. Cota"
With this microbenchmark we can measure the overhead of emulating atomic
instructions with a configurable degree of contention.
The benchmark spawns $n threads, each performing $o atomic ops (additions)
in a loop. Each atomic operation is performed on a different cache lin
From: "Emilio G. Cota"
[rth: Eliminate some unnecessary temporaries.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-13-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 76 +
1 file chang
From: "Emilio G. Cota"
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-19-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/tr
On 1 July 2016 at 18:18, Peter Maydell wrote:
> On 28 June 2016 at 19:24, Cédric Le Goater wrote:
>> This test uses the palmetto platform and the AST2400 SPI controller to
>> test the m25p80 flash module device model. The flash model is defined
>> by the platform (n25q256a) and it would be nice t
From: "Emilio G. Cota"
The exception is not emitted anymore.
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-30-git-send-email-c...@braap.org>
---
linux-user/main.c | 125 --
1 file changed, 125 deletions(-)
diff --git a/linux-us
Force the use of cmpxchg16b on x86_64.
Wikipedia suggests that only very old AMD64 (circa 2004) did not have
this instruction. Further, it's required by Windows 8 so no new cpus
will ever omit it.
If we truely care about these, then we could check this at startup time
and then avoid executing pa
From: "Emilio G. Cota"
[rth: Avoid qemu_load that's redundant with the atomic op.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-15-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 26 --
1 file changed, 20 ins
From: "Emilio G. Cota"
[rth: Merge gen_inc_locked back into gen_inc to share cc update.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-14-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 24 +---
1 file changed, 13
Stop specializing on TARGET_LONG_BITS == 32; unconditionally allocate
a temp and expand with tcg_gen_extu_i32_tl. Split out gen_aa32_addr,
gen_aa32_frob64, gen_aa32_ld_i32 and gen_aa32_st_i32 as separate interfaces.
Signed-off-by: Richard Henderson
---
target-arm/translate.c | 171 +
When we cannot emulate an atomic operation within a parallel
context, this exception allows us to stop the world and try
again in a serial context.
Signed-off-by: Richard Henderson
---
cpu-exec-common.c | 6 +
cpu-exec.c | 23 +++
cpus.c |
From: "Emilio G. Cota"
It's been superseded by the atomic helpers.
The use of the atomic helpers provides a significant performance and scalability
improvement. Below is the result of running the atomic_add-test microbenchmark
with:
$ x86_64-linux-user/qemu-x86_64 tests/atomic_add-bench -o 500
I spent a couple evenings this week tweaking Emilio's patch set.
The first major change is to "qemu/int128.h", so that we can use
that type in the context of a 16-byte cmpxchg. I have yet to teach
TCG code generation about this type, so it's really only usable
from other helper functions. But th
From: "Emilio G. Cota"
[rth: Move redundant qemu_load out of cmpxchg loop.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-16-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 38 ++
1 file changed, 3
From: "Emilio G. Cota"
[rth: Avoid redundant qemu_ld in locked case. Fix previously unnoticed
incorrect zero-extension of address in register-offset case.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-18-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
targe
From: "Emilio G. Cota"
[rth: Move load of reg value to common location.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-17-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletio
If __int128 is not supported, prefer a base type that is
returned in registers rather than memory.
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 110 +++---
1 file changed, 69 insertions(+), 41 deletions(-)
diff --git a/include/qemu/int
From: "Emilio G. Cota"
The diff here is uglier than necessary. All this does is to turn
FOO
into:
if (s->prefix & PREFIX_LOCK) {
BAR
} else {
FOO
}
where FOO is the original implementation of an unlocked cmpxchg.
[rth: Adjust unlocked cmpxchg to use movcond instead of branches.
Adjust he
From: "Emilio G. Cota"
This paves the way for upcoming work.
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-8-git-send-email-c...@braap.org>
---
include/qemu/atomic.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
index 7a5909
From: "Emilio G. Cota"
This paves the way for upcoming work.
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-9-git-send-email-c...@braap.org>
---
include/qemu/atomic.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/qemu/atomic.h b/include/qemu/atomic
Signed-off-by: Richard Henderson
---
exec.c| 4 ++--
include/qemu/int128.h | 10 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index 0122ef7..806e2fe 100644
--- a/exec.c
+++ b/exec.c
@@ -318,9 +318,9 @@ static inline bool section_cover
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 135 +-
1 file changed, 134 insertions(+), 1 deletion(-)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 52aaf99..08f1db1 100644
--- a/include/qemu/int128.h
+++ b/include
This is really just a placeholder for an actual
command-line switch for mttcg.
---
translate-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/translate-all.c b/translate-all.c
index 99ae7f9..a10fa06 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -119,7 +119,7 @@ sta
On 1 July 2016 at 17:44, Cédric Le Goater wrote:
> I have some extra patches to use a rom device and boot from flash0.
> That is for next week.
We're in softfreeze now, so really I should stop
taking non-bugfix patches, though for a new board
with missing stuff that prevents boot there's a little
To have shorter lines and be consistent with other fs devices.
Acked-by: Cédric Le Goater
Signed-off-by: Greg Kurz
---
hw/9pfs/9p-synth.c | 200 ++---
1 file changed, 100 insertions(+), 100 deletions(-)
diff --git a/hw/9pfs/9p-synth.c b/hw/9pfs/9
From: Greg Kurz
The system header doesn't exist on all host platforms. Code
should include "qemu/osdep.h" instead to avoid build breaks on plafforms
that don't define CONFIG_IOVEC (like win32, if it is to support 9p one day).
Acked-by: Cédric Le Goater
Acked-by: Michael Fritscher
Signed-off-b
The following changes since commit 94e31093ff34ead50dc3970699a4e36582fb3f17:
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20160630.0'
into staging (2016-07-01 11:52:14 +0100)
are available in the git repository at:
https://github.com/gkurz/qemu.git tags/for-upstream
for
On 01/07/16 19:29, Alvise Rigo wrote:
> Hi Sergey,
>
> On Mon, Jun 20, 2016 at 12:28 AM, Sergey Fedorov
> wrote:
>> diff --git a/cpu-exec-common.c b/cpu-exec-common.c
>> index 8184e0662cbd..3056324738f8 100644
>> --- a/cpu-exec-common.c
>> +++ b/cpu-exec-common.c
>> @@ -25,6 +25,7 @@
>>
>> bool e
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