This change was made by a bot.
** Changed in: linux (Ubuntu)
Status: New => Confirmed
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https://bugs.launchpad.net/bugs/1563887
Title:
qemu-system-ppc64 freezes on starting imag
Hm - I can boot a wily cloud image, just not a xenial one.
** Also affects: linux (Ubuntu)
Importance: Undecided
Status: New
** Changed in: qemu (Ubuntu)
Status: Incomplete => Confirmed
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You received this bug notification because you are a member of qemu-
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** Changed in: qemu (Ubuntu)
Status: New => Incomplete
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1563887
Title:
qemu-system-ppc64 freezes on starting image on ppc64le
Status in QEMU:
Public bug reported:
If I compile qemu-2.4.1 like this:
CC="gcc -mtune=generic -Os -pipe" CXX="g++ -mtune=generic -Os -pipe
-fno-exceptions -fno-rtti" ./configure --prefix=/usr/local
--localstatedir=/var --libexecdir=/usr/local/lib/qemu
--interp-prefix=/usr/local/share/qemu --disable-smartcard-ns
I just updated GNU ARM Eclipse QEMU to 2.5.1 and initially I had some problems,
main() failed quite early, in the first call to `find_default_machine()`.
After several debug sessions, I identified the problem to be a null pointer
when a referred interface is not defined. In my Cortex-M specific
On Apr 1, 2016 14:38, Aurelien Jarno wrote:
> Richard, do you have a pending TCG pull request in which you can include
> this one?
Nothing pending at the moment, no. I was going to do one special for this, but it looks as if I won't get to it before Sunday at minimum. If you'd like to include
On Fri, 1 Apr 2016 14:50:43 -0400
Stefan Berger wrote:
> On 03/31/2016 10:07 AM, Igor Mammedov wrote:
> > On Thu, 31 Mar 2016 00:03:57 -0400
> > Stefan Berger wrote:
> >
> >> On 03/30/2016 09:33 AM, Igor Mammedov wrote:
> >>> On Mon, 21 Mar 2016 10:21:11 -0400
> >>> Stefan Berger wrote:
> >>>
>
On Apr 2, 2016, at 1:35 PM, Peter Maydell wrote:
> On 2 April 2016 at 18:25, Programmingkid wrote:
>>
>> On Apr 2, 2016, at 1:07 PM, Peter Maydell wrote:
>>
>>> On 2 April 2016 at 17:56, Programmingkid wrote:
The mouse down event should not be sent to the guest if the mouse down
ev
On 2 April 2016 at 18:25, Programmingkid wrote:
>
> On Apr 2, 2016, at 1:07 PM, Peter Maydell wrote:
>
>> On 2 April 2016 at 17:56, Programmingkid wrote:
>>> The mouse down event should not be sent to the guest if the mouse down event
>>> causes an activation of QEMU. This patch prevents activati
On Apr 2, 2016, at 1:07 PM, Peter Maydell wrote:
> On 2 April 2016 at 17:56, Programmingkid wrote:
>> The mouse down event should not be sent to the guest if the mouse down event
>> causes an activation of QEMU. This patch prevents activation clicks from
>> going
>> to the guest.
>>
>> Signed-
On 2 April 2016 at 17:56, Programmingkid wrote:
> The mouse down event should not be sent to the guest if the mouse down event
> causes an activation of QEMU. This patch prevents activation clicks from going
> to the guest.
>
> Signed-off-by: John Arbuckle
> ---
> ui/cocoa.m | 2 +-
> 1 file cha
The mouse down event should not be sent to the guest if the mouse down event
causes an activation of QEMU. This patch prevents activation clicks from going
to the guest.
Signed-off-by: John Arbuckle
---
ui/cocoa.m | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ui/cocoa.m b/u
For now we only support the following devices:
* up to 4 Cortex A9 cores
* A9 MPCORE (SCU, GIC, TWD)
* 5 i.MX UARTs
* 2 EPIT timers
* 1 GPT timer
* 3 I2C controllers
* 7 GPIO controllers
* 6 SDHC controllers
* 5 SPI controllers
* 1 CCM device
* 1 SRC device
* various ROM/RAM areas.
Reviewed-by: Pe
Quoting Serge Hallyn (2016-04-01 11:56:29)
> Hi,
>
> I've redeployed my test box with 14.04 with kilo-staging archive, but i
> get a core dump when i try to run kvm the same way you did.
What does `ppc64_cpu --info` report? The original bug had some output
that suggested SMT was enabled:
> cpu
The sabrelite supports one SPI FLASH memory on SPI1
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* Output a message and exit if RAM size is unsupported.
Changes since V2:
* Added include "qemu/osdep.h"
* Added access to controllers through properties.
Changes since V3:
* No
This one is build on top of the existing FIFO8
Reviewed-by: Peter Maydell
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* None
Changes since V2:
* Added copyright
* define Fifo32 as a struct containing Fifo8
* remove fifo32_pop_buf()
Changes since V3:
* Added comment on
Split ARM on/off function from PSCI support code.
This will allow to reuse these functions in other code.
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* Not present on V1
Changes since V2:
* Not present on V2
Changes since V3:
* Move to a more generic/usefull API
* Manage C
This controller is also present in i.MX5X devices but they are not
yet emulated by QEMU.
Reviewed-by: Peter Maydell
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* Change "reset" sematic to mean full power cyvle.
Changes since V2:
* use arm-powerctl API
* Added #include "qemu/
This patch series adds support for the Freescale i.MX6 processor.
For now we only support the following devices:
* up to 4 Cortex A9 cores
* A9 MPCORE (SCU, GIC, TWD)
* 5 i.MX UARTs
* 2 EPIT timers
* 1 GPT timer
* 7 GPIO controllers
* 6 SDHC controllers
* 5 SPI controllers
* 1 CCM device
* 1 SRC d
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* Access SPI slave only at a byte level.
* rework the CS activation to avoid to reset access to SPI slaves.
Changes since V2:
* Added #include "qemu/osdep.h"
* remove previous_level from state struct
* save burst_length in VMSTATE
This will not compile on "target-arm.next" as I need to rework a bit the
header file included.
I am fixing it and will send a v7.
Sorry for the noise.
JC
Le 02/04/2016 14:46, Jean-Christophe Dubois a écrit :
This patch series adds support for the Freescale i.MX6 processor.
For now we only s
Wouter,
On 2 Apr 2016, at 13:57, Wouter Verhelst wrote:
> On Fri, Apr 01, 2016 at 10:54:42AM +0100, Alex Bligh wrote:
>> Improve the documentation of NBD_CMD_FLUSH and NBD_CMD_FLAG_FUA. Specifically
>> the latter may be set on any command, and its semantics on commands other
>> than NBD_CMD_WRIT
The sabrelite supports one SPI FLASH memory on SPI1
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* Output a message and exit if RAM size is unsupported.
Changes since V2:
* Added include "qemu/osdep.h"
* Added access to controllers through properties.
Changes since V3:
* N
On Fri, Apr 01, 2016 at 10:54:42AM +0100, Alex Bligh wrote:
> Improve the documentation of NBD_CMD_FLUSH and NBD_CMD_FLAG_FUA. Specifically
> the latter may be set on any command, and its semantics on commands other
> than NBD_CMD_WRITE need explaining. Further, explain how these relate to
> reorde
For now we only support the following devices:
* up to 4 Cortex A9 cores
* A9 MPCORE (SCU, GIC, TWD)
* 5 i.MX UARTs
* 2 EPIT timers
* 1 GPT timer
* 3 I2C controllers
* 7 GPIO controllers
* 6 SDHC controllers
* 5 SPI controllers
* 1 CCM device
* 1 SRC device
* various ROM/RAM areas.
Reviewed-by: Pe
This controller is also present in i.MX5X devices but they are not
yet emulated by QEMU.
Reviewed-by: Peter Maydell
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* Change "reset" sematic to mean full power cyvle.
Changes since V2:
* use arm-powerctl API
* Added #include "qemu/
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* Access SPI slave only at a byte level.
* rework the CS activation to avoid to reset access to SPI slaves.
Changes since V2:
* Added #include "qemu/osdep.h"
* remove previous_level from state struct
* save burst_length in VMSTATE
This one is build on top of the existing FIFO8
Reviewed-by: Peter Maydell
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* None
Changes since V2:
* Added copyright
* define Fifo32 as a struct containing Fifo8
* remove fifo32_pop_buf()
Changes since V3:
* Added comment on
Split ARM on/off function from PSCI support code.
This will allow to reuse these functions in other code.
Signed-off-by: Jean-Christophe Dubois
---
Changes since V1:
* Not present on V1
Changes since V2:
* Not present on V2
Changes since V3:
* Move to a more generic/usefull API
* Manage C
This patch series adds support for the Freescale i.MX6 processor.
For now we only support the following devices:
* up to 4 Cortex A9 cores
* A9 MPCORE (SCU, GIC, TWD)
* 5 i.MX UARTs
* 2 EPIT timers
* 1 GPT timer
* 7 GPIO controllers
* 6 SDHC controllers
* 5 SPI controllers
* 1 CCM device
* 1 SRC d
On Fri, Apr 01, 2016 at 06:25:24PM -0400, Kevin O'Connor wrote:
> I'm getting different results. When you have time we should probably
> track down the discrepancy. Some of the difference is likely due to
> different hardware (I'm using kvm on an old AMD machine) and some is
> likely due to diffe
On 04/02/2016 12:29 AM, Eric Blake wrote:
Rather than requiring allocation by default and allowing trims
only on request during WRITE_ZEROES, it seems like a better
default is to allow server optimizations by default and require
full allocation by specific request. Since WRITE_ZEROES is
experime
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