On 2016/2/27 0:36, Dr. David Alan Gilbert wrote:
* Dr. David Alan Gilbert (dgilb...@redhat.com) wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
From: root
This is the 15th version of COLO (Still only support periodic checkpoint).
Here is only COLO frame part, you can get the w
Hello, I am hoping someone here can help me. I am implementing QCow2 support
for a PC emulator project and have a couple questions regarding compression I
haven't been able to figure out on my own.
First some background:
I am using the information I found at
https://people.gnome.org/~markmc/qco
On Fri, 02/26 23:40, Denis V. Lunev wrote:
> On 02/26/2016 10:55 PM, Paolo Bonzini wrote:
> >
> >On 19/02/2016 09:51, Markus Armbruster wrote:
> >>>Is it an abuse to "Get LBA Status" to return dirty information? Because in
> >>>SCSI
> >>>the command reports "mapped", "allocated" and "anchored" sta
On 2016/2/26 23:42, Peter Maydell wrote:
> On 26 February 2016 at 15:28, Wei Huang wrote:
>>
>>
>> On 02/26/2016 09:06 AM, Peter Maydell wrote:
>>> On 26 February 2016 at 14:54, Shannon Zhao wrote:
On 2016/2/26 20:53, Peter Maydell wrote:
> I don't understand why a 500ms pulse is bette
Signed-off-by: Andrew Baumann
---
hw/arm/bcm2835_peripherals.c | 18 +++
hw/char/Makefile.objs| 1 +
hw/char/bcm2835_aux.c| 241 +++
include/hw/arm/bcm2835_peripherals.h | 2 +
include/hw/char/bcm2835_aux.h| 31
Signed-off-by: Andrew Baumann
---
hw/arm/bcm2835_peripherals.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 6d66fa0..6ce9cd1 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -171,6 +171,
The property channel driver now interfaces with the framebuffer device
to query and set framebuffer parameters. As a result of this, the "get
ARM RAM size" query now correctly returns the video RAM base address
(not total RAM size), and the ram-size property is no longer relevant
here.
Signed-off-
This patch series adds support for the AUX (second UART) and
framebuffer devices on Raspberry Pi 2, and enables booting Windows on
this device. As with the previous series, it is heavily based on the
original (out of tree) work of Gregory Estrade, Stefan Weil and others
to support Raspberry Pi 1.
The framebuffer occupies the upper portion of memory (64MiB by
default), but it can only be controlled/configured via a system
mailbox or property channel (to be added by a subsequent patch).
Signed-off-by: Andrew Baumann
---
hw/arm/bcm2835_peripherals.c | 38 +++-
hw/arm/bcm2836.c
On 02/25/2016 07:45 AM, Hervé Poussineau wrote:
> When a DMA transfer is done (ie all bytes have been transfered), the
> corresponding
> Terminal Count bit must be set in the status register.
> This bit is already cleared in i8257_read_cont and i8257_write_cont when
> required.
>
> This fixes
Hi Juan;
We need your assistance in reviewing two competing designs for migrating
some block data so we can move forward with the feature.
First, some background:
What: Block Dirty Bitmaps. They are simple primitives that keep track of
which clusters have been written to since the last incrementa
On Fri, Feb 26, 2016 at 5:24 AM, Peter Maydell wrote:
> The sd.c SD card emulation code can be in a state where the
> SDState BlockBackend pointer is NULL; this is treated as
> "card not present". Add a missing check to sd_get_inserted()
> so that we don't segfault in this situation.
>
> (This cou
Do you have this mirrored in a git repo so I can browse it more
effectively? I can't figure out what all the prerequisite patches are,
so it will be convenient to just have a repo in that case for the RFC.
On 02/17/2016 10:28 AM, Vladimir Sementsov-Ogievskiy wrote:
> This series add persistent dir
On 02/26/2016 03:03 PM, Paolo Bonzini wrote:
>
>
> On 26/02/2016 20:55, Paolo Bonzini wrote:
>>
>>
>> On 19/02/2016 09:51, Markus Armbruster wrote:
Is it an abuse to "Get LBA Status" to return dirty information? Because in
SCSI
the command reports "mapped", "allocated" and "anch
On 02/26/2016 10:55 PM, Paolo Bonzini wrote:
On 19/02/2016 09:51, Markus Armbruster wrote:
Is it an abuse to "Get LBA Status" to return dirty information? Because in SCSI
the command reports "mapped", "allocated" and "anchored" statuses. Does that
mean NBD will use a different status set?
Perh
The new functions handles the data that is taken from the BlockBackend.
Signed-off-by: Kevin Wolf
---
block/qapi.c | 131 +++
1 file changed, 68 insertions(+), 63 deletions(-)
diff --git a/block/qapi.c b/block/qapi.c
index db2d3fb..c04f1d8
Since commit 5ec18f8c, query-blockstats didn't return the statistics of
drives without media any more because such drives have only a BB now,
but not a BDS any more.
This patch fixes the regression so that query-blockstats iterates over
BBs by default and empty drives are displayed again.
Signed-
This series fixes a regression introduced by recent blockdev work. As a nice
side effect, it gets rid of at least one user of bs->blk.
Kevin Wolf (3):
block/qapi: Factor out bdrv_query_blk_stats()
block/qapi: Factor out bdrv_query_bds_stats()
block/qapi: Include empty drives in query-blockst
The new functions handles the data that is taken from the
BlockDriverState.
Signed-off-by: Kevin Wolf
---
block/qapi.c | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/block/qapi.c b/block/qapi.c
index c04f1d8..31ae879 100644
--- a/block/qapi.
On 02/26/2016 11:03 PM, Paolo Bonzini wrote:
On 26/02/2016 20:55, Paolo Bonzini wrote:
On 19/02/2016 09:51, Markus Armbruster wrote:
Is it an abuse to "Get LBA Status" to return dirty information? Because in SCSI
the command reports "mapped", "allocated" and "anchored" statuses. Does that
mea
On 02/22/2016 07:59 AM, Alex Bennée wrote:
> +qemu_set_dfilter_ranges("0x1000+0x100");
> +
> +g_assert_false(qemu_log_in_addr_range(0xfff));
> +g_assert(qemu_log_in_addr_range(0x1000));
> +g_assert(qemu_log_in_addr_range(0x1100));
This is exactly what I was talking about wrt off-by
On 02/22/2016 07:59 AM, Alex Bennée wrote:
> When debugging stuff that occurs over several forks it would be useful
> not to keep overwriting the one logfile you've set-up. This allows a
> simple %d to be included once in the logfile parameter which is
> substituted with getpid().
>
> As the test
On 02/22/2016 07:59 AM, Alex Bennée wrote:
> Each individual architecture needs to use the qemu_log_in_addr_range()
> feature for enabling in_asm output as it is part of the frontend.
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Aurelien Jarno
>
> ---
> v5
> - no longer wrapping tcg_gen_insn
On 02/22/2016 07:59 AM, Alex Bennée wrote:
> My later debugging patches need access to the origin PC which is held in
> the TranslationBlock structure. Pass down the whole structure as it also
> holds the information about the code start point.
>
> Signed-off-by: Alex Bennée
>
> ---
> v1
> - ch
Public bug reported:
[qemu/target-arm/helper.c:5493]: (style) Expression '(X & 0x1f) !=
0xf80f' is always true.
Source code is
(env->uncached_cpsr & CPSR_M) != CPSR_USER &&
but
./qemu/target-arm/cpu.h:#define CPSR_M (0x1fU)
./qemu/target-arm/cpu.h:#define CPSR_USER (CPSR_NZCV | CP
On 25.02.2016 20:41, Peter Maydell wrote:
On 19 February 2016 at 20:04, Edgar E. Iglesias
wrote:
From: "Edgar E. Iglesias"
Add the following flags to the data abort syndrome generator:
* isv - Instruction syndrome valid
* sas - Syndrome access size
* sse - Syndrome sign extend
* srt - Syndrom
On 26/02/2016 20:55, Paolo Bonzini wrote:
>
>
> On 19/02/2016 09:51, Markus Armbruster wrote:
>>> Is it an abuse to "Get LBA Status" to return dirty information? Because in
>>> SCSI
>>> the command reports "mapped", "allocated" and "anchored" statuses. Does that
>>> mean NBD will use a differe
On 19/02/2016 09:51, Markus Armbruster wrote:
>> Is it an abuse to "Get LBA Status" to return dirty information? Because in
>> SCSI
>> the command reports "mapped", "allocated" and "anchored" statuses. Does that
>> mean NBD will use a different status set?
>
> Perhaps some conceptual gymnastics
On Thu, Feb 25, 2016 at 11:15:12PM +0800, Lan Tianyu wrote:
> x2apic feature is in the kvm_default_props and automatically added to all
> CPU models when KVM is enabled. But userspace devices don't support x2apic
> which can't be enabled without the in-kernel irqchip. It will trigger
> warning of "
> From: John Snow [mailto:js...@redhat.com]
> Sent: Friday, 26 February 2016 9:53 AM
>
> On 02/26/2016 12:23 PM, Andrew Baumann wrote:
> >> From: John Snow [mailto:js...@redhat.com]
> >> Sent: Friday, 26 February 2016 9:13 AM
[...]
> >> Andrew, you might want to update the examples on that wiki: i
Quoting Bharata B Rao (2016-02-25 10:22:38)
> Add sPAPR specific CPU core device that is based on generic CPU core device.
> Creating this core device will result in creation of all the CPU thread
> devices that are part of this core.
>
> Signed-off-by: Bharata B Rao
> ---
> hw/ppc/Makefile.objs
On 02/24/2016 06:39 PM, Michael S. Tsirkin wrote:
On Wed, Feb 24, 2016 at 06:33:38PM +0300, Denis V. Lunev wrote:
On 02/24/2016 05:34 PM, Michael S. Tsirkin wrote:
On Wed, Feb 24, 2016 at 10:50:46AM +0300, Denis V. Lunev wrote:
New counter from the Linux kernel +
It is in AKPM's linux-next ke
On 02/26/2016 12:23 PM, Andrew Baumann wrote:
>> From: John Snow [mailto:js...@redhat.com]
>> Sent: Friday, 26 February 2016 9:13 AM
>>
>> On 02/26/2016 04:30 AM, Mats Malmberg wrote:
>>> Hello, thank you for your quick response!
>>>
>>> It helped me to get a little bit further, but unfortunately
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Friday, 26 February 2016 5:24 AM
>
> The sdhci device was missing a DeviceClass reset method;
> implement it. Poweron reset looks the same as reset commanded
> by the guest via the device registers, apart from modelling of
> the rpi '
Alistair Francis writes:
> From: Peter Crosthwaite
>
> Add memory io handlers that glue the register API to the memory API.
> Just translation functions at this stage. Although it does allow for
> devices to be created without all-in-one mmio r/w handlers.
>
> Signed-off-by: Peter Crosthwaite
> From: John Snow [mailto:js...@redhat.com]
> Sent: Friday, 26 February 2016 9:13 AM
>
> On 02/26/2016 04:30 AM, Mats Malmberg wrote:
> > Hello, thank you for your quick response!
> >
> > It helped me to get a little bit further, but unfortunately the problem
> persists.
> > I now get some output
On 02/26/2016 04:30 AM, Mats Malmberg wrote:
> Hello, thank you for your quick response!
>
> It helped me to get a little bit further, but unfortunately the problem
> persists.
> I now get some output from the kernel startup, but I think that it is unable
> to find the provided sd-card image.
Alistair Francis writes:
> This API provides some encapsulation of registers and factors our some
> common functionality to common code. Bits of device state (usually MMIO
> registers), often have all sorts of access restrictions and semantics
> associated with them. This API allow you to define
On 26 February 2016 at 16:51, Alex Bennée wrote:
> I think this needlessly complicates the memory region code and I'm not
> sure what is too be gained for the register code. The only usage of the
> code is inside a loop in register_init_block32. In each case the region
> has the same set of ops. W
Alistair Francis writes:
> Add a function called memory_region_add_subregion_no_print() that
> creates memory subregions that won't be printed when running
> the 'info mtree' command.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: KONRAD Frederic
> ---
>
> include/exec/memory.h | 17 +
On 26 February 2016 at 16:19, Leon Alrae wrote:
> Cluster Power Controller (CPC) is responsible for power management in
> multiprocessing system. It provides registers to control the power and the
> clock frequency of the individual elements in the system.
>
> This patch implements only three regi
On 26 February 2016 at 15:20, Peter Maydell wrote:
> The following changes since commit 4d1e324b2241017c92d816ec3af51a14685dbf62:
>
> Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160226' into
> staging (2016-02-26 12:54:22 +)
>
> are availa
* Dr. David Alan Gilbert (dgilb...@redhat.com) wrote:
> * zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
> > From: root
> >
> > This is the 15th version of COLO (Still only support periodic checkpoint).
> >
> > Here is only COLO frame part, you can get the whole codes from github:
> > htt
On 25.02.2016 17:22, Bharata B Rao wrote:
> Implement query cpu-slots that provides information about hot-plugged
> as well as hot-pluggable CPU slots that the machine supports.
>
> TODO: As Eric suggested use enum for type instead of str.
> TODO: @hotplug-granularity probably isn't required.
>
>
On 19 February 2016 at 20:40, Alistair Francis
wrote:
> Add a generic loader to QEMU which can be used to load images or set
> memory values.
I'm not inherently opposed to this (it seems like a nice way
to deal with the desire to load arbitrary images), but it feels
a bit half-baked at the moment
Cluster Power Controller (CPC) is responsible for power management in
multiprocessing system. It provides registers to control the power and the
clock frequency of the individual elements in the system.
This patch implements only three registers that are used to control the
power state of each VP
On Malta, after reset, only VP0 on Core0 starts the execution. Other VPs
are halted until VP0 powers them up using Cluster Power Controller.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/hw/mips/mips_malta.c
This minimal CPC support is one of the elements required to allow R6 Linux to
bring up Virtual Processors on Malta board. This patch applies on top of
Yongbok's GIC/GCR patchset which still requires updating/fixing (that
probably will also affect CPC, in particular when we come up with a wrapper
fo
Alistair Francis writes:
> This patch series is based on Peter C's original register API. His
> original cover letter is below.
In the next revision you'll need to add the osdep includes that
currently break this when applied to origin/master.
See:
https://travis-ci.org/stsquad/qemu/builds/11
Andrew Jones writes:
> On Fri, Feb 26, 2016 at 02:54:33PM +, Alex Bennée wrote:
>>
>> Andrew Jones writes:
>>
>> > On Fri, Feb 26, 2016 at 01:15:22PM +, Alex Bennée wrote:
>> >> Hi,
>> >>
>> >> Some of these patches have been posted before and previous patches
>> >> have already been ac
On 26 February 2016 at 15:17, Amit Shah wrote:
> The following changes since commit 0c6940d086f39bbf725d96104abe46da87429cb6:
>
> build: [bsd-user] Rename "syscall.h" to "target_syscall.h" in target
> directories (2016-02-25 16:41:08 +)
>
> are available in the git repository at:
>
> http
On 19 February 2016 at 20:40, Alistair Francis
wrote:
> Signed-off-by: Alistair Francis
> ---
>
> docs/generic-loader.txt | 21 +
> 1 file changed, 21 insertions(+)
> create mode 100644 docs/generic-loader.txt
>
> diff --git a/docs/generic-loader.txt b/docs/generic-loader.tx
On 02/25/2016 09:22 AM, Bharata B Rao wrote:
> Implement query cpu-slots that provides information about hot-plugged
> as well as hot-pluggable CPU slots that the machine supports.
>
> TODO: As Eric suggested use enum for type instead of str.
> TODO: @hotplug-granularity probably isn't required.
In v8, the illegal mode changes which are UNPREDICTABLE in v7 are
given architected behaviour:
* the mode field is unchanged
* PSTATE.IL is set (so any subsequent instructions will UNDEF)
* any other CPSR fields are written to as normal
This is pretty much the same behaviour we picked for our
U
On 26 February 2016 at 15:28, Wei Huang wrote:
>
>
> On 02/26/2016 09:06 AM, Peter Maydell wrote:
>> On 26 February 2016 at 14:54, Shannon Zhao wrote:
>>> On 2016/2/26 20:53, Peter Maydell wrote:
I don't understand why a 500ms pulse is better than a short one.
>>> Oh, I just pick a valu
On 02/26/2016 06:14 PM, Amit Shah wrote:
On (Fri) 26 Feb 2016 [17:58:34], Denis V. Lunev wrote:
On 02/26/2016 04:15 PM, Amit Shah wrote:
On (Fri) 26 Feb 2016 [12:23:01], Peter Maydell wrote:
Hi. I'm afraid this causes make check to fail:
Oops, I should've caught that.
/i386/ahci/flush/mi
On Fri, Feb 26, 2016 at 02:54:33PM +, Alex Bennée wrote:
>
> Andrew Jones writes:
>
> > On Fri, Feb 26, 2016 at 01:15:22PM +, Alex Bennée wrote:
> >> Hi,
> >>
> >> Some of these patches have been posted before and previous patches
> >> have already been accepted upstream so I'm tagging t
From: Andrew Baumann
This quirk is a workaround for the following hardware behaviour, on
which UEFI (specifically, the bootloader for Windows on Pi2) depends:
1. at boot with an SD card present, the interrupt status/enable
registers are initially zero
2. upon enabling it in the interrupt enab
From: Andrew Baumann
This reverts commit 723697551a7e926abe7d3c7f2966012b8075143d.
This change was poorly tested on my part. It squelched card insertion
interrupts on reset, but that was not necessary because sdhci_reset()
clears all the registers (via the call to memset), so the subsequent
sdhc
Signed-off-by: Pranith Kumar
---
cpus.c | 4 ++--
qemu-options.hx | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index 9592163..bc774e2 100644
--- a/cpus.c
+++ b/cpus.c
@@ -630,7 +630,7 @@ void configure_icount(QemuOpts *opts, Error **errp)
icount sleep takes on or off as options. A few places mention sleep=no
which is not accepted. This patch corrects them.
Signed-off-by: Pranith Kumar
---
cpus.c | 4 ++--
qemu-options.hx | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index 9592
The following changes since commit 4d1e324b2241017c92d816ec3af51a14685dbf62:
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160226' into staging
(2016-02-26 12:54:22 +)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
The v8 ARM ARM defines that unused spaces in the ID_AA64* system
register ranges are Reserved and must RAZ, rather than being UNDEF.
Implement this.
In particular, ARM v8.2 adds a new feature register ID_AA64MMFR2,
and newer versions of the Linux kernel will attempt to read this,
which causes them
We don't actually support Hyp mode yet, but add the correct
checks for it to the bad_mode_switch() function for completeness.
Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
Message-id: 146977-3644-8-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 3 +++
1 file ch
On 02/26/2016 09:06 AM, Peter Maydell wrote:
> On 26 February 2016 at 14:54, Shannon Zhao wrote:
>> On 2016/2/26 20:53, Peter Maydell wrote:
>>> I don't understand why a 500ms pulse is better than a short one.
>>>
>> Oh, I just pick a value which seems like a real latency for pressing a
>> butto
From: Sascha Silbe
The VMState API is rather sparsely documented. Start by describing the
meaning of all VMStateFlags.
Reviewed-by: Amit Shah
Reviewed-by: Juan Quintela
Signed-off-by: Sascha Silbe
Message-Id: <1456474693-11662-1-git-send-email-si...@linux.vnet.ibm.com>
Signed-off-by: Amit Sha
From: "Edgar E. Iglesias"
Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW due to the register not
having any underlying state. This fixes an issue with booting
KVM enabled kernels when EL2 is on.
Signed-off-by: Edgar E. Iglesias
Message-id: 1456490739-19343-1-git-send-email-edgar.igles...@gmail.com
Review
From: "Denis V. Lunev"
There is a possibility to hit an assert in qcow2_get_specific_info that
s->qcow_version is undefined. This happens when VM in starting from
suspended state, i.e. it processes incoming migration, and in the same
time 'info block' is called.
The problem is that qcow2_invalid
From: Wei Huang
pl061.c emulates two GPIO devices, ARM PL061 and TI Stellaris, which
share the same read/write functions (pl061_read and pl061_write).
However PL061 and Stellaris have different GPIO register definitions
and pl061_read()/pl061_write() doesn't check it. This patch enforces
checking
From: Thomas Huth
Some header files in the include/hw/arm/ directory can be assigned
to entries in the MAINTAINERS file.
Signed-off-by: Thomas Huth
Message-id: 1456399324-24259-1-git-send-email-th...@redhat.com
Signed-off-by: Peter Maydell
---
MAINTAINERS | 4
1 file changed, 4 insertion
From: Thomas Huth
Signed-off-by: Thomas Huth
Reviewed-by: Amit Shah
Message-Id: <1456393669-20678-1-git-send-email-th...@redhat.com>
Signed-off-by: Amit Shah
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 606d9c0..5fafa81 100644
--- a/MAINT
If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to
NonSecure PL1 modes are illegal mode changes. Implement this check
in bad_mode_switch().
(We don't currently implement HCR.TGE, but this is the only missing
check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the
rest of
The only case where we can attempt a cpsr_write() mode switch from
User is from the gdbstub; all other cases are handled in the
calling code (notably translate.c). Architecturally attempts to
alter the mode bits from user mode are simply ignored (and not
treated as a bad mode switch, which in v8 se
From: Andrew Baumann
Recent changes to sdhci broke SD on raspi. This change mirrors
the logic to create the SD card device at the board level.
Signed-off-by: Andrew Baumann
Message-id: 1456351128-5560-1-git-send-email-andrew.baum...@microsoft.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter
On (Fri) 26 Feb 2016 [17:58:34], Denis V. Lunev wrote:
> On 02/26/2016 04:15 PM, Amit Shah wrote:
> >On (Fri) 26 Feb 2016 [12:23:01], Peter Maydell wrote:
> >>Hi. I'm afraid this causes make check to fail:
> >Oops, I should've caught that.
> >
> >> /i386/ahci/flush/migrate:
> >> /i386/ahci/mig
When linux-user code is calling cpsr_write(), use a restrictive
mask to ensure we are limiting the set of CPSR bits we update.
In particular, don't allow the mode bits to be changed.
Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
Message-id: 146977-3644-5-git-send-email-peter.mayd.
Add an argument to cpsr_write() to indicate what kind of CPSR
write is being requested, since the exact behaviour should
differ for the different cases.
Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
Message-id: 146977-3644-3-git-send-email-peter.mayd...@linaro.org
---
linux-user/
In v8 trying to switch mode to Mon from Secure EL1 is an
illegal mode switch. (In v7 this is impossible as all secure
modes except User are at EL3.) We can handle this case by
making a switch to Mon valid only if the current EL is 3,
which then gives the correct answer whether EL3 is AArch32
or AAr
QEMU doesn't implement the NSACR.RFR bit, which is a permitted
IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8.
Add a comment to bad_mode_switch() to note that this is why
FIQ is always a valid mode regardless of the CPU's Secure state.
Signed-off-by: Peter Maydell
Reviewed-by: S
Mode switches from Hyp to any other mode via the CPS and MRS
instructions are illegal mode switches (though obviously switching
via exception return is valid). Add this check to bad_mode_switch().
Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
Message-id: 146977-3644-11-git-send-e
Implement the performance monitor register traps controlled
by MDCR_EL3.TPM and MDCR_EL2.TPM. Most of the performance
registers already have an access function to deal with the
user-enable bit, and the TPM checks can be added there. We
also need a new access function which only implements the
TPM c
icount sleep takes on or off as options. A few places mention sleep=no
which is not accepted. This patch corrects them.
Signed-off-by: Pranith Kumar
---
cpus.c | 4 ++--
qemu-options.hx | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index 9592
Fix two issues with our implementation of the SDCR:
* it is only present from ARMv8 onwards
* it does not contain several of the trap bits present in its 64-bit
counterpart the MDCR_EL3
Put the register description in the right place so that it does not
get enabled for ARMv7 and earlier, and
On Thu, 25 Feb 2016 21:52:39 +0530
Bharata B Rao wrote:
> Initialize boot CPUs as spapr-cpu-core devices and create links from
> machine object to these core devices. These links can be considered
> as CPU slots in which core devices will get hot-plugged. spapr-cpu-core
> device's slot property i
Raw CPSR writes should skip the architectural checks for whether
we're allowed to set the A or F bits and should also not do
the switching of register banks if the mode changes. Handle
this inside cpsr_write(), which allows us to drop the "manually
set the mode bits to avoid the bank switch" code f
Now that there is a set_blocking callback in QEMUFileOps,
and all users needing non-blocking support have been
converted to QIOChannel, there is no longer any codepath
requiring the qemu_get_fd() method for QEMUFile. Remove it
to avoid further code being introduced with an expectation
of direct fil
The rules for setting the CPSR on a 32-bit exception return are
subtly different from those for setting the CPSR via an instruction
like MSR or CPS. (In particular, in Hyp mode changing the mode bits
is not valid via MSR or CPS.) Split the exception-return case into
its own helper for setting CPSR,
From: Wei Yang
In qemu_savevm_state_complete_precopy(), it iterates on each device to add
a json object and transfer related status to destination, while the order
of the last two steps could be refined.
Current order:
json_start_object()
save_section_header()
vmstate_save()
All the remaining QEMUFile implementations provide an iovec
based write handler, so the put_buffer callback can be removed
to simplify the code.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Daniel P. Berrange
---
include/migration/qemu-file.h | 9 -
migration/qemu-file.c
From: "Denis V. Lunev"
There is a possibility to hit an assert in qcow2_get_specific_info that
s->qcow_version is undefined. This happens when VM in starting from
suspended state, i.e. it processes incoming migration, and in the same
time 'info block' is called.
The problem is that qcow2_invalid
From: Matthew Fortune
sys/eventfd.h was being guarded only by a check for linux but does
not exist on older distributions like CentOS 5. Move the include
into the code that uses it and add an appropriate guard.
Signed-off-by: Matthew Fortune
Reviewed-by: Juan Quintela
Message-Id: <6d39441bf12e
The post-copy code does some I/O to/from an intermediate
in-memory buffer rather than direct to the underlying
I/O channel. Switch this code to use QIOChannelBuffer
instead of QEMUSizedBuffer.
Signed-off-by: Daniel P. Berrange
---
docs/migration.txt | 4 ++--
include/sysemu/sysemu.h | 2 +
The following changes since commit 0c6940d086f39bbf725d96104abe46da87429cb6:
build: [bsd-user] Rename "syscall.h" to "target_syscall.h" in target
directories (2016-02-25 16:41:08 +)
are available in the git repository at:
https://git.kernel.org/pub/scm/virt/qemu/amit/migration.git
tags
Now that the tcp, unix and fd migration backends have converted
to use the QIOChannel based QEMUFile, there is no user remaining
for the sockets based QEMUFile impl and it can be deleted.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Daniel P. Berrange
---
include/migration/qemu-file.h |
Currently if an app initiates an outgoing migration, it
may or may not, get an error reported back on failure. If
the error occurs synchronously to the 'migrate' command
execution, the client app will see the error message. This
is the case for DNS lookup failures. If the error occurs
asynchronousl
This extends the migration_set_incoming_channel and
migration_set_outgoing_channel methods so that they
will automatically wrap the QIOChannel in a
QIOChannelTLS instance if TLS credentials are configured
in the migration parameters.
This allows TLS to work for tcp, unix, fd and exec
migration pro
Convert the exec savevm code to use QIOChannel and QEMUFileChannel,
instead of the stdio APIs.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Daniel P. Berrange
---
migration/savevm.c | 8 +---
tests/Makefile | 4 ++--
tests/test-vmstate.c | 11 ++-
3 files changed, 17
Define two new migration parameters to be used with TLS encryption.
The 'tls-creds' parameter provides the ID of an instance of the
'tls-creds' object type, or rather a subclass such as 'tls-creds-x509'.
Providing these credentials will enable use of TLS on the migration
data stream.
If using x509
Introduce a new QEMUFile implementation that is based on
the QIOChannel objects. This impl is different from existing
impls in that there is no file descriptor that can be made
available, as some channels may be based on higher level
protocols such as TLS.
Although the QIOChannel based implementat
Now that we don't have have a buffer based QemuFile
implementation, the QEMUSizedBuffer code is also
unused and can be deleted. A simpler buffer class
also exists in util/buffer.c which other code can
used as needed.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Daniel P. Berrange
---
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