On Wed, Jun 17, 2015 at 08:52:42AM +0200, Markus Armbruster wrote:
> "Dr. David Alan Gilbert (git)" writes:
>
> > From: "Dr. David Alan Gilbert"
> >
> > Older QEMUs dont understand the new (sub)sections that
> > may be generated in the serial device. Limit their generation
> > to newer machine
On Tue, Jun 16, 2015 at 09:03:44AM -0600, Eric Blake wrote:
> On 06/16/2015 06:53 AM, Michael S. Tsirkin wrote:
> > makes it possible to copy error_abort pointers,
> > not just pass them on directly.
> >
> > Signed-off-by: Michael S. Tsirkin
> > ---
> > util/error.c | 16 +++-
> > 1
"Dr. David Alan Gilbert (git)" writes:
> From: "Dr. David Alan Gilbert"
>
> Older QEMUs dont understand the new (sub)sections that
> may be generated in the serial device. Limit their generation
> to newer machine types.
Please explain briefly what state migration can lose with old machine
ty
On Wed, Jun 17, 2015 at 09:06:47AM +0800, Shannon Zhao wrote:
>
>
> On 2015/6/16 22:19, Michael S. Tsirkin wrote:
> > On Tue, Jun 16, 2015 at 09:33:19AM +0800, Shannon Zhao wrote:
> >>
> >>
> >> On 2015/6/16 2:13, Michael S. Tsirkin wrote:
> >>> On Mon, Jun 15, 2015 at 05:59:06PM +0100, Peter May
On Wed, Jun 17, 2015 at 09:41:40AM +0800, Chen Fan wrote:
>
> On 06/16/2015 06:20 PM, Michael S. Tsirkin wrote:
> >On Tue, Jun 16, 2015 at 04:10:57PM +0800, Chen Fan wrote:
> >>Particularly, For vfio devices, Once need to recovery devices
> >>by bus reset such as AER, we always need to reset the h
On Di, 2015-06-16 at 16:16 +0100, Dr. David Alan Gilbert wrote:
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > On 16 June 2015 at 08:57, Gerd Hoffmann wrote:
> > > Hi,
> > >
> > > This pull request almost completes virtio-gpu support, by adding pci
> > > support (virtio-gpu-pci) and a v
Peter Crosthwaite writes:
> On Tue, Jun 16, 2015 at 8:09 AM, Markus Armbruster wrote:
>> Peter Crosthwaite writes:
>>
>>> The monitor currently has one helper, mon_get_cpu() which will return
>>> an env pointer. The target specific users of this API want an env, but
>>> all the target agnostic
On Wed, Jun 17, 2015 at 12:16:09PM +0800, Jason Wang wrote:
>
>
> On 06/16/2015 04:16 PM, Thibaut Collet wrote:
> > For a live migration my understanding is there are a suspend resume
> > operation:
> > - The VM image is regularly copied from the old host to the new one
> > (modified pages due t
On 06/16/2015 10:08 PM, Alex Williamson wrote:
On Tue, 2015-06-16 at 16:10 +0800, Chen Fan wrote:
On 06/10/2015 05:24 AM, Alex Williamson wrote:
On Tue, 2015-06-09 at 11:37 +0800, Chen Fan wrote:
the vfio_pci_hot_reset differentiate the single and multi in-used
devices for reset. but sometime
On Wed, 27 May 2015 19:52:56 +0200
Markus Armbruster wrote:
> Since we now require GLib 2.22+ (commit f40685c), we don't have to
> work around lack of g_hash_table_iter_init() & friends anymore.
>
> This reverts commit f8833a37c0c6b22ddd57b45e48cfb0f97dbd5af4.
>
> Signed-off-by: Markus Armbrust
On Tue, Jun 16, 2015 at 08:30:42PM +0200, Laszlo Ersek wrote:
> OVMF downloads the ACPI linker/loader script from QEMU when the edk2 PCI
> Bus driver globally signals the firmware that PCI enumeration and resource
> allocation have completed. At this point QEMU regenerates the ACPI payload
> in an
On Tue, Jun 16, 2015 at 8:09 AM, Markus Armbruster wrote:
> Peter Crosthwaite writes:
>
>> The monitor currently has one helper, mon_get_cpu() which will return
>> an env pointer. The target specific users of this API want an env, but
>> all the target agnostic users really just want the cpu poin
On 06/16/2015 04:16 PM, Thibaut Collet wrote:
> For a live migration my understanding is there are a suspend resume operation:
> - The VM image is regularly copied from the old host to the new one
> (modified pages due to VM operation can be copied several time)
> - As soon as there are only few
On 06/16/2015 04:18 PM, Pankaj Gupta wrote:
> We use vhostforce to enable vhost even if Guests don't have MSI-X support
> and we fall back to QEMU virtio-net. This patch will enable vhost
> unconditionally
> whenever we have vhostforce='ON' or vhost='ON'.
>
> Initially, I wanted to remove vhos
On Mon, Jun 15, 2015 at 01:31:20PM -0300, Eduardo Habkost wrote:
> On Fri, Jun 12, 2015 at 02:30:27PM +0530, Bharata B Rao wrote:
> > Store memory address range information of boot memory in address
> > range list of numa_info.
> >
> > This helps to have a common NUMA node lookup by address funct
On Tue, Jun 16, 2015 at 7:59 PM, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Here we add a member in MachineState to store the irq array returned
> from qemu_allocate_irqs. Then these irq arrays will be free before QEMU
> exit and it will be used to fix the memory leak due to misuse
> qemu_alloc
Hi Peter, Andreas,
It's been a while since a QOM PULL and there are a good number of
already-reviewed patches on list. Is Andreas on vacation and returning
before hard freeze or should we do a PULL in the meantime?
Regards,
Peter
From: Shannon Zhao
These are relevant to memory leak in machine init function. Here we add
a member in MachineState to store irq array returned from
qemu_allocate_irqs.
PS. These patches are split from my previous patchset [1] since they are
relevant to MachineState.
Thanks,
Shannon
[1] [PATCH
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/spitz.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 5bf032a..454919d 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -812,8 +812,8 @@
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/ppc/ppc440_bamboo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 778970a..944999d 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -
From: Shannon Zhao
Here we add a member in MachineState to store the irq array returned
from qemu_allocate_irqs. Then these irq arrays will be free before QEMU
exit and it will be used to fix the memory leak due to misuse
qemu_allocate_irqs.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zh
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/tosa.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 73572eb..4711514 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -85,10 +85,8 @@ sta
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/sh4/r2d.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 5e22ed7..7f621b2 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -261,6 +261,7 @@ static void r2d_init(MachineState
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/sparc/leon3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 7f5dcd6..6733ebb 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -140,6 +140,7 @@ static void le
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/palm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 7f1cfb8..6fe28e5 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -156,7 +156,7 @@ static
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/m68k/an5206.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c
index f63ab2b..6ebf2d2 100644
--- a/hw/m68k/an5206.c
+++ b/hw/m68k/an5206.c
@@ -58,7 +58,7 @@
We now use the helper everywhere, so no need to call this on this two
places. See on previous commit that there were a place where we missed
to mark the trace. Now all tracing is done in migrate_set_state().
Signed-off-by: Juan Quintela
---
migration/migration.c | 2 --
1 file changed, 2 delet
cmpxchg returns the old value
Signed-off-by: Juan Quintela
---
migration/migration.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/migration/migration.c b/migration/migration.c
index f1ecf76..1791185 100644
--- a/migration/migration.c
+++ b/migration/migration.c
@@ -505,7 +
It needs to be the first one and it is not optional, that is the reason
why it is opencoded. For new machine types, it is required than machine
type name is the same in both sides.
It is just done right now for pc's.
Signed-off-by: Juan Quintela
---
hw/i386/pc_piix.c | 1 +
hw/i38
There were three places that were not using the migrate_set_state()
helper, just fix that.
Signed-off-by: Juan Quintela
---
migration/migration.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/migration/migration.c b/migration/migration.c
index 1791185..1c84249 100644
To make sections optional, we need to do it at the beggining of the code.
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
---
include/migration/vmstate.h | 2 ++
migration/savevm.c | 8
migration/vmstate.c | 11 +++
trace-events
We reuse the migration events from the source side, sending them on the
appropiate place.
Signed-off-by: Juan Quintela
Reviewed-by: Eric Blake
---
migration/migration.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/migration/migration.c b/migration/migration.c
index 36
We have one argument that tells us what event has happened.
Signed-off-by: Juan Quintela
X3
Signed-off-by: Juan Quintela
---
docs/qmp/qmp-events.txt | 14 ++
migration/migration.c | 2 ++
qapi/event.json | 14 ++
3 files changed, 30 insertions(+)
diff --git
Hi
As the beggining of both series have been accepted, I merged both here.
Changes:
- answered all comments on list and applied suggested changes
- Use migrate_set_state() consistently
- we were misusing atomic_cmpxchg(), it didn't matter until now because
we were missing only traces, but it s
Next commit would allow to move from incoming migration to error happening on
source.
Should we add more states to this transition? Luiz?
Signed-off-by: Juan Quintela
---
vl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/vl.c b/vl.c
index c659a00..555fd88 100644
--- a/vl.c
+++ b/vl.c
This section would be sent:
a- for all new machine types
b- for old achine types if section state is different form {running,paused}
that were the only giving us troubles.
So, in new qemus: it is alwasy there. In old qemus: they are only
there if it an error has happened, basically stoping on
This includes a new section that for now just stores the current qemu state.
Right now, there are only one way to control what is the state of the
target after migration.
- If you run the target qemu with -S, it would start stopped.
- If you run the target qemu without -S, it would run just after
This allows us to store the current state to send it through migration.
Signed-off-by: Juan Quintela
---
include/sysemu/sysemu.h | 1 +
vl.c| 12
2 files changed, 13 insertions(+)
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 0304aa7..d7b
ping...
On 06/08/2015 06:35 PM, Zhu Guihua wrote:
ICC Bus was used for providing a hotpluggable bus for APIC and CPU,
but now we use HotplugHandler to make hotplug. So ICC Bus is
unnecessary.
This code has passed the new pc-cpu-test.
And I have tested with kvm along with kernel_irqchip=on/off,
On 06/16/2015 06:20 PM, Michael S. Tsirkin wrote:
On Tue, Jun 16, 2015 at 04:10:57PM +0800, Chen Fan wrote:
Particularly, For vfio devices, Once need to recovery devices
by bus reset such as AER, we always need to reset the host bus
to recovery the devices under the bus, so we need to add pci b
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> It needs to be the first one and it is not optional, that is the reason
>> why it is opencoded. For new machine types, it is required than machine
>> type name is the same in both sides.
>>
>> It is just done right
On Tue, Jun 16, 2015 at 06:21:56PM -0700, Peter Crosthwaite wrote:
> On Tue, Jun 16, 2015 at 6:12 PM, Edgar E. Iglesias
> wrote:
> > On Tue, Jun 16, 2015 at 06:09:22PM -0700, Peter Crosthwaite wrote:
> >> On Tue, Jun 16, 2015 at 5:54 PM, Edgar E. Iglesias
> >> wrote:
> >> > On Tue, Jun 16, 2015 a
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> This section would be sent:
>>
>> a- for all new machine types
>> b- for old achine types if section state is different form {running,paused}
>>that were the only giving us troubles.
>>
>> So, in new qemus: it
On Tue, Jun 16, 2015 at 05:36:14PM -0700, Peter Crosthwaite wrote:
> The CPUs currently supported by zynqmp are the APU (application
> processing unit) CPUs. There are other CPUs in Zynqmp so unqualified
> "cpus" in ambiguous. Preface the variables with "APU" accordingly, to
> prepare support addin
On Tue, Jun 16, 2015 at 6:12 PM, Edgar E. Iglesias
wrote:
> On Tue, Jun 16, 2015 at 06:09:22PM -0700, Peter Crosthwaite wrote:
>> On Tue, Jun 16, 2015 at 5:54 PM, Edgar E. Iglesias
>> wrote:
>> > On Tue, Jun 16, 2015 at 05:36:19PM -0700, Peter Crosthwaite wrote:
>> >> Add the 2xCortexR5 CPUs to z
On Tue, Jun 16, 2015 at 05:36:12PM -0700, Peter Crosthwaite wrote:
> Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,
> and both thumb and ARM div instructions.
>
> Also implement dummy ATCM and BTCM. These CPs are defined for R5 but
> don't have a lot of meaning in QEMU yet. Raz
On Tue, Jun 16, 2015 at 06:09:22PM -0700, Peter Crosthwaite wrote:
> On Tue, Jun 16, 2015 at 5:54 PM, Edgar E. Iglesias
> wrote:
> > On Tue, Jun 16, 2015 at 05:36:19PM -0700, Peter Crosthwaite wrote:
> >> Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset
> >> (this is true of
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> This includes a new section that for now just stores the current qemu state.
>>
>> Right now, there are only one way to control what is the state of the
>> target after migration.
>>
>> - If you run the target qemu
On Tue, Jun 16, 2015 at 5:54 PM, Edgar E. Iglesias
wrote:
> On Tue, Jun 16, 2015 at 05:36:19PM -0700, Peter Crosthwaite wrote:
>> Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset
>> (this is true of real hardware) by default or selectable as the boot
>> processor.
>
> Hi Pete
On 2015/6/16 22:19, Michael S. Tsirkin wrote:
> On Tue, Jun 16, 2015 at 09:33:19AM +0800, Shannon Zhao wrote:
>>
>>
>> On 2015/6/16 2:13, Michael S. Tsirkin wrote:
>>> On Mon, Jun 15, 2015 at 05:59:06PM +0100, Peter Maydell wrote:
On 15 June 2015 at 17:32, Andrew Jones wrote:
> On Mon,
On Tue, Jun 16, 2015 at 05:36:19PM -0700, Peter Crosthwaite wrote:
> Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset
> (this is true of real hardware) by default or selectable as the boot
> processor.
Hi Peter,
I think it would be good if you could model at least a minimal
"Denis V. Lunev" wrote:
> On 14/05/15 19:28, Juan Quintela wrote:
>> This allows us to store the current state to send it through migration.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> include/sysemu/sysemu.h | 1 +
>> vl.c| 11 +++
>> 2 files changed, 12 inserti
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> Given a string state, we need a way to get the RunState for that string.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> include/sysemu/sysemu.h | 1 +
>> vl.c| 13 +
>> 2 files chang
Hi,
I'm having trouble running a simple multithreaded program on a PowerPC host
machine.
The machine I'm using is a ppc VM--I think it's running under KVM (I'm using
OVH's RunAbove Power8 service):
admin@adsf:~/qemu$ uname -a
Linux adsf 3.13.0-37-generic #64-Ubuntu SMP Mon Sep 22 21:27:09 UT
Add a string property that specifies the primary boot cpu. All CPUs
except the one selected will start-powered-off. This allows for elf
boots on any CPU, which prepares support for booting R5 elfs directly
on the R5 processors.
Signed-off-by: Peter Crosthwaite
---
hw/arm/xlnx-ep108.c |
Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset
(this is true of real hardware) by default or selectable as the boot
processor.
Signed-off-by: Peter Crosthwaite
---
changed since v2:
Add boot-cpu start-powered-off conditional
changed since v1:
s/rcpu/rpu-cpu/
hw/arm/xlnx-
The CPUs currently supported by zynqmp are the APU (application
processing unit) CPUs. There are other CPUs in Zynqmp so unqualified
"cpus" in ambiguous. Preface the variables with "APU" accordingly, to
prepare support adding the RPU (realtime processing unit) processors.
Signed-off-by: Peter Cros
Define the MPUIR register for MPU supporting ARMv6 and onwards.
Currently we only support unified MPU.
The size of the unified MPU is defined via the number of "dregions".
So just a single config is added to specify this size. (When split MPU
is implemented we will add an extra iregions config).
Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,
and both thumb and ARM div instructions.
Also implement dummy ATCM and BTCM. These CPs are defined for R5 but
don't have a lot of meaning in QEMU yet. Raz them so the guest can
proceed if they are read. The TCM registers will retur
Define the arm CP registers for PMSAv7 and their accessor functions.
RGNR serves as a shared index that indexes into arrays storing the
DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd
separately from the CP interface using a new PMSA specific VMSD
subsection.
Reviewed-by: Peter
Hi Peter and all,
This patch series adds ARM Cortex R5 processor support. The PMSAv7 MPU
is implemented. Two R5s are added to the Xilinx ZynqMP SoC.
Changed since v2:
Rebased (early patches merged)
Added boot CPU selection.
Addressed PMM review (see indiv. patches)
Changed since v1:
Addressed PM
Unified MPU only. Uses ARM architecture major revision to switch
between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains
unsupported and is asserted against.
Reviewed-by: Peter Maydell
Signed-off-by: Peter Crosthwaite
---
changed since v2
Add missing -1 on initialiser
Use default if d
Eric Blake wrote:
D> On 05/18/2015 03:58 AM, Dr. David Alan Gilbert wrote:
>> * Juan Quintela (quint...@redhat.com) wrote:
>>> Given a string state, we need a way to get the RunState for that string.
>>>
>>> Signed-off-by: Juan Quintela
>>> ---
>>> include/sysemu/sysemu.h | 1 +
>>> vl.c
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> This allows us to store the current state to send it through migration.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> include/sysemu/sysemu.h | 1 +
>> vl.c| 11 +++
>> 2 files changed,
On Tue, Jun 16, 2015 at 3:25 PM, Liviu Ionescu wrote:
>
>> On 16 Jun 2015, at 19:10, Peter Crosthwaite
>> wrote:
>>
>> ... In my proposal the machine model would do this.
>>
>> qdev_connect_gpio_out_named(mcu, "name", index, qdev_get_gpio_in(gpio_dev,
>> 0));
>>
>> Or something like that.
>
> c
Eric Blake wrote:
> On 05/20/2015 09:35 AM, Juan Quintela wrote:
>> We have one argument that tells us what event has happened.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> docs/qmp/qmp-events.txt | 16
>> migration/migration.c | 12
>> qapi/event.json |
Jiri Denemark wrote:
> On Wed, May 20, 2015 at 17:35:23 +0200, Juan Quintela wrote:
>> We have one argument that tells us what event has happened.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> docs/qmp/qmp-events.txt | 16
>> migration/migration.c | 12
>> qapi/ev
On Tue, 16 Jun 2015 17:11:03 +0300
Gal Hammer wrote:
> Signed-off-by: Gal Hammer
> ---
> tests/Makefile | 2 ++
> tests/vmgenid-test.c | 44
> 2 files changed, 46
> insertions(+) create mode 100644 tests/vmgenid-test.c
>
> diff --git a/tests/M
On Tue, 16 Jun 2015 17:11:02 +0300
Gal Hammer wrote:
> Based on Microsoft's specifications (paper can be downloaded from
> http://go.microsoft.com/fwlink/?LinkId=260709), add a device
> description to the SSDT ACPI table and its implementation.
>
> The GUID is set using a global "vmgenid.uuid" p
On Tue, 16 Jun 2015 17:11:01 +0300
Gal Hammer wrote:
> Add a new method to the AcpiDeviceIfClass interface. The new
> method sends an ACPI notfication when the VM generation id is
> changed.
>
> Signed-off-by: Gal Hammer
> ---
> hw/acpi/core.c | 8
> hw/acpi/ich9
On Tue, 16 Jun 2015 17:11:02 +0300
Gal Hammer wrote:
> Based on Microsoft's specifications (paper can be downloaded from
> http://go.microsoft.com/fwlink/?LinkId=260709), add a device
> description to the SSDT ACPI table and its implementation.
>
> The GUID is set using a global "vmgenid.uuid" p
> On 16 Jun 2015, at 19:10, Peter Crosthwaite
> wrote:
>
> ... In my proposal the machine model would do this.
>
> qdev_connect_gpio_out_named(mcu, "name", index, qdev_get_gpio_in(gpio_dev,
> 0));
>
> Or something like that.
connecting a gpio_out to a gpio_in seems not possible, gpio_in irq
[This Week]
- Fix ppc: mem_claim() and mmu_claim()
- Remove extraneous "interrupts" property from /pci/mac-io
- I'm having trouble tracking down where the property is actually being
set. The mac-io devices are defined in drivers/pci_database.c, but the
pci_dev_t struct (drivers/
Am 16.06.2015 um 23:08 schrieb Alexander Graf:
> We now finally have TCG support for the basic set of instructions necessary
> to run the s390-ccw machine. That means in any aspect possible that machine
> type is now superior to the legacy s390-virtio machine.
>
> Switch over to the ccw machine as
On 2015-06-16 23:08, Alexander Graf wrote:
> We now finally have TCG support for the basic set of instructions necessary
> to run the s390-ccw machine. That means in any aspect possible that machine
> type is now superior to the legacy s390-virtio machine.
>
> Switch over to the ccw machine as def
On Tue, Jun 16, 2015 at 09:08:16AM -0600, Eric Blake wrote:
> On 06/16/2015 06:53 AM, Michael S. Tsirkin wrote:
> > We probably should just switch everyone, this is
> > just to demonstrate the API usage.
> >
> > Signed-off-by: Michael S. Tsirkin
> > ---
> > block/nfs.c | 2 +-
> > 1 file changed
We now finally have TCG support for the basic set of instructions necessary
to run the s390-ccw machine. That means in any aspect possible that machine
type is now superior to the legacy s390-virtio machine.
Switch over to the ccw machine as default. That way people don't get a halfway
broken mach
The MOVE LONG instruction should pad the destination operand with the
byte from bit positions 32-39 of the source length (r2 + 1), not with
the same byte in the source address.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/mem_helper.c | 2 +-
1 file c
On Tue, Jun 16, 2015 at 07:54:09PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Older QEMUs dont understand the new (sub)sections that
> may be generated in the serial device. Limit their generation
> to newer machine types.
>
> Signed-off-by: Dr. David Alan
On Tue, Jun 16, 2015 at 12:22 PM, Liviu Ionescu wrote:
>
>> On 16 Jun 2015, at 21:19, Peter Crosthwaite
>> wrote:
>>
>> Your autoformatter does a surprisingly good job of getting close to
>> qemu coding style. Can the rules just be tweaked any maybe QEMU coding
>> style can be added to eclipse?
On Fri, Jun 12, 2015 at 12:10 PM, Peter Crosthwaite
wrote:
> Unified MPU only. Uses ARM architecture major revision to switch
> between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains
> unsupported and is asserted against.
>
> Signed-off-by: Peter Crosthwaite
> ---
> changed since v1 (
> On 16 Jun 2015, at 21:19, Peter Crosthwaite
> wrote:
>
> Your autoformatter does a surprisingly good job of getting close to
> qemu coding style. Can the rules just be tweaked any maybe QEMU coding
> style can be added to eclipse?
this is exactly what I did, I took the K&R and tweaked it whe
On Mon, Jun 15, 2015 at 6:44 AM, Peter Maydell wrote:
> On 12 June 2015 at 20:10, Peter Crosthwaite
> wrote:
>> Define the MPUIR register for MPU supporting systems V6 onwards.
>
> "(ARMv6 and onwards)".
>
>> Currently only support unified MPU.
>
> "we only"
>
>> The size of the unified MPU is su
On 06/16/2015 12:25 PM, Eric Blake wrote:
> On 06/16/2015 10:02 AM, John Snow wrote:
>> The only guidance the AHCI specification gives on memory access
>> is: "Register accesses shall have a maximum size of 64-bits;
>> 64-bit access must not cross an 8-byte alignment boundary."
>>
>> I interpret
From: "Dr. David Alan Gilbert"
Older QEMUs dont understand the new (sub)sections that
may be generated in the serial device. Limit their generation
to newer machine types.
Signed-off-by: Dr. David Alan Gilbert
---
hw/char/serial.c | 19 +--
hw/i386/pc_piix.c|
SeaBIOS expects OpenFirmware device paths in the "bootorder" fw_cfg file
to follow the pattern
/pci-root@N/pci@i0cf8/...
for devices that live behind an extra root bus. The extra root bus in
question is the N'th among the extra root bridges. (In other words, N
gives the position of the affected
This is done mainly for improving readability, and in preparation for the
next patch, but Markus pointed out another bonus for the string being
returned:
"No arbitrary length limit. Before the patch, it's 39 characters, and the
code breaks catastrophically when qdev_fw_name() is longer: the second
The sysbus_get_fw_dev_path() function formats OpenFirmware device path
nodes ("driver-name@unit-address") for sysbus devices. The first choice
for "unit-address" is the base address of the device's first MMIO region.
The second choice is its first IO port.
However, if two sysbus devices with the s
No functional changes whatsoever; addressing commit message, code
comment, and coding style remarks from Markus. Those updates are listed
individually per patch. I added / preserved all Tested-by and
Reviewed-by tags I got for v4.
Cc: Marcel Apfelbaum
Cc: Michael S. Tsirkin
Cc: Markus Armbruster
OVMF downloads the ACPI linker/loader script from QEMU when the edk2 PCI
Bus driver globally signals the firmware that PCI enumeration and resource
allocation have completed. At this point QEMU regenerates the ACPI payload
in an fw_cfg read callback, and this is when the PXB's _CRS gets
populated.
On Tue, Jun 16, 2015 at 10:16 AM, Liviu Ionescu wrote:
>
>> On 16 Jun 2015, at 19:10, Peter Crosthwaite
>> wrote:
>>
>>> +bool use_stderr;
>>
>> Why do you want to switch between stderr and stdout?
>
> I wasn't sure which one is more appropriate, I first used stdout then tried
> stderr.
>
>
On 13.06.15 00:45, Aurelien Jarno wrote:
> This patch set adds support for the Program-Event Recording (PER)
> feature. It implements all the PER functionalities except the
> following ones:
> - zero-address-detection event (part of the zero-address-detection
> facility)
> - transaction-end eve
On 16.06.15 19:44, Aurelien Jarno wrote:
> On 2015-06-16 18:44, Alexander Graf wrote:
>> On 06/13/15 00:46, Aurelien Jarno wrote:
>>> This patch adds support for PER Breaking-Event-Address register. Like
>>> real hardware, it save the current PSW address when the PSW address is
>>> changed by an
On 2015-06-15 22:44, Hervé Poussineau wrote:
> Hi Aurelien,
>
> Le 12/06/2015 01:30, Aurelien Jarno a écrit :
> >On 2015-06-11 22:30, Hervé Poussineau wrote:
> >>This workarounds a bug in memory management.
> >>
> >>To reproduce the problem, try to start the Windows NT 4.0/MIPS installer.
> >>Afte
On 2015-06-16 18:44, Alexander Graf wrote:
> On 06/13/15 00:46, Aurelien Jarno wrote:
> >This patch adds support for PER Breaking-Event-Address register. Like
> >real hardware, it save the current PSW address when the PSW address is
> >changed by an instruction. We have to take care of optimization
Ping? Any feedback? I want to get this into 2.4.
On Mon, Jun 08, 2015 at 04:07:38PM -0300, Eduardo Habkost wrote:
> The problem:
>
> The existing libvirt APIs assume that if a given CPU model is runnable in a
> host kernel+hardware combination, it will be always runnable on that host even
> if t
> On 16 Jun 2015, at 19:10, Peter Crosthwaite
> wrote:
>
>> +bool use_stderr;
>
> Why do you want to switch between stderr and stdout?
I wasn't sure which one is more appropriate, I first used stdout then tried
stderr.
> I think stderr is more correct,
yes, that was my conclusion too.
On 06/13/15 00:46, Aurelien Jarno wrote:
This patch adds support for PER Breaking-Event-Address register. Like
real hardware, it save the current PSW address when the PSW address is
changed by an instruction. We have to take care of optimizations QEMU
does, a branch to the next instruction is sti
On 16/06/15 17:37, Eric Blake wrote:
On 06/16/2015 06:57 AM, Denis V. Lunev wrote:
PING, 1 week till soft freeze.
Michael, can you pls consider these patches? We have
really small amount of time left.
Regards,
Den
_PING_
I think Michael is on vacation until the end of this week.
Stefa
On Tue, 16 Jun 2015 18:26:47 +0200
Greg Kurz wrote:
> The tce_list variable is not a TCE but the address to a TCE: we shouldn't
> clear permission bits as we do now. And this is dead code anyway since we
> check tce_list is 4K aligned a few lines above.
>
> This patch doesn't fix any bug, it is o
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