Hello!
> Hm, weren't there some patches for irqfd on arm?
Yes, there were. However, they had a design problem by breaking backwards
compatibility
with unmodified virtio. Their idea was to set up one more shared memory area
between
virtio and vhost-net and use it to pass ISR value, which helps
No, he is on vacation this week. Sorry for the delay!
Of you are doing cleanups in virtio, perhaps you can look into using alias
properties for virtio-balloon's QOM properties (for example the statistics).
The code is currently using object_property_add and manually-written
getters/setters.
Th
Applied to -trivial, thank you!
/mjt
Public bug reported:
Hi,
I'm running a freshly installed Windows 7 domU on an up-to-date Debian
jessie machine running Xen 4.4.1-9. When the Windows machine is idle,
I'm seeing upwards of 10% CPU usage from the qemu-system-i386 instance.
Other Linux and FreeBSD machines register negligable CPU u
Paolo Bonzini writes:
> Right now, NBD includes potentially platform-specific error values in
> the wire protocol.
Design flaw.
> Luckily, most common error values are more or less universal: in
> particular, of all errno values <= 34 (up to ERANGE), they are all
> the same on supported platfor
Eric Blake writes:
> On 05/06/2015 10:18 AM, John Snow wrote:
>
>>> To find out, add just buffering. Something like this in your patch
>>> instead of byte2hex():
>>>
>>> for (i = 0; i < len; i++) {
>>> -qtest_sendf(chr, "%02x", data[i]);
>>> +snprintf(&enc[i * 2]
On Fr, 2015-05-08 at 00:28 +0200, Alexander Graf wrote:
>
> On 05.05.15 11:43, Gerd Hoffmann wrote:
> > Signed-off-by: Gerd Hoffmann
> > Reviewed-by: Max Reitz
> > ---
>
> [...]
>
> > +void surface_gl_create_texture(ConsoleGLState *gls,
> > + DisplaySurface *surfa
John Snow writes:
> On 05/07/2015 08:22 AM, Peter Maydell wrote:
>> On 10 March 2015 at 17:45, Peter Maydell wrote:
>>> On 10 March 2015 at 17:43, John Snow wrote:
Wasn't aware we were actually going through with that; it had looked
like we were going to refrain from fiddling with it
On 7 May 2015 at 22:05, Chen Gang wrote:
>
> Since no response, I assume that it is not suitable to send patches
> before finish printing hello world successfully (when sending patches,
> we should be sure of the patches are valuable enough).
Er, I said you should send patches earlier rather than
On Thu, 05/07 14:20, Stefan Hajnoczi wrote:
> On Wed, May 06, 2015 at 12:52:02PM +0800, Fam Zheng wrote:
> > v2: Fix typo and add Eric's rev-by in patch 3.
> > Add patch 1 to discard target in mirror job. (Paolo)
> > Add patch 6 to improve iotests.wait_ready. (John)
> >
> > This fixes the
On 2015/5/7 23:51, Peter Maydell wrote:
> On 7 May 2015 at 10:29, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > Add aml_interrupt() for describing device interrupt in resource template.
>> > These can be used to generating DSDT table for ACPI on ARM.
>> > +/* Interrupt Number */
>> >
On 2015/5/7 23:44, Peter Maydell wrote:
> On 7 May 2015 at 10:29, Shannon Zhao wrote:
>> From: Shannon Zhao
>>
>> Introduce a preliminary framework in virt-acpi-build.c with the main
>> ACPI build functions. It exposes the generated ACPI contents to
>> guest over fw_cfg.
>>
>> The required ACPI v
On 2015/5/7 18:50, Alex Bennée wrote:
> Shannon Zhao writes:
>
>> > From: Shannon Zhao
>> >
>> > Introduce a preliminary framework in virt-acpi-build.c with the main
>> > ACPI build functions. It exposes the generated ACPI contents to
>> > guest over fw_cfg.
>> >
>> > The required ACPI v5.1 tabl
On 2015/4/29 23:24, Shannon Zhao wrote:
> The private qdev properties of virtio devices are only used by
> themselves. As Peter suggested and like what virtio-blk has done, we
> should move the private qdev properties into devices and don't expose
> them to avoid wrongly use.
>
> This patchset is
On 05.05.15 17:49, Richard Henderson wrote:
> On 05/05/2015 12:18 AM, Paolo Bonzini wrote:
>> Patches 1 and 2 enable support from more than 8 MMU modes in TCG (patch
>> 1 is in the targets, patch 2 is in cpu-defs.h). The TLB size is reduced
>> proportionally on targets where that is necessary.
>
We're currently missing the laa and laag instructions in our emulation.
In fact, we're missing the complete "interlocked-access facility 1" which
is part of zEC12. However, I really only needed the laa instruction for now.
Signed-off-by: Alexander Graf
---
This really should implement all the o
I find it really hard to grasp what each field in the opcode list means.
Slowly walking through its semantics myself, I figured I'd write a small
summary at the top of the file to make life easier for me and whoever
looks at the file next.
Signed-off-by: Alexander Graf
---
target-s390x/insn-data
The function bdrv_clear_dirty_bitmap() is updated to use
faster hbitmap_reset_all() call.
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
Acked-by: Paolo Bonzini
---
block.c| 2 +-
include/qemu/hbitmap.h | 8
tests/test-hbitmap.c |
Add bootloader support using standard ARM bootloader.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Add loader_start field
Make commit message body standalone.
hw/arm/xlnx-ep108.c | 9 +
1 file changed, 9 insertions(+)
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use memory_region_allocate_system_memory
Change too-small warning to be qemu_log
changed since v1:
Add ram size cla
There are 2x Cadence UARTs in Zynq MP. Add them.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
Changed since v4:
Remove ERR_PROP_CHECK_RETURN usage.
Changed since v1:
Fixed "UARTSs" typo
hw/arm/xlnx-zynqmp.c
Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
Add a machine model for the Xilinx ZynqMP SoC EP108 board.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
Chaned since v1:
Change board name to ep108
hw/arm/Makefile.objs | 2 +-
hw/ar
Clean up some variable names in preparation for migrating the state struct
and type cast macro to a public header. The acronym "UART" on it's own is
not specific enough to be used in a more global namespace so preface with
"cadence". Fix the capitalisation of "uart" in the state type while touching
With quad Cortex-A53 CPUs.
Use SMC PSCI, with the standard policy of secondaries starting in
power-off.
Tested-by: Alistair Francis
Reviewed-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
---
changed since v4 (PMM review):
Squashed in PSCI stuffs.
Add (c)
Create a new header for Cadence GEM to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
Cleanup some variable names in preparation for migrating the state
struct and type cast macro to a public header. The acronym "GEM" on
its own is not specific enough to be used in a more global namespace
so preface with "cadence". Fix the capitalisation of "gem" in the
state type while touching the
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
under-decoded through a 64k address region so implement aliases
accordingly.
Signed-off-by: Peter Crosthwaite
---
changed since v7:
Made GIC region size definition board specific
changed since v6:
Added aliases.
changed since v5
Rename some A57 CP register variables in preparation for support for
Cortex A53. Use "a57_a53" to describe the shareable features. Some of
the CP15 registers (such as ACTLR) are specific to implementation, but
we currently just RAZ them so continue with that as the policy for both
A57 and A53 proce
There are 4x Cadence GEMs in ZynqMP. Add them.
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Remove use of ERR_PROP_CHECK_RETURN
hw/arm/xlnx-zynqmp.c | 35 +++
include/hw/arm/xlnx-zynqmp.h
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Tested-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use macro for GIC_INTERNAL
hw/arm/xlnx-zynqmp.c | 17 +
1 file changed, 17 insertions(
Add the ARM Cortex-A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.
Ac
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
board.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs added. The
pre-existing models for GEM and UART are not SoC friendly (no visible
On 05/08/2015 02:32 AM, John Snow wrote:
>
>
> On 05/06/2015 10:20 PM, Wen Congyang wrote:
>> On 05/02/2015 12:47 AM, John Snow wrote:
>>>
>>>
>>> On 04/03/2015 07:05 AM, Paolo Bonzini wrote:
On 03/04/2015 12:01, Wen Congyang wrote:
> Signed-off-by: Wen Congyang
> Signed-o
On 08.05.15 02:11, David Gibson wrote:
> At Alex Graf's request I'm now acting as sub-maintainer for the sPAPR
> (-machine pseries) code. This updates MAINTAINERS accordingly.
>
> While we're at it, change the label to mention pseries since that's the
> actual name of the machine type, even if
On Thu, May 7, 2015 at 7:02 AM, Peter Maydell wrote:
> On 6 May 2015 at 23:50, Peter Crosthwaite
> wrote:
>> Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
>> under-decoded through a 64k address region so implement aliases
>> accordingly.
>
>> +assert(ARRAY_SIZE(xlnx_zy
On Thu, May 7, 2015 at 6:59 AM, Peter Maydell wrote:
> On 6 May 2015 at 23:50, Peter Crosthwaite
> wrote:
>> GIC generally uses a 4k memory region for the various subregions, such
>> as GICC, GICD, GICV and GICH. Macroify this number in the publicly
>> visible header.
>
>> +#define ARM_GIC_REGIO
On Fri, May 08, 2015 at 12:39:20AM +0200, Alexander Graf wrote:
>
>
> On 07.05.15 07:33, David Gibson wrote:
> > From: Michael Roth
> >
> > This device emulates a firmware abstraction used by pSeries guests to
> > manage hotplug/dynamic-reconfiguration of host-bridges, PCI devices,
> > memory,
At Alex Graf's request I'm now acting as sub-maintainer for the sPAPR
(-machine pseries) code. This updates MAINTAINERS accordingly.
While we're at it, change the label to mention pseries since that's the
actual name of the machine type, even if most of the C files use the sPAPR
name.
Signed-off
On 07.05.15 07:33, David Gibson wrote:
> From: Michael Roth
>
> This device emulates a firmware abstraction used by pSeries guests to
> manage hotplug/dynamic-reconfiguration of host-bridges, PCI devices,
> memory, and CPUs. It is conceptually similar to an SHPC device,
> complete with LED indi
On 05.05.15 11:43, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> Reviewed-by: Max Reitz
> ---
[...]
> +void surface_gl_create_texture(ConsoleGLState *gls,
> + DisplaySurface *surface)
> +{
> +assert(gls);
> +assert(surface_stride(surface) % surfac
On 05.05.15 09:18, Paolo Bonzini wrote:
> Patches 1 and 2 enable support from more than 8 MMU modes in TCG (patch
> 1 is in the targets, patch 2 is in cpu-defs.h). The TLB size is reduced
> proportionally on targets where that is necessary.
>
> Patch 3 uses the new support in the PPC target.
>
On 07.05.15 07:33, David Gibson wrote:
> Hi Alex (et al),
>
> Here's my current batch of -machine pseries related patches which I
> think are ready to merge. Sorry this is a resend pretty close after
> the last batch I sent out - I wanted to make sure I sent out the queue
> because I'm going to
Since no response, I assume that it is not suitable to send patches
before finish printing hello world successfully (when sending patches,
we should be sure of the patches are valuable enough).
And sorry, I delayed too much for developing tilegx qemu, next I shall
try to print hello world success
On 05/06/2015 10:18 AM, John Snow wrote:
>> To find out, add just buffering. Something like this in your patch
>> instead of byte2hex():
>>
>> for (i = 0; i < len; i++) {
>> -qtest_sendf(chr, "%02x", data[i]);
>> +snprintf(&enc[i * 2], 2, "%02x", data[i]);
>>
On 05/07/2015 04:21 PM, Eric Blake wrote:
> On 05/07/2015 11:51 AM, John Snow wrote:
>> Instead of converting each byte one-at-a-time and then sending
>> each byte over the wire, use sprintf() to pre-compute all of the
>> hex nibs into a single buffer, then send the entire buffer all at
>> once.
On 05/07/2015 11:51 AM, John Snow wrote:
> Instead of converting each byte one-at-a-time and then sending each byte
> over the wire, use sprintf() to pre-compute all of the hex nibs into a
> single buffer, then send the entire buffer all at once.
>
> This gives a moderate speed boost to memread()
Latest version from git, using FreeBSD10.0:
qemu-system-ppc64 -cdrom FreeBSD-10.0-RELEASE-powerpc-disc1.iso -hda
freebsd10.0-ppc -m 256 -boot d -k en-us:
SLOF **
QEMU Starting
Build Date = Mar 13 2015 22:37:28
FW Version = git
I used the -nographic option as well, but lost it in the copy and paste.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/623852
Title:
PPC emulation loops on booting a FreeBSD kernel
Status in QEMU:
On 02/27/2015 12:24 PM, Vladimir Sementsov-Ogievskiy wrote:
> Signed-off-by: John Snow
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> tests/qemu-iotests/iotests.py | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests
On 7 May 2015 at 17:46, Juan Quintela wrote:
> Hi again (2)
>
> And now on v3
>
> - I fix not using of atomic with 64 bit values.
> Notice that the code was wrong in any architecture, someplaces used atomics,
> someothers used something different.
>
> Praying $deity_in_32bits of the day
>
> Pl
On 05/06/2015 10:20 PM, Wen Congyang wrote:
> On 05/02/2015 12:47 AM, John Snow wrote:
>>
>>
>> On 04/03/2015 07:05 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 03/04/2015 12:01, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
On (Thu) 07 May 2015 [13:45:26], Peter Maydell wrote:
> On 7 May 2015 at 12:50, Juan Quintela wrote:
> >
> >
> > Hi again
> >
> > For v2
> >
> > - fix 32bit compilation (as said, compiling for 64bit linux, 64bit
> > windows and 32bit windows was not enough)
> >
> > - Now, we have versions 2.4 ev
Im replying this cause i made a mistake asking to someones private mail,
sorry:
> OK, another question. How come if Cortex-M3 doesnt support DSP
instructions
> qemu understand them? I tried some of them with an stellaris lm3s6965evb.
I
> do understand that they were implemented for the A profile co
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
> +/* An output operand to return the StoreConditional result */
> +static void gen_stcond_i32(TCGOpcode opc, TCGv_i32 is_dirty, TCGv_i32 val,
> + TCGv addr, TCGMemOp memop, TCGArg idx)
> +{
> +tcg_gen_op5ii_i32(opc, is_dirty, v
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
> +#define DATA_SIZE (1 << SHIFT)
> +
> +#if DATA_SIZE == 8
> +#define SUFFIX q
> +#define LSUFFIX q
> +#define SDATA_TYPE int64_t
> +#define DATA_TYPE uint64_t
Duplicating all of the stuff from softmmu_template.h is Just Wrong.
> +/* For the benefit o
On 05/07/2015 02:13 AM, Markus Armbruster wrote:
> John Snow writes:
>
>> On 05/06/2015 11:19 AM, Markus Armbruster wrote:
>>> John Snow writes:
>>>
On 05/06/2015 02:25 AM, Markus Armbruster wrote:
> John Snow writes:
>
>> Instead of letting printf and friends do this for us
Instead of converting each byte one-at-a-time and then sending each byte
over the wire, use sprintf() to pre-compute all of the hex nibs into a
single buffer, then send the entire buffer all at once.
This gives a moderate speed boost to memread() and memwrite() functions.
Signed-off-by: John Snow
This patch requires (as context only) patches 1,2
(but excluding patch 4) from:
Message-id: 1430864578-22072-1-git-send-email-js...@redhat.com
[PATCH v3 0/5] qtest: base64 r/w and faster memset
Or, alternatively, use the github mirrors below.
==
For convenience, this branch is available at:
https
On Mon, 4 May 2015, Quan Xu wrote:
> This patch adds infrastructure for xen front drivers living in qemu,
> so drivers don't need to implement common stuff on their own. It's
> mostly xenbus management stuff: some functions to access XenStore,
> setting up XenStore watches, callbacks on device dis
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
> Add a new flag for the TLB entries to force all the accesses made to a
> page to follow the slow-path.
>
> Mark the accessed page as dirty to invalidate any pending operation of
> LL/SC.
>
> Suggested-by: Jani Kokkonen
> Suggested-by: Claudio Fontana
On 05/07/2015 10:54 AM, Stefan Hajnoczi wrote:
> On Wed, Apr 22, 2015 at 08:04:44PM -0400, John Snow wrote:
>> +static void block_dirty_bitmap_clear_prepare(BlkTransactionState
>> *common, + Error
>> **errp) +{ +BlockDirtyBitmapState *state =
>> DO_
On 07/05/2015 18:46, Juan Quintela wrote:
> static CompressParam *comp_param;
> static QemuThread *compress_threads;
> +/* comp_done_cond is used to wake up the migration thread when
> + * one of the compression threads has finished the compression.
> + * comp_done_lock is used to co-work with
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
> The purpose of this new bitmap is to flag the memory pages that are in
> the middle of LL/SC operations (after a LL, before a SC).
> For all these pages, the corresponding TLB entries will be generated
> in such a way to force the slow-path.
>
> The acc
On 05/07/2015 08:58 AM, Alberto Garcia wrote:
> Label the "size" and "offset" fields in BLOCK_IMAGE_CORRUPTED as
> optional, and clarify that the latter refers to the host's offset into
> the image.
>
> Signed-off-by: Alberto Garcia
> ---
> docs/qmp/qmp-events.txt | 5 +++--
> qapi/block-core.js
On 07/05/2015 19:01, Eric Blake wrote:
>> >
>> > +/* NBD errors should be universally equal to the corresponding
>> > + * errno values, check it here.
>> > + */
>> > +QEMU_BUILD_BUG_ON(EPERM != 1);
> And this is (probably not the first place) where qemu compilation would
> fail
On 07/05/2015 18:56, Jérémy Fanguède wrote:
> USB devices fail with a timeout error, as if the communication between
> the kernel and the devices fail at a certain point:
> usb 1-1: device not accepting address 5, error -110
> usb usb1-port1: unable to enumerate USB device
>
> e1000 fails when t
On 05/07/2015 09:26 AM, Paolo Bonzini wrote:
> Right now, NBD includes potentially platform-specific error values in
> the wire protocol.
>
> Luckily, most common error values are more or less universal: in
> particular, of all errno values <= 34 (up to ERANGE), they are all
> the same on supporte
On Thu, May 7, 2015 at 5:34 PM, Christoffer Dall
wrote:
> On Thu, May 7, 2015 at 4:50 PM, Jérémy Fanguède
> wrote:
>> On Thu, May 7, 2015 at 1:20 PM, Christoffer Dall
>> wrote:
>>> On Thu, May 07, 2015 at 12:50:50PM +0200, Jérémy Fanguède wrote:
On Wed, May 6, 2015 at 4:12 PM, Christoffer D
From: Liang Li
Add the hmp interface to tune and query the parameters used in
live migration.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Signed-off-by: Juan Quintela
---
hmp-commands.hx | 17 +++
hmp.c | 65
From: Liang Li
If live migration is very fast and can be completed in 1 second,
the dirty_sync_count of MigrationState will not be updated.
Then you will see "dirty sync count: 0" in qemu monitor even if
the actual dirty sync count is not 0.
Signed-off-by: Liang Li
Reviewed-by: Juan Quintela
R
From: Michael Chapman
This bug manifested itself as a VM that could not be resumed by libvirt
following a migration:
# virsh resume example
error: Failed to resume domain example
error: internal error: cannot parse json {"return":
{"xbzrle-cache":
{..., "cache-miss-rate": -nan, .
From: Liang Li
Put the three parameters related to multiple thread (de)compression
into an int array, and use an enum type to index the parameter.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Signed-off-by: Juan Quintela
---
include/migration/migration.h | 4 +---
migration/migration.c
From: Liang Li
Implement the core logic of multiple thread decompression,
the decompression can work now.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Signed-off-by: Juan Quintela
---
arch_init.c | 50 --
1 file changed, 48 insertions(+),
From: Liang Li
The multiple compression threads can be turned on/off through
qmp and hmp interface before doing live migration.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Reviewed-by: Dr.David Alan Gilbert
Reviewed-by: Eric Blake
Signed-off-by: Juan Quintela
---
migration/migration.
From: Liang Li
Define the data structure and variables used to do multiple thread
decompression, and add the code to initialize and free them.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Reviewed-by: Dr.David Alan Gilbert
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
ar
From: Liang Li
Implement the core logic of the multiple thread compression. At this
point, multiple thread compression can't co-work with xbzrle yet.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Signed-off-by: Juan Quintela
---
arch_init.c | 185 +
From: Liang Li
Add the qmp commands to tune and query the parameters used in live
migration.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Signed-off-by: Juan Quintela
---
migration/migration.c | 56 ++
qapi-schema.json | 45 ++
From: Liang Li
Define the data structure and variables used to do multiple thread
compression, and add the code to initialize and free them.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Reviewed-by: Dr.David Alan Gilbert
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
arch
From: Liang Li
Now, multiple thread compression can co-work with xbzrle. when
xbzrle is on, multiple thread compression will only work at the
first round of RAM data sync.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Reviewed-by: Dr.David Alan Gilbert
Signed-off-by: Juan Quintela
---
a
From: Liang Li
qemu_put_compression_data() compress the data and put it to QEMUFile.
qemu_put_qemu_file() put the data in the buffer of source QEMUFile to
destination QEMUFile.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
incl
From: Liang Li
Add the code to create and destroy the multiple threads those will be
used to do data decompression. Left some functions empty just to keep
clearness, and the code will be added later.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Reviewed-by: Dr.David Alan Gilbert
Reviewed
From: Liang Li
Split the function save_zero_page from ram_save_page so that we can
reuse it later.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
arch_init.c | 61 +++--
1
From: Liang Li
Add the code to create and destroy the multiple threads those will
be used to do data compression. Left some functions empty to keep
clearness, and the code will be added later.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Reviewed-by: Dr.David Alan Gilbert
Reviewed-by: Ju
From: Liang Li
Give some details about the multiple thread (de)compression and
how to use it in live migration.
Signed-off-by: Liang Li
Signed-off-by: Yang Zhang
Reviewed-by: Dr.David Alan Gilbert
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
docs/multi-thread-compression.txt
7e9b2b17:
Merge remote-tracking branch 'remotes/rth/tags/tcg-next-20150505' into
staging (2015-05-06 11:16:35 +0100)
are available in the git repository at:
git://github.com/juanquintela/qemu.git tags/migration/20150507-1
for you to fetch changes up to 362ba4e3ee801e8f5e28d72d
On 7 May 2015 at 10:29, Shannon Zhao wrote:
> From: Shannon Zhao
>
> This patch series generate seven ACPI tables for machine virt on ARM.
> The set of generated tables are:
> - RSDP
> - RSDT
> - MADT
> - GTDT
> - FADT
> - DSDT
> - MCFG (For PCIe host bridge)
>
> These tables are created dynamica
On 07/05/2015 14:02, Peter Maydell wrote:
>> +static int add_semihosting_arg(const char *name, const char *val, void
>> *opaque)
>> +{
>> +SemihostingConfig *s = opaque;
>> +if (strcmp(name, "arg") == 0) {
>> +s->argc++;
>> +s->argv = g_realloc(s->argv, s->argc * sizeof(voi
On 7 May 2015 at 10:29, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Expose the needed device information to the table generation
> insfrastructure and register a machine_init_done notify to
"infrastructure".
> call virt_acpi_build().
>
> Add CONFIG_ACPI to arm-softmmu.mak.
>
> Signed-off-by: S
On 7 May 2015 at 10:29, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add aml_interrupt() for describing device interrupt in resource template.
> These can be used to generating DSDT table for ACPI on ARM.
> +/* Interrupt Number */
> +build_append_byte(var->buf, extract32(irq, 0, 8)); /*
This is the behavior in the operating system, for example Linux's
blkdev_write_iter has the following:
if (bdev_read_only(I_BDEV(bd_inode)))
return -EPERM;
This does not apply to opening a device for read/write, when the
device only supports read-only operation. In this c
On 7 May 2015 at 10:29, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Introduce a preliminary framework in virt-acpi-build.c with the main
> ACPI build functions. It exposes the generated ACPI contents to
> guest over fw_cfg.
>
> The required ACPI v5.1 tables for ARM are:
> - RSDP: Initial table t
On Thu, May 7, 2015 at 4:50 PM, Jérémy Fanguède
wrote:
> On Thu, May 7, 2015 at 1:20 PM, Christoffer Dall
> wrote:
>> On Thu, May 07, 2015 at 12:50:50PM +0200, Jérémy Fanguède wrote:
>>> On Wed, May 6, 2015 at 4:12 PM, Christoffer Dall
>>> wrote:
>>> > Hi Jérémy,
>>> >
>>> > On Tue, May 05, 2015
On Thu, May 07, 2015 at 03:05:45PM +0530, Bharata B Rao wrote:
> On Wed, Mar 18, 2015 at 11:50:04AM +0530, Bharata B Rao wrote:
> > On Tue, Mar 17, 2015 at 11:56:04AM +0100, Andreas Färber wrote:
> > > Am 17.03.2015 um 09:39 schrieb Bharata B Rao:
> > > > On Tue, Mar 17, 2015 at 07:56:41AM +0100, A
Right now, NBD includes potentially platform-specific error values in
the wire protocol.
Luckily, most common error values are more or less universal: in
particular, of all errno values <= 34 (up to ERANGE), they are all
the same on supported platforms except for 11 (which is EAGAIN on
Windows and
This is consistent with the handling of writes.
Signed-off-by: Paolo Bonzini
---
nbd.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/nbd.c b/nbd.c
index cb1b9bb..eea8c51 100644
--- a/nbd.c
+++ b/nbd.c
@@ -1325,6 +1325,12 @@ static void nbd_trip(void *opaque)
break;
case
In reference to b0ad5a45...078a458e, metadata writes to
qcow2/cow/qcow/vpc/vmdk are all synced prior to succeeding writes.
Only when write is successful that bdrv_flush is called.
Signed-off-by: Zhe Qiu
---
block/vdi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/block/vdi.c b/block/
On 05/07/2015 08:22 AM, Peter Maydell wrote:
> On 10 March 2015 at 17:45, Peter Maydell wrote:
>> On 10 March 2015 at 17:43, John Snow wrote:
>>> Wasn't aware we were actually going through with that; it had looked
>>> like we were going to refrain from fiddling with it because we found
>>> a w
On May 7, 2015, at 2:47 AM, Michael Tokarev wrote:
> 07.05.2015 09:12, Michael Tokarev wrote:
>> 07.05.2015 04:11, G 3 wrote:
>>> Did you boot Windows XP to the desktop? I have tested Windows 95, Windows
>>> 2000, and Windows XP. All of them fail to boot to the desktop.
>>
>> Yes, booted to des
Label the "size" and "offset" fields in BLOCK_IMAGE_CORRUPTED as
optional, and clarify that the latter refers to the host's offset into
the image.
Signed-off-by: Alberto Garcia
---
docs/qmp/qmp-events.txt | 5 +++--
qapi/block-core.json| 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
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