SeokYeon Hwang writes:
[...]
> But if 2.2 comes with all "realized" devices, if there is no "init" devices,
> then this patch isn't needed.
No PCI devices will be converted to realize in 2.2. We'll start the
conversion early in the 2.3 development cycle. Whether we can finish it
in the same cy
Amos Kong writes:
> On Fri, Nov 07, 2014 at 11:24:55AM +0900, SeokYeon Hwang wrote:
>> Added 'assert(os_errno > 0)' in 'error_set_errno()'.
>> Fixed errno since it passes wrong value to 'error_set_errno()'.
>>
>> Signed-off-by: SeokYeon Hwang
>> ---
>> hw/pci/pcie.c | 2 +-
>> util/error.c |
On Thu, Nov 06, 2014 at 01:43:13PM -0600, Tom Musta wrote:
> When computing the upper address of a program segment, do not subtract the
> offset from the virtual address; instead compute the sum of the virtual
> address
> and the memory size.
Thanks, I'll test this and try to get it applied ASAP.
On Fri, Nov 07, 2014 at 11:24:55AM +0900, SeokYeon Hwang wrote:
> Added 'assert(os_errno > 0)' in 'error_set_errno()'.
> Fixed errno since it passes wrong value to 'error_set_errno()'.
>
> Signed-off-by: SeokYeon Hwang
> ---
> hw/pci/pcie.c | 2 +-
> util/error.c | 1 +
> 2 files changed, 2 ins
On (Thu) 06 Nov 2014 [12:49:17], Peter Maydell wrote:
> On 6 November 2014 11:20, Amit Shah wrote:
> > The following changes since commit 6e76d125f244e10676b917208f2a074729820246:
> >
> > Update version for v2.2.0-rc0 release (2014-11-05 15:21:04 +)
> >
> > are available in the git repositor
The following changes since commit 6e76d125f244e10676b917208f2a074729820246:
Update version for v2.2.0-rc0 release (2014-11-05 15:21:04 +)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/qemu/amit/virtio-serial.git
tags/vser-2.2.0-queue-2
for you to fetch chan
The 'QemuConsole' is the input source for handler, we share some
input handlers to process the input events from different QemuConsole.
Normally we only have one set of keyboard, mouse, usbtablet, etc.
The devices have different mask, it's fine to just checking mask to
insure that the handler has
Signed-off-by: Amos Kong
---
qapi-schema.json | 5 +
1 file changed, 5 insertions(+)
diff --git a/qapi-schema.json b/qapi-schema.json
index 24379ab..a1573d8 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -3231,6 +3231,11 @@
#
# Input event union.
#
+# @key: Input event of Keyboar
> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Thursday, November 06, 2014 6:24 PM
> To: SeokYeon Hwang
> Cc: 'Paolo Bonzini'; 'Markus Armbruster'; qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH] pci: fixed mismatch of error-handling
> between pci
On Thu, Nov 06, 2014 at 11:01:11PM +0800, Amos Kong wrote:
> On Thu, Nov 06, 2014 at 02:37:54PM +0800, Amos Kong wrote:
> > On Wed, Nov 05, 2014 at 09:47:47AM +0100, Gerd Hoffmann wrote:
> > > On Mi, 2014-11-05 at 00:49 +0800, Amos Kong wrote:
> > > > qemu_input_find_handler() prefers a handler ass
On 2014/11/6 19:09, Michael S. Tsirkin wrote:
> On Thu, Nov 06, 2014 at 05:54:54PM +0800, Shannon Zhao wrote:
>> On 2014/11/6 17:34, Michael S. Tsirkin wrote:
>>> On Tue, Nov 04, 2014 at 05:35:12PM +0800, Shannon Zhao wrote:
As the current virtio-mmio only support single irq,
so some adva
>OK, some high level questions:
>
> 1) How does the performance compare to running a separate compressor process
> in the stream rather than embedding it in the qemu?
>
I have not do the test, so I don't know the performance. Maybe I can do it
later.
> 2) Since you're looking at different comp
> -Original Message-
> From: Markus Armbruster [mailto:arm...@redhat.com]
> Sent: Thursday, November 06, 2014 6:25 PM
> To: SeokYeon Hwang
> Cc: 'Paolo Bonzini'; 'Max Reitz'; qemu-devel@nongnu.org; Peter Maydell;
> paolo.bonz...@gmail.com
> Subject: Re: [Qemu-devel] [PATCH] error: fixed err
Added 'assert(os_errno > 0)' in 'error_set_errno()'.
Fixed errno since it passes wrong value to 'error_set_errno()'.
Signed-off-by: SeokYeon Hwang
---
hw/pci/pcie.c | 2 +-
util/error.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 5845
Hi, all
I used base image A to clone so many vm,
after running for months, each vm has its own private applications and
data,
which maybe different from each other.
Now, I want to install some applications for all of the clones,
what should I do?
>
>How wou
Needless to call bdrv_flush() in qcow2_cache_flush()
if no cache entry is dirty.
Signed-off-by: Zhang Haoyu
---
block/qcow2-cache.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/block/qcow2-cache.c b/block/qcow2-cache.c
index 904f6b1..09ee155 1006
On 2014/11/7 1:26, Paolo Bonzini wrote:
> On 06/11/2014 17:49, Stefan Hajnoczi wrote:
-Boot Devices Supporting dynamically modify boot order of
guest, and assuring taking effect after the guest rebooting.
>> "Please add this" isn't enough. What is the justification to add
>> it during h
launchpad mangled that pretty good, maybe this is better -
http://fpaste.org/148539/
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1384892
Title:
RTL8168 NIC VFIO not working anymore since QEMU 2.1
Does this improve anything? Reviewing the quirk seems to show there's a
bug in how we're writing to the MSI-X table. Not sure how it worked
before. Tested this with a Win8.1 VM and assigned RTL8111/8168/8411.
Thanks.
--- a/hw/misc/vfio.c
+++ b/hw/misc/vfio.c
@@ -1834,8 +1834,8 @@ static void vf
Answers to some of your questions:
Can you only get this on one particular host (i.e. hardware type)?
- No as I can repro in KVM
-Is there anything in syslog?
- Nothing relevant
Which packages (dpkg -l | grep qemu)
ii qemu-utils 2.0.0+dfsg-2ubuntu1.6 amd64
On 06/11/2014 17:09, Andrew Jones wrote:
> +if (sockets * cores * threads != max_cpus) {
> +fprintf(stderr, "cpu topology: "
> +"sockets (%u) * cores (%u) * threads (%u) != max_cpus
> (%u)\n",
> +sockets, cores, threads, max_cpus);
> +
Le 06/11/2014 19:23, Artyom Tarasenko a écrit :
On Thu, Nov 6, 2014 at 6:36 PM, Damien Hilloulin
wrote:
Le 06/11/2014 16:27, Artyom Tarasenko a écrit :
Hello Damien,
On Thu, Nov 6, 2014 at 8:38 AM, Damien Hilloulin
wrote:
Hello everyone,
I'm a newcomer in QEMU and my goal would be to port
Correct the way PC is updated when single-stepping instructions, by
keeping the old PC only for the BS_EXCP (exception condition) state.
Some MTC0 (and possibly other) instructions switch to the BS_STOP state
to terminate the current translation block, so that the state transition
of the simula
On Fri, Oct 3, 2014 at 9:07 PM, Andrea Arcangeli wrote:
> We run out of 32bits in vm_flags, noop change for 64bit archs.
What? Again?
As I see there are some free bits: 0x200, 0x1000, 0x8
I prefer to reserve 0x0200 for VM_ARCH_2
>
> Signed-off-by: Andrea Arcangeli
> ---
> fs/proc/task
When computing the upper address of a program segment, do not subtract the
offset from the virtual address; instead compute the sum of the virtual address
and the memory size.
Signed-off-by: Tom Musta
---
Please include this patch in QEMU 2.2.
Commit a93934fecd4dffc9d4b452b670c9506be5dea30d i
On Thu, Nov 06, 2014 at 05:09:35PM +0100, Andrew Jones wrote:
> smp_parse has a couple problems. First, it should use max_cpus,
> not smp_cpus when calculating missing topology information.
> Conversely, if maxcpus is not input, then the topology should
> dictate max_cpus, as the topology may suppo
On 11/5/2014 2:04 PM, Michael Roth wrote:
> Hello,
>
> On behalf of the QEMU Team, I'd like to announce the availability of the
> first release candidate for the QEMU 2.2 release. This release is meant
> for testing purposes and should not be used in a production environment.
>
> http://wiki.q
Am 06.11.2014 18:24, schrieb Paolo Bonzini:
>
> On 06/11/2014 16:58, Christian Borntraeger wrote:
>> Now here comes my proposal:
>> Markus statement brought up an idea of special casing DASDs support. We can
>> call an ioctl BIODASDINFO on the block device that will only succeed if the
>> host
>>
On Thu, Nov 6, 2014 at 6:36 PM, Damien Hilloulin
wrote:
> Le 06/11/2014 16:27, Artyom Tarasenko a écrit :
>>
>> Hello Damien,
>>
>> On Thu, Nov 6, 2014 at 8:38 AM, Damien Hilloulin
>> wrote:
>>>
>>> Hello everyone,
>>>
>>> I'm a newcomer in QEMU and my goal would be to port an existing system
>>>
Le 06/11/2014 16:27, Artyom Tarasenko a écrit :
Hello Damien,
On Thu, Nov 6, 2014 at 8:38 AM, Damien Hilloulin
wrote:
Hello everyone,
I'm a newcomer in QEMU and my goal would be to port an existing system
simulator using another emulator to QEMU.
Some work has already been done, and Sparc has
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/11/2014 17:49, Stefan Hajnoczi wrote:
>>> -Boot Devices Supporting dynamically modify boot order of
>>> guest, and assuring taking effect after the guest rebooting.
> "Please add this" isn't enough. What is the justification to add
> it during
On 06/11/2014 16:58, Christian Borntraeger wrote:
> Now here comes my proposal:
> Markus statement brought up an idea of special casing DASDs support. We can
> call an ioctl BIODASDINFO on the block device that will only succeed if the
> host
> disk is really a dasd. We could enable the auto dete
On 11/06/2014 06:18 PM, Alexander Graf wrote:
>
>
> On 06.11.14 17:23, Fabien Chouteau wrote:
>> In the previous patch, the registers were added to init_proc_G2LE
>> instead of init_proc_e300.
>>
>> Signed-off-by: Fabien Chouteau
>
> Thanks, applied to ppc-next (for 2.2).
>
Thank you,
On 06.11.14 17:23, Fabien Chouteau wrote:
> In the previous patch, the registers were added to init_proc_G2LE
> instead of init_proc_e300.
>
> Signed-off-by: Fabien Chouteau
Thanks, applied to ppc-next (for 2.2).
Alex
> -Original Message-
> From: Paolo Bonzini [mailto:paolo.bonz...@gmail.com] On Behalf Of Paolo
> Bonzini
> Sent: Monday, November 03, 2014 8:22 PM
> To: Xu, Quan; qemu-devel@nongnu.org
> Cc: aligu...@amazon.com; xen-de...@lists.xen.org
> Subject: Re: [PATCH 4/4] Qemu-Xen-vTPM: QEMU machin
On Thursday, November 06, 2014 05:36:04 PM Eduardo Otubo wrote:
> On Thu, Nov 06, 2014 at 11:22:16AM -0500, Paul Moore wrote:
> > On Thursday, November 06, 2014 03:49:18 PM Eduardo Otubo wrote:
> > > Right now seccomp is breaking the compilation of Qemu on armv7l due
> > > to libsecomp current lack
On Thu, Nov 06, 2014 at 12:51:23PM +0800, Gonglei wrote:
> On 2014/11/5 23:32, Peter Maydell wrote:
>
> > Hi; I've just tagged v2.2.0-rc0 in master, so we're now officially
> > in hardfreeze, and only accepting bug fixes from here onward.
> > Mike Roth should have the rc0 tarballs out sometime lat
On Thursday, November 06, 2014 10:24:41 AM Eduardo Otubo wrote:
> Paul, do you have any plans for a new libseccomp release?
Yes, I have plans. Do I have a date, no. ;)
I was trying to sync up with support for a new ABI, but I believe that was
pushed to v3.19. I'll need to check on things, but
On Thu, Nov 06, 2014 at 11:22:16AM -0500, Paul Moore wrote:
> On Thursday, November 06, 2014 03:49:18 PM Eduardo Otubo wrote:
> > Right now seccomp is breaking the compilation of Qemu on armv7l due
> > to libsecomp current lack of support for this arch. This problem is
> > already fixed on libsecco
On 06/11/2014 17:18, Igor Mammedov wrote:
> On Thu, 06 Nov 2014 16:57:47 +0100
> Paolo Bonzini wrote:
>
>> On 06/11/2014 07:53, Hanjun Guo wrote:
So the important question is _why_ the guest needs to see an ACPI
environment. What exactly can ACPI provide to the guest that DT does not
In the previous patch, the registers were added to init_proc_G2LE
instead of init_proc_e300.
Signed-off-by: Fabien Chouteau
---
target-ppc/translate_init.c | 52 +--
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/target-ppc/translate_ini
On Thu, Nov 06, 2014 at 03:49:04PM +, Peter Maydell wrote:
> On 6 November 2014 14:49, Eduardo Otubo
> wrote:
> > Right now seccomp is breaking the compilation of Qemu on armv7l due
> > to libsecomp current lack of support for this arch. This problem is
> > already fixed on libseccomp upstrea
On Thursday, November 06, 2014 03:49:18 PM Eduardo Otubo wrote:
> Right now seccomp is breaking the compilation of Qemu on armv7l due
> to libsecomp current lack of support for this arch. This problem is
> already fixed on libseccomp upstream but no release date for that is
> scheduled to far. This
On Thu, 06 Nov 2014 16:57:47 +0100
Paolo Bonzini wrote:
> On 06/11/2014 07:53, Hanjun Guo wrote:
> >> So the important question is _why_ the guest needs to see an ACPI
> >> environment. What exactly can ACPI provide to the guest that DT does not
> >> already provide, and why is that necessary? Wh
smp_parse has a couple problems. First, it should use max_cpus,
not smp_cpus when calculating missing topology information.
Conversely, if maxcpus is not input, then the topology should
dictate max_cpus, as the topology may support more than the
input smp_cpus number. Second, smp_parse shouldn't si
Markus, Kevin, Stefan,
here is a (somewhat late) followup of some KVM forum discussions regarding
block size and geometry of pass-through block devices. Let's just do a quick
wrap-up (as of my understanding) and a proposal at the end of the mail
- DASD/ECKD disk devices have several special p
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Cleaned-up ats_write() to only call A32_BANKED_CURRENT_REG_
On Thu, 6 Nov 2014, Xu, Quan wrote:
> > -Original Message-
> > From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> > Sent: Thursday, November 06, 2014 11:42 PM
> > To: Xu, Quan
> > Cc: Stefano Stabellini; qemu-devel@nongnu.org; xen-de...@lists.xen.org
> > Subject: RE: [PATC
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Reordered CP register component order
- Removed
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Revert unnecessary CPreg definition ch
On Thu, Nov 06, 2014 at 03:14:19PM +0100, Eric Blake wrote:
> On 11/06/2014 02:57 PM, Markus Armbruster wrote:
>
> >> Yes, you can override the backing file driver (backing.driver=raw should
> >> do the trick). Not really user-friendly, especially with long backing
> >> file chains, but it happens
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Added endianness support to the MAIR field structure definition.
v5 -> v6
- Changed _el field variants to be array based
---
target-arm/cpu.h| 21 +
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v3 -> v4
- Reverted esr/dfsr back to array-based notation as a union
From: Fabian Aggeler
Adds secure and non-secure bank register suport for TTBR0 and TTBR1.
Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as
well as a CP register definition for TTBR0_EL3. Added a union containing
both EL based array fields and secure and non-secure fie
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and
storage.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Added definition for IFSR32_EL2
- Changed ifs
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Added definition for DACR32_EL2
- Changed dacr cp15 f
Artyom Tarasenko writes:
> Hello Damien,
>
> On Thu, Nov 6, 2014 at 8:38 AM, Damien Hilloulin
> wrote:
>> Hello everyone,
>>
>> I'm a newcomer in QEMU and my goal would be to port an existing system
>> simulator using another emulator to QEMU.
>> However, it seems that the Sparc targets doesn'
From: Fabian Aggeler
Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits
are used to control whether the CPSR masking bits can be adjusted from
non-secure state.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Move cpsr_write mask filtering a
From: Fabian Aggeler
Rename CSSELR (cache size selection register) and add secure
instance (AArch32).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Replaced call to ARM_CP_SECSTATE_TEST with direct access
v7 -> v8
- Fix CSSELR CP regist
On 06/11/2014 07:53, Hanjun Guo wrote:
>> So the important question is _why_ the guest needs to see an ACPI
>> environment. What exactly can ACPI provide to the guest that DT does not
>> already provide, and why is that necessary? What infrastrucutre is
>> needed for that use case?
>
> There is im
From: Fabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v9 -> v10
- Fix SCTLR to use opc0 instead of cp
v8 -> v9
- Remove the v8 check in arm_cpu_reset when setting regs[15]
- Fix SCTLR definiti
From: Sergey Fedorov
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter .
The TBFLAG captures the SCR NS secure state at the time when a TB is created so
the correct bank is accessed on system reg
Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for
register storage.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Fixed declaration order of the SDER register components
v7 -> v8
From: Fabian Aggeler
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d3db279..1871865 10064
From: Fabian Aggeler
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Removed unused NSACR constants
- Added TODO for trap
From: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Fixed declaration order of the MVBARR registe
From: Fabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
--
From: Fabian Aggeler
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Fixed setting of secure field in add_cpreg_to_hashtable so it uses secstate
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Changed contextidr structure definiti
Added additional NS-bit to CPREG hash encoding. Updated hash lookup
locations to specify hash bit currently set to non-secure.
Signed-off-by: Greg Bellows
---
v8 -> v9
- Fixed CP_REG_NS_MASK
- Changed ENCODE_CP_REG argument order so ns follows is64
- Replaced use of CP_REG_NS_MASK with CP_REG_
From: Fabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Also added secure state tracking field and flags. This allows for
i
From: Fabian Aggeler
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving AArch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
From: Fabian Aggeler
If EL3 is in AArch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.
- A32_BANKED macros are used for choosing the banked register based on provided
input security ar
From: Fabian Aggeler
Adds secure and non-secure bank register suport for TTBCR.
Added new struct to compartmentalize the TCR data and masks. Removed old
tcr/ttbcr data and added a 4 element array of the new structs in cp15. This
allows for one entry per EL. Added a CP register definition for T
Version 10 of the ARM processor security extension (TrustZone) support. This
patchset includes changes to support the processor security extensions
on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
This is a rebase of v9 to a more recent master as well as a fix for an
overlooked bug i
Adds a dedicated function and a lookup table for determining the target
exception level of IRQ and FIQ exceptions. The lookup table is taken from the
ARMv7 and ARMv8 specification exception routing tables.
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Fixed target_el_t
This patch extends arm_excp_unmasked() to use lookup tables for determining
whether IRQ and FIQ exceptions are masked. The lookup tables are based on the
ARMv8 and ARMv7 specification physical interrupt masking tables.
If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels
oth
On 6 November 2014 14:49, Eduardo Otubo wrote:
> Right now seccomp is breaking the compilation of Qemu on armv7l due
> to libsecomp current lack of support for this arch. This problem is
> already fixed on libseccomp upstream but no release date for that is
> scheduled to far. This patch disables
> -Original Message-
> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> Sent: Thursday, November 06, 2014 11:42 PM
> To: Xu, Quan
> Cc: Stefano Stabellini; qemu-devel@nongnu.org; xen-de...@lists.xen.org
> Subject: RE: [PATCH 2/4] Qemu-Xen-vTPM: Register Xen stubdom vTP
* Li Liang (liang.z...@intel.com) wrote:
> Instead of sending the guest memory directly, this solution compress
> the ram page before sending, after receiving, the data will be
> decompressed.
> This feature can help to reduce the data transferred about
> 60%, this is very useful when the network b
On Thu, 6 Nov 2014, Xu, Quan wrote:
> > -Original Message-
> > From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> > Sent: Monday, November 03, 2014 7:54 PM
> > To: Xu, Quan
> > Cc: qemu-devel@nongnu.org; xen-de...@lists.xen.org;
> > stefano.stabell...@eu.citrix.com
> > Sub
Hello Damien,
On Thu, Nov 6, 2014 at 8:38 AM, Damien Hilloulin
wrote:
> Hello everyone,
>
> I'm a newcomer in QEMU and my goal would be to port an existing system
> simulator using another emulator to QEMU.
> Some work has already been done, and Sparc has been the main target so far
> because of
In the enqueue path, we can't complete request, otherwise
"Co-routine re-entered recursively" may be caused, so this
patch fixes the issue with below ideas:
- for -EAGAIN or partial completion, retry the submision by
schedule an BH in following completion cb
- for part of c
Previously -EAGAIN is simply ignored for !s->io_q.plugged case,
and sometimes it is easy to cause -EIO to VM, such as NVME device.
This patch handles -EAGAIN by io queue for !s->io_q.plugged case,
and it will be retried in following aio completion cb.
Suggested-by: Paolo Bonzini
Signed-off-by: M
The 1st patch fixes batch submission.
The 2nd one fixes -EAGAIN for non-batch case.
The 3rd one is a cleanup.
This patchset is splitted from previous patchset(dataplane: optimization
and multi virtqueue support), as suggested by Stefan.
v3:
- rebase on QEMU master
v2:
- code sty
No one uses the 'node' field any more, so remove it
from 'struct qemu_laiocb', and this can save 16byte
for the struct on 64bit arch.
Signed-off-by: Ming Lei
---
block/linux-aio.c |1 -
1 file changed, 1 deletion(-)
diff --git a/block/linux-aio.c b/block/linux-aio.c
index f5ca41d..b12da25 1
Christopher Covington writes:
> Hi,
>
> [snip--for full message see
> https://groups.google.com/d/msg/android-emulator-dev/dltBnUW_HzU/2tSZNLaVzmQJ]
>
>> 5) Relationship with upstream
>>
>> In an ideal world, we would not need a fork, and all code would live on
>> the upstream QEMU git.
>>
>> I
Am 06.11.2014 um 14:57 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > Am 04.11.2014 um 19:45 hat Markus Armbruster geschrieben:
> >> I'll try to explain all solutions fairly. Isn't easy when you're as
> >> biased towards one of them as I am. Please bear with me.
> >>
> >>
> >>
On Thu, Nov 06, 2014 at 02:37:54PM +0800, Amos Kong wrote:
> On Wed, Nov 05, 2014 at 09:47:47AM +0100, Gerd Hoffmann wrote:
> > On Mi, 2014-11-05 at 00:49 +0800, Amos Kong wrote:
> > > qemu_input_find_handler() prefers a handler associated with con.
> > > But if none exists, it takes any. This patc
On 2014-11-06 at 15:56, Jeff Cody wrote:
On Thu, Nov 06, 2014 at 01:53:35PM +0100, Max Reitz wrote:
On 2014-11-06 at 13:26, Markus Armbruster wrote:
Max Reitz writes:
On 2014-11-04 at 19:45, Markus Armbruster wrote:
I'll try to explain all solutions fairly. Isn't easy when you're as
biased
On Thu, Nov 06, 2014 at 01:53:35PM +0100, Max Reitz wrote:
> On 2014-11-06 at 13:26, Markus Armbruster wrote:
> >Max Reitz writes:
> >
> >>On 2014-11-04 at 19:45, Markus Armbruster wrote:
> >>>I'll try to explain all solutions fairly. Isn't easy when you're as
> >>>biased towards one of them as I
Hi folks,
I am looking for feedback regarding work-in-progress or planned CPU power
management features for Qemu-KVM based Virtual Machines.
Looking back through the mailing list archives I did not find any discussion
or patches relating to the general problem of virtual machine power
management.
I spent some time with Andrei Ostanin's "Playing with Mac OS X on KVM"
(http://blog.ostanin.org/2014/02/11/playing-with-mac-os-x-on-kvm/) which
works like a charm, except for the final part where I am supposed to
install a bootloader (Chimera, Chameleon) to be able to boot my virtual
machine. In pr
Right now seccomp is breaking the compilation of Qemu on armv7l due
to libsecomp current lack of support for this arch. This problem is
already fixed on libseccomp upstream but no release date for that is
scheduled to far. This patch disables support for seccomp on armv7l
temporarily until libsecco
Now qemu only supports vhd type VHD_FIXED and VHD_DYNAMIC, so qemu
can't read snapshot volume of vhd, and can't support other storage
features of vhd file.
This patch add read parent information in function "vpc_open", read
bitmap in "vpc_read", and change bitmap in "vpc_write".
Signed-off-by: Xi
On Thu, Nov 06, 2014 at 02:57:07PM +0100, Markus Armbruster wrote:
> Kevin Wolf writes:
>
> > Am 04.11.2014 um 19:45 hat Markus Armbruster geschrieben:
[...]
> >> I proposed something less radical, namely to keep guessing the image
> >> format, but base the guess on trusted meta-data only: file
On 2014-10-31 2:02, Mark Rutland wrote:
> On Thu, Oct 30, 2014 at 05:52:44PM +, Peter Maydell wrote:
>> On 30 October 2014 17:43, Alexander Spyridakis
>> wrote:
>>> Currently, the virt machine model generates Device Tree information
>>> dynamically based on the existing devices in the system.
Now qemu only supports vhd type VHD_FIXED and VHD_DYNAMIC, so qemu
can't read snapshot volume of vhd, and can't support other storage
features of vhd file.
This patch add read parent information in function "vpc_open", read
bitmap in "vpc_read", and change bitmap in "vpc_write".
Signed-off-by: Xi
Fix build failure that would be caused by missing pc_dimm_count()
that was introduced in dropped
[03/11] pc: check if KVM has enough memory slots for DIMM devices
Signed-off-by: Igor Mammedov
---
hw/i386/pc.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i
On 11/06/2014 02:57 PM, Markus Armbruster wrote:
>> Yes, you can override the backing file driver (backing.driver=raw should
>> do the trick). Not really user-friendly, especially with long backing
>> file chains, but it happens to be there.
>>
>> And of course, libvirt should be using it for non-
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