On Fri, 10/10 16:52, Ken Chiang wrote:
> Hello,
>
> I am trying to add a block device dynamically using qmp and are having some
> issues.
>
> After successfully adding the block device using "blockdev-add" and verifying
> that it has been added using "query-block", I am unable to see the block
Hi all,
When i try to passthrough BCM5719 Gigabit Ethernet to guest using the qemu
master branch, it aborted,
and show kvm_set_phys_mem:error registering slot:Bad Address.
qemu command:
#./qemu/qemu/x86_64-softmmu/qemu-system-x86_64 --enable-kvm -smp 4 -m 4096 -vnc
:99 -device virtio-scsi-pci,
On 2014/10/11 11:44, Eric Blake wrote:
> On 10/10/2014 09:32 PM, Gonglei wrote:
>
Actually, I had noted that C standard says it is a no-operation.
But that doesn't mean that every C-library handles it like that.
>>>
>>> EVERY libc that is C89 compliant handles it like that. The last
>>
On 10/10/2014 09:32 PM, Gonglei wrote:
>>> Actually, I had noted that C standard says it is a no-operation.
>>> But that doesn't mean that every C-library handles it like that.
>>
>> EVERY libc that is C89 compliant handles it like that. The last
>> platform that failed on free(NULL) was SunOS 4,
On 2014/10/11 11:26, Eric Blake wrote:
> On 10/10/2014 09:21 PM, Gonglei wrote:
>
>>
>> Actually, I had noted that C standard says it is a no-operation.
>> But that doesn't mean that every C-library handles it like that.
>
> EVERY libc that is C89 compliant handles it like that. The last
> plat
On 10/10/2014 09:21 PM, Gonglei wrote:
>
> Actually, I had noted that C standard says it is a no-operation.
> But that doesn't mean that every C-library handles it like that.
EVERY libc that is C89 compliant handles it like that. The last
platform that failed on free(NULL) was SunOS 4, which is
On 10/10/2014 08:54 PM, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> The caller of qemu_vfree() maybe not check whether parameter
> ptr pointer is NULL or not, such as vpc_open().
> Using g_free() is more safe.
NACK. g_free is only safe for pointers allocated by g_malloc.
qemu_vfree is fo
On 2014/10/11 11:10, Zhanghailiang wrote:
> On 2014/10/11 10:54, arei.gong...@huawei.com wrote:
>> From: Gonglei
>>
>> The caller of qemu_vfree() maybe not check whether parameter
>> ptr pointer is NULL or not, such as vpc_open().
>> Using g_free() is more safe.
>>
>
> It seems that free(NULL) i
On 2014/10/11 10:54, arei.gong...@huawei.com wrote:
From: Gonglei
The caller of qemu_vfree() maybe not check whether parameter
ptr pointer is NULL or not, such as vpc_open().
Using g_free() is more safe.
It seems that free(NULL) is harmless.
From section 7.20.3.2/2 of the C99 standard:
The
From: Gonglei
The caller of qemu_vfree() maybe not check whether parameter
ptr pointer is NULL or not, such as vpc_open().
Using g_free() is more safe.
Signed-off-by: Gonglei
---
util/oslib-posix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/oslib-posix.c b/util/os
kvm.git + qemu.git:da01e614_b6011bd8
test on Ivytown_EP
kernel version: 3.17.0
when create guest with bridge, and the bridge network driver is virtio, the
guest can get ip.
the bug cannot reproduce.
** Changed in: qemu
Status: New => Fix Released
--
You received this bug notification bec
On 2014/10/11 0:17, Xiaodong Gong wrote:
> Now qemu only supports vhd type VHD_FIXED and VHD_DYNAMIC, so qemu
> can't read snapshot volume of vhd, and can't support other storage
> features of vhd file.
>
> This patch add read parent information in function "vpc_open", read
> bitmap in "vpc_read"
Hello,
I am trying to add a block device dynamically using qmp and are having some
issues.
After successfully adding the block device using "blockdev-add" and verifying
that it has been added using "query-block", I am unable to see the block device
in the VM under /dev/sdXX
I am using ubuntu1
On Fri, 2014-10-10 at 20:44 +0100, Peter Maydell wrote:
> Following cleanup of the vga device code in commit d2e043a8041,
> the arrays dmask4 and dmask16 are now unused. gcc doesn't warn
> about this, but clang does; remove them.
Ah right, I missed those, thanks.
> Signed-off-by: Peter Maydell
>
Following cleanup of the vga device code in commit d2e043a8041,
the arrays dmask4 and dmask16 are now unused. gcc doesn't warn
about this, but clang does; remove them.
Signed-off-by: Peter Maydell
---
hw/display/vga.c | 26 --
1 file changed, 26 deletions(-)
diff --git a
On 10/10/2014 01:33 PM, Peter Maydell wrote:
> The local variable 'ac' in send_qmp_error_event() is declared with the
> wrong type, which causes clang to complain when it is initialized
> and again when it is used:
>
> block.c:3655:20: warning: implicit conversion from enumeration type 'enum
> Io
The local variable 'ac' in send_qmp_error_event() is declared with the
wrong type, which causes clang to complain when it is initialized
and again when it is used:
block.c:3655:20: warning: implicit conversion from enumeration type 'enum
IoOperationType' to different enumeration type 'BlockErrorA
411a696be1a7272b1c:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2014-10-09 15:09:05 +0100)
>
> are available in the git repository at:
>
>
> git://github.com/cohuck/qemu.git tags/s390x-20141010
>
> for you to fe
The ARM ARM requires that the FPINST and FPINST2 VFP control
registers are not accessible to code at EL0. We were already
correctly implementing this for reads of these registers; add
the missing check for the write code path.
Signed-off-by: Peter Maydell
---
target-arm/translate.c | 3 +++
1 fi
For the CPU type "any" (only used with linux-user) we were reporting
the L1Ip field as 0b00, which is reserved. Change this field to 0b10
instead, indicating a VIPT icache as the comment describes.
Signed-off-by: Peter Maydell
---
target-arm/cpu64.c | 2 +-
1 file changed, 1 insertion(+), 1 dele
This is a rather specific use case. Note that linux can use
partitionless diskspace just fine, and depending on the bootmanager, one
can use single partition as a virtual disk to boot linux too (syslinux
supports this mode for one). Implementing this feature in qemu does not
make much sense to me
On 10/10/2014 12:49 PM, Peter Maydell wrote:
> The DZP bit in the DCZID system register should be set if
> the control bits which prohibit use of the DC ZVA instruction
> have been set (it stands for Data Zero Prohibited). However
> we had the sense of the test inverted; fix this so that the
> bit
On Fri, Oct 10, 2014 at 8:24 PM, Peter Maydell wrote:
> On 14 September 2014 21:29, Max Filippov wrote:
>> On Sun, Sep 14, 2014 at 12:36 PM, Peter Maydell
>> wrote:
>>> The XtensaConfig structs will be defined but not used if they are
>>> for the opposite endianness from that of the binary being
Xorg server hangs when using xfig and typing a text with space:
#0 qxl_wait_for_io_command (qxl=) at qxl_io.c:47
#1 0x7f826a49a299 in qxl_download_box (surface=0x221d030, x1=231, y1=259,
x2=, y2=) at qxl_surface.c:143
while (!(ram_header->int_pending & QXL_INTERRUPT_IO_CMD))
The DZP bit in the DCZID system register should be set if
the control bits which prohibit use of the DC ZVA instruction
have been set (it stands for Data Zero Prohibited). However
we had the sense of the test inverted; fix this so that the
bit reads correctly.
To avoid this regressing the behaviou
On 08/26/2014 03:36 PM, Max Reitz wrote:
> Add a test for qcow2's fast bdrv_make_empty implementation on images
> without internal snapshots.
This test may need to be limited to compat=1.1 files.
>
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/098 | 78
> ++
On 09/10/2014 11:05 PM, Fam Zheng wrote:
> Signed-off-by: Fam Zheng
> ---
> blockdev.c | 48
> qapi-schema.json | 3 +++
> 2 files changed, 51 insertions(+)
>
> +++ b/qapi-schema.json
> @@ -1251,11 +1251,14 @@
> #
> # A discriminated rec
On 10 October 2014 16:19, Ard Biesheuvel wrote:
> Move the registering of CPU reset handlers to before the point where
> we leave the function in the -bios (not -kernel) case, so CPU reset
> works correctly with -bios as well.
>
> Signed-off-by: Ard Biesheuvel
> ---
Applied to target-arm.next,
From: Fabian Aggeler
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8ba72ed..fa12602 10064
On 14 September 2014 21:29, Max Filippov wrote:
> On Sun, Sep 14, 2014 at 12:36 PM, Peter Maydell
> wrote:
>> The XtensaConfig structs will be defined but not used if they are
>> for the opposite endianness from that of the binary being built;
>> keep the compiler from complaining about this by m
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
---
target-arm/cpu.h| 12 +++-
target-arm/helper.c | 8 +---
2 files changed, 16 insertions(+), 4 deletions(-)
dif
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to
From: Fabian Aggeler
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Switch to use distinct CPREG secure flags
v4 -> v
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 9 +
2 files changed, 14 inser
On 10/10/2014 05:39 AM, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> This patch-pair adds the QEMUSizedBuffer based in-memory QEMUFile
> written by Stefan Berger and Joel Schopp. I've made some
> fixes and modified the existing test-vmstate to use it for some test c
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/pxa2xx.c | 2 +-
target-arm/cpu.h| 13 +++--
target-arm/helper.c | 19
From: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 15 +--
2 files changed
Now qemu only supports vhd type VHD_FIXED and VHD_DYNAMIC, so qemu
can't read snapshot volume of vhd, and can't support other storage
features of vhd file.
This patch add read parent information in function "vpc_open", read
bitmap in "vpc_read", and change bitmap in "vpc_write".
Signed-off-by: Xi
On 10/10/2014 02:16 AM, Magnus Reftel wrote:
> On Thu, Oct 9, 2014 at 11:30 PM, Eric Blake wrote:
>> On 10/09/2014 01:12 PM, Magnus Reftel wrote:
>>> +if (parse_uint(arg, &seed, &end, 0) != 0 || *end != 0 || seed >
>>> UINT_MAX) {
>>
>> Slightly shorter as:
>>
>> if (parse_uint_full(arg, &see
From: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4d9f6f8..64208bc 100644
--- a/targe
From: Fabian Aggeler
Rename CSSELR (cache size selection register) and add secure
instance (AArch32).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Switch to use distinct CPREG secure flags.
- Merged CSSELR and
From: Fabian Aggeler
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving AArch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
From: Fabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Consolidate SCTLR and SCTLR_EL1 reginfo entries
---
hw/arm/pxa2xx.c
On 9 October 2014 14:00, wrote:
> From: KONRAD Frederic
>
> This removes num_irq parameter from gic_init_irqs_and_distributor as it is not
> used.
>
> Signed-off-by: KONRAD Frederic
> ---
Thanks, applied to target-arm.next.
-- PMM
From: Fabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 9 +
From: Fabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Also added secure state tracking field and flags. This allows for
i
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Merged VBAR and VBAR_EL1 reginfo
Added additional NS-bit to CPREG hash encoding. Updated hash lookup
locations to specify hash bit currently set to non-secure.
Signed-off-by: Greg Bellows
==
v5 -> v6
- Globally replace Aarch# with AArch#
---
target-arm/cpu.h | 25 -
target-arm/helper.c
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
-
v3 -> v4
- Revert to array-based notation of far_el in combination with v7
From: Fabian Aggeler
If EL3 is in AArch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.
- A32_BANKED macros are used for choosing the banked register based on provided
input security ar
From: Fabian Aggeler
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Fixed NS-bit number in the CPREG hash lookup from 27 to 29.
- Switch
From: Sergey Fedorov
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter .
The TBFLAG captures the SCR NS secure state at the time when a TB is created so
the correct bank is accessed on system reg
From: Fabian Aggeler
Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
translation functions to use TCR/TTBCR instance depending on CPU state.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
v4 -
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Reverted esr/dfsr back to array-based notation as a union with v7 naming.
-
From: Fabian Aggeler
Add TTBR0 and maps secure/non-secure instance of ttbr0 and ttbr1
accordingly (translation table base register).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Merged TTBR# and TTBR#_EL1 regin
From: Fabian Aggeler
bits when modifying CPSR.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Fixed up conditions for ignoring CPSR.A/F updates by isolating to v7 and
checking for the existence of EL3 and non-existence of EL2.
---
target-arm/helper.c |
From: Fabian Aggeler
Implements SMC instruction in AArch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Fixed PC offsetting for
From: Fabian Aggeler
This patch extends arm_excp_unmasked() according to ARM ARMv7 and
ARM ARMv8 (all EL running in AArch32) and adds comments.
If EL3 is using AArch64 IRQ/FIQ masking is ignored in
all exception levels other than EL3 if SCR.{FIQ|IRQ} is
set to 1 (routed to EL3).
Signed-off-by:
From: Fabian Aggeler
Adds a dedicated function for IRQ and FIQ exceptions to determine
target_el and mode (AArch32) according to tables in ARM ARMv8 and
ARM ARM v7.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Removed unneeded arm_phys_excp_target_el() func
From: Fabian Aggeler
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed to use renamed arm_current_el()
---
target-arm/cpu.h| 6
From: Fabian Aggeler
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Updated vmstate_arm_cpu versioning from 20 to 21
---
target-arm/cpu.h | 4 ++--
target-arm/machine.c | 8 +
Version 6 of the ARM processor security extension (TrustZone) support.
This patchset includes changes to support the processor security extensions
on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
Summary of generic changes from v5 -> v6:
- Removed patch v5 32/33 (add GDB scr register)
From: Sergey Fedorov
Reject switching to monitor mode from non-secure state.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper
From: Fabian Aggeler
Make arm_current_el() return EL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly infered from arm_
current_el(). Changes assertion in arm_el_is_aa64() to allow EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 ->
From: Fabian Aggeler
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellow
Renamed the arm_current_pl CPU function to more accurately represent that it
returns the ARMv8 EL rather than ARMv7 PL.
Signed-off-by: Greg Bellows
==
v5 -> v6
- Renamed DisasContext current_pl field to current_el
- Added comment to arm_current_el on handling v7 PL
- Fixed comments refe
On 10/10/2014 06:32 AM, Eric Blake wrote:
> On 08/26/2014 03:36 PM, Max Reitz wrote:
>> bdrv_make_empty() is currently only called if the current image
>> represents an external snapshot that has been committed to its base
>> image; it is therefore unlikely to have internal snapshots. In this
>> ca
On 10 October 2014 15:58, Claudio Fontana wrote:
> On 10.10.2014 13:32, Peter Maydell wrote:
>> Thanks for catching this. Better to fix it by dropping
>> the unnecessary local variable completely and just setting
>> info._sifields._sigfault._addr = env->exception.vaddress;
>> at the only point w
Move the registering of CPU reset handlers to before the point where
we leave the function in the -bios (not -kernel) case, so CPU reset
works correctly with -bios as well.
Signed-off-by: Ard Biesheuvel
---
Changes since v2:
- split into two loops again, as the boot_info field must not be assign
Il 10/10/2014 16:52, Paul Durrant ha scritto:
>> -Original Message-
>> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
>> Sent: 10 October 2014 15:40
>> To: Paul Durrant
>> Cc: qemu-devel@nongnu.org; xen-de...@lists.xenproject.org; Michael S.
>> Tsirkin; Stefano Stabellin
On 10 October 2014 12:35, Ard Biesheuvel wrote:
> Move the registering of CPU reset handlers to before the point where
> we leave the function in the -bios (not -kernel) case, so CPU reset
> works correctly with -bios as well.
>
> Signed-off-by: Ard Biesheuvel
> ---
> hw/arm/boot.c | 12 ++--
On 10.10.2014 13:32, Peter Maydell wrote:
> On 10 October 2014 05:22, Amanieu d'Antras wrote:
>> On AArch64 the si_addr field of siginfo_t is truncated to 32 bits
>> because the fault address passes through an uint32_t variable. This
>> is fixed by changing the variable to uint64_t.
>>
>> Signed-o
Hello,
On 10.10.2014 14:09, Jiri Slaby wrote:
> I am using qemu for teaching the Linux kernel at our university. I
> wrote a simple PCI device that can answer to writes/reads, generate
> interrupts and perform DMA. As I am dragging it locally over 2 years,
> I am sending it to you now.
>
> Signed
> -Original Message-
> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> Sent: 10 October 2014 15:40
> To: Paul Durrant
> Cc: qemu-devel@nongnu.org; xen-de...@lists.xenproject.org; Michael S.
> Tsirkin; Stefano Stabellini; Peter Maydell; Paolo Bonzini; Michael Tokarev;
>
On 10 October 2014 11:59, Antony Pavlov wrote:
> Running barebox on qemu-system-mips* with '-d unimp' overloads
> stderr by very very many mips_cpu_handle_mmu_fault() messages:
>
> mips_cpu_handle_mmu_fault address=b80003fd ret 0 physical 180003fd
> prot 3
> mips_cpu_handle_mmu_fault
On Fri, 10 Oct 2014, Paul Durrant wrote:
> The ioreq-server API added to Xen 4.5 offers better security than
> the existing Xen/QEMU interface because the shared pages that are
> used to pass emulation request/results back and forth are removed
> from the guest's memory space before any requests ar
On 14/07/2014 10:55, Yongbok Kim wrote:
> add MSA branch instructions
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 107
> ++-
> 1 files changed, 105 insertions(+), 2 deletions(-)
>
> diff --git a/target-mips/translate.c b/target-
On 10/10/14 09:44, Stefano Stabellini wrote:
On Thu, 9 Oct 2014, Don Slutz wrote:
This adds synchronisation of the 6 vcpu registers (only 32bits of
them) that vmport.c needs between Xen and QEMU.
This is to avoid a 2nd and 3rd exchange between QEMU and Xen to
fetch and put these 6 vcpu register
The ioreq-server API added to Xen 4.5 offers better security than
the existing Xen/QEMU interface because the shared pages that are
used to pass emulation request/results back and forth are removed
from the guest's memory space before any requests are serviced.
This prevents the guest from mapping
On 10 October 2014 11:23, Paolo Bonzini wrote:
> As usual, SLES11's GCC complained about double typedefs:
>
> /home/cohuck/git/qemu/kvm-all.c:110: error: redefinition of typedef ‘KVMState’
> /home/cohuck/git/qemu/include/sysemu/kvm.h:161: error: previous declaration
> of ‘KVMState’ was here
>
> R
On Thu, 9 Oct 2014, Don Slutz wrote:
> This adds synchronisation of the 6 vcpu registers (only 32bits of
> them) that vmport.c needs between Xen and QEMU.
>
> This is to avoid a 2nd and 3rd exchange between QEMU and Xen to
> fetch and put these 6 vcpu registers used by the code in vmport.c
> and v
于 10/10/14, 7:37 PM, Zhang Haoyu 写道:
Hi,
Is it worthy to introduce a unified co-scheduling mechanism to CFS ?
Because multiple cooperating threads or tasks frequently synchronize
with each other,
not executing them concurrently would only increase the latency of
synchronization.
For example,
From: Thomas Huth
This patch provides the cpu save information for dumps and later life
migration and enables migration of the CPU state. The code is based on
earlier work from Christian Borntraeger and Jason Herne.
Signed-off-by: Thomas Huth
Signed-off-by: David Hildenbrand
[provide cpu_post_
The vhost-scsi-ccw backend is of type VHostSCSICcw, not VirtIOSCSICcw.
This fixes a segfault when invoking
qemu-system-s390x -device vhost-scsi-ccw,?
Reviewed-by: Thomas Huth
Tested-by: Christian Borntraeger
Signed-off-by: Cornelia Huck
---
hw/s390x/virtio-ccw.c |2 +-
1 file changed
From: David Hildenbrand
This patch makes sure that halting a cpu and stopping a cpu are two different
things. Stopping a cpu will also set the cpu halted - this is needed for common
infrastructure to work (note that the stop and stopped flag cannot be used for
our purpose because they are already
From: Jens Freimann
Sync headers with 3.17-rc7
Acked-by: Paolo Bonzini
Signed-off-by: Jens Freimann
Signed-off-by: Cornelia Huck
---
linux-headers/asm-mips/kvm_para.h |6 +-
linux-headers/asm-powerpc/kvm.h |2 ++
linux-headers/asm-x86/kvm.h |3 +++
linux-headers/linux
From: David Hildenbrand
Let QEMU propagate the cpu state to kvm. If kvm doesn't yet support it, it is
silently ignored as kvm will still handle the cpu state itself in that case.
The state is not synced back, thus kvm won't have a chance to actively modify
the cpu state. To do so, control has to
From: David Hildenbrand
This patch reuses kvm_s390_reset_vcpu() to get rid of some CONFIG_KVM and
CONFIG_USER_ONLY ifdefs in cpu.c.
In order to get rid of CONFIG_USER_ONLY, kvm_s390_reset_vcpu() has to provide a
dummy implementation - the two definitions are moved to the proper section in
cpu.h.
From: David Hildenbrand
Until now, when a s390 cpu was stopped or halted, the number of running
CPUs was tracked in a global variable. This was problematic for migration,
so Jason came up with a per-cpu running state.
As it turns out, we want to track the full logical state of a target vcpu,
so w
From: David Hildenbrand
We need to synchronize registers after a reset has been performed. The
current code does that in qemu_system_reset(), load_normal_reset() and
modified_clear_reset() for all vcpus. After SIGP (INITIAL) CPU RESET,
this needs to be done for the targeted vcpu as well, so let's
for-upstream' into staging
(2014-10-09 15:09:05 +0100)
are available in the git repository at:
git://github.com/cohuck/qemu.git tags/s390x-20141010
for you to fetch changes up to 4b7757bae7c94f980969031119db12d540cf2b61:
s390x/virtio-ccw: fix vhost-scsi intialization (20
Jason Wang writes:
> Commit 1ceef9f27359cbe92ef124bf74de6f792e71f6fb (net: multiqueue
> support) tries to use set_pointer() and get_pointer() to set and get
> NICPeers which is not a pointer defined in DEFINE_PROP_NETDEV. This
> trick works but result a unclean and fragile implementation (e.g
> p
I am using qemu for teaching the Linux kernel at our university. I
wrote a simple PCI device that can answer to writes/reads, generate
interrupts and perform DMA. As I am dragging it locally over 2 years,
I am sending it to you now.
Signed-off-by: Jiri Slaby
---
MAINTAINERS | 5 +
> +*nb_clusters = cluster + cluster_count - contiguous_free_clusters;
> +*refcount_table = g_try_realloc(*refcount_table,
> +*nb_clusters * sizeof(uint16_t));
Something tells me that these sizeof(uint16_t) are connected to
s->refcount_order
On 08/26/2014 03:36 PM, Max Reitz wrote:
> bdrv_make_empty() is currently only called if the current image
> represents an external snapshot that has been committed to its base
> image; it is therefore unlikely to have internal snapshots. In this
> case, bdrv_make_empty() can be greatly sped up by
On Fri, Aug 29, 2014 at 11:40:53PM +0200, Max Reitz wrote:
> The size of a refblock entry is (in theory) variable; calculate
> therefore the number of entries per refblock and the according bit shift
> (1 << x == entry count) when opening an image.
>
> Signed-off-by: Max Reitz
> ---
> block/qcow
On (Fri) 10 Oct 2014 [12:23:21], Peter Maydell wrote:
> On 10 October 2014 12:19, Amit Shah wrote:
> > On (Thu) 09 Oct 2014 [14:04:53], Peter Maydell wrote:
> >> What I would like to see in this patch is a comment giving
> >> much clearer definition of the semantics of the guest_writable
> >> call
Fam Zheng writes:
> This applies cases on drive-backup on blockdev-backup, except cases with
> target format and mode.
>
> Also add a case to check source == target.
>
> Signed-off-by: Fam Zheng
> ---
> tests/qemu-iotests/055 | 277
> ++---
> tests/q
> +} else if (!num) {
> +error_report("Unexpected end of image");
> +return 0;
I think this test can miss some case of Unexpected end of image.
For example supose that in map_is_allocated the first bdrv_is_allocated
actually succeed then *pnum = num. Then the botto
>> Hi,
>>
>> Is it worthy to introduce a unified co-scheduling mechanism to CFS ?
>> Because multiple cooperating threads or tasks frequently synchronize
with each other,
>> not executing them concurrently would only increase the latency of
synchronization.
>> For example, a thread blocking in s
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