Juan Quintela writes:
> fwrite() returns the number of items written. But when there is one
> error, it can return a short write.
>
> In the particular bug that I was tracking, I did a migration to a
> read-only filesystem. And it was able to finish the migration
> correctly. fwrite() never re
Reviewers accepted v2 of the patch, but what got committed was v1,
with the R-bys for v2. This is the v1->v2 followup fix.
Signed-off-by: Markus Armbruster
---
qemu-file.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-file.c b/qemu-file.c
index f074af1..e5ec798 100644
Alexey Kardashevskiy writes:
> On 02/21/2014 09:30 PM, Paolo Bonzini wrote:
>> Il 21/02/2014 04:04, Alexey Kardashevskiy ha scritto:
>>> On 02/21/2014 12:50 AM, Alexey Kardashevskiy wrote:
> From: Paolo Bonzini
>
> This is a first step towards QOMifying /machine.
>
> Sig
Fam Zheng writes:
> Compiling util/modules.c with modules enabled fails now.
>
> Fix it by including qemu-common.h before #ifdef testing in module.c.
>
> Signed-off-by: Fam Zheng
> ---
> util/module.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/util/module.c b/util/
On 27 February 2014 12:21, Pranavkumar Sawargaonkar
wrote:
> We need to "Feed the kernel back its initial register state" using KVM
> ioctls for KVM ARM64 (just like KVM ARM). This means we need to save
> the "initial register state" in kvm_arch_init_vcpu() which is not the
> case for KVM ARM64 ri
On 27 February 2014 12:21, Pranavkumar Sawargaonkar
wrote:
> If we have in-kernel emulation of PSCI v0.2 for KVM ARM/ARM64 then
> we enable PSCI v0.2 for each VCPU at the time of VCPU init hence we
> need to provide PSCI v0.2 function IDs via generated DTB.
>
> This patch updates generated DTB to
On 27 February 2014 12:21, Pranavkumar Sawargaonkar
wrote:
> Provide versions of the KVM PSCI v0.2 constants to non-KVM code;
> this will allow us to avoid an ifdef in boards which set up a
> PSCI v0.2 node in the device tree.
>
> Signed-off-by: Pranavkumar Sawargaonkar
> Signed-off-by: Anup Pate
On 27 February 2014 12:21, Pranavkumar Sawargaonkar
wrote:
> Latest linux kernel supports in-kernel emulation of PSCI v0.2 but
> to enable it we need to select KVM_ARM_VCPU_PSCI_0_2 feature using
> KVM_ARM_VCPU_INIT ioctl.
>
> Also, we can use KVM_ARM_VCPU_PSCI_0_2 feature for VCPU only when
> lin
On 27 February 2014 12:21, Pranavkumar Sawargaonkar
wrote:
> In-kernel PSCI v0.2 emulation of KVM ARM/ARM64 forwards SYSTEM_OFF
> and SYSTEM_RESET function calls to QEMU using KVM_EXIT_SYSTEM_EVENT
> exit reason.
>
> This patch updates kvm_arch_handle_exit() to handle KVM_EXIT_SYSTEM_EVENT
> from
On 27 February 2014 12:21, Pranavkumar Sawargaonkar
wrote:
> QEMU Aarch64 tries various target types in kvm_arm_get_host_cpu_features()
> to determine perferred VCPU target type and VCPU features.
>
> This patch adds target type KVM_ARM_TARGET_XGENE_POTENZA to cpus_to_try[]
> of kvm_arm_get_host_c
On 27 February 2014 12:21, Pranavkumar Sawargaonkar
wrote:
> Syncup KVM related linux headers from v3.14-rc3.
>
> Signed-off-by: Pranavkumar Sawargaonkar
> Signed-off-by: Anup Patel
> ---
> linux-headers/asm-arm/kvm.h | 63 ++-
> linux-headers/asm-arm64/k
On 27 February 2014 12:21, Pranavkumar Sawargaonkar
wrote:
> Recentely patches have been posted for in-kernel emulation of PSCI v0.2
> http://www.spinics.net/lists/arm-kernel/msg305467.html
> This patchset adds the QEMU side changes for providing PSCI v0.2 to VM.
>
> Pranavkumar Sawargaonkar (7):
Eduardo Habkost writes:
> We had an unwritten rule about declarations having to be at beginning of
> blocks. Make it a written rule.
>
> Signed-off-by: Eduardo Habkost
> Reviewed-by: Stefan Weil
> ---
> Changes v2:
> * s/be at beginning/be at the beginning/
> ---
> CODING_STYLE | 7 +++
>
Zhang, Yang Z wrote on 2014-02-21:
> From: Yang Zhang
>
> The following patches are ported from Xen Qemu-traditional branch
> which are adding Intel IGD passthrough supporting to Qemu upstream.
>
> To pass through IGD to guest, user need to add following lines in Xen
> config file: gfx_passthru=
On Thu, Feb 27, 2014 at 06:31:33AM +0800, Fam Zheng wrote:
> Compiling util/modules.c with modules enabled fails now.
>
> Fix it by including qemu-common.h before #ifdef testing in module.c.
>
> Signed-off-by: Fam Zheng
> ---
> util/module.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(
The commit 88c1ee73d3231c74ff90bcfc084a7589670ec244
char/serial: Fix emptyness check
Still causes extra NULL byte(s) to be sent.
So if the fifo is empty, do not send an extra NULL byte.
Do full state change on fifo8_is_empty.
Signed-off-by: Don Slutz
---
v1 to v2: Do all the state changes that
On 02/21/2014 09:30 PM, Paolo Bonzini wrote:
> Il 21/02/2014 04:04, Alexey Kardashevskiy ha scritto:
>> On 02/21/2014 12:50 AM, Alexey Kardashevskiy wrote:
>>> > From: Paolo Bonzini
>>> >
>>> > This is a first step towards QOMifying /machine.
>>> >
>>> > Signed-off-by: Paolo Bonzini
>> I got inte
I did send a patch for dmidecode to exit gracefully if there is no bios
or smbus before it did all the mmap() damage, but no one seemed
interested in that patch. I was told that upstream is working on a
different approach.
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de
virtio: set virtio-mmio transport features for various backends
Hi Peter, i.e others -
This is a second attempt at setting transport backend features, for
back-ends that are instantiated separately from transport and dynamically
plugged in. virtio-mmio transport is addressed by this patch for vi
Signed-off-by: BALATON Zoltan
---
hw/char/serial-pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/char/serial-pci.c b/hw/char/serial-pci.c
index 991c99f..e662b77 100644
--- a/hw/char/serial-pci.c
+++ b/hw/char/serial-pci.c
@@ -60,6 +60,7 @@ static int serial_pci_init(PCIDevice *dev)
On Wed, 02/26 16:41, Stefan Hajnoczi wrote:
> On Wed, Feb 26, 2014 at 11:14:04AM +0100, Peter Lieven wrote:
> > I was wondering if it would be a good idea to set the O_DIRECT mode for the
> > source
> > files of a qemu-img convert process if the source is a host_device?
> >
> > Currently the back
On 02/26/2014 04:51 PM, Peter Maydell wrote:
> The function qobject_from_json() doesn't actually allow its
> argument to be a format string -- it passes a NULL va_list*
> to qobject_from_jsonv(), and the parser code will then never
> actually intepret %-escape sequences (it tests whether the
> va_l
The function qobject_from_json() doesn't actually allow its
argument to be a format string -- it passes a NULL va_list*
to qobject_from_jsonv(), and the parser code will then never
actually intepret %-escape sequences (it tests whether the
va_list pointer is NULL and will stop with a parse error).
This patch allows registers to be properly read from and written to
when using the gdbstub to debug a ppc guest running in little
endian mode. It accomplishes this goal by byte swapping the values of
any registers if the MSR:LE value is set.
Signed-off-by: Thomas Falcon
---
Differences from v3:
clang doesn't support the __noclone__ attribute and emits a warning about
it. Fortunately clang also implements a mechanism for asking if a particular
attribute is implemented; use it. We assume that if the compiler doesn't
support __has_attribute() then it must be GCC and must support __noclone__.
On 26 February 2014 22:58, Paolo Bonzini wrote:
> Il 26/02/2014 23:47, Peter Maydell ha scritto:
>
>> Some of our test binaries programmatically generate JSON format
>> strings to feed to qobject_from_json(). Since that function is
>> marked with GCC_FMT_ATTR(), clang complains about this:
>> tes
Il 26/02/2014 23:47, Peter Maydell ha scritto:
Some of our test binaries programmatically generate JSON format
strings to feed to qobject_from_json(). Since that function is
marked with GCC_FMT_ATTR(), clang complains about this:
tests/test-qmp-input-visitor.c:76:35: warning: format string is no
On 25 February 2014 14:07, Juan Quintela wrote:
> Hi
>
> Please pull, this include:
>
> - make rdma as stable (patch has been reviewed since long ago)(mrhines)
> - less_equal means less_equal not great_or_eual: (david and brown paperbag
> for me)
> - fix two XBZRLE corruptions
> - fwrite(): we ar
Some of our test binaries programmatically generate JSON format
strings to feed to qobject_from_json(). Since that function is
marked with GCC_FMT_ATTR(), clang complains about this:
tests/test-qmp-input-visitor.c:76:35: warning: format string is not a
string literal (potentially insecure) [-Wfor
Is there something we can do for ARM32 cloud-images so that customers
who might download the image and try to deploy it will not see this
issue? Something like:
dpkg-divert --local --divert /path/dmidecode --rename --add /bin/true
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On 02/26/2014 02:06 PM, Tom Musta wrote:
> s/AES_Te4/AES_Te*/
>
> And I should have added ...
>
> Even though I cannot use AES_Te4, I certainly can construct a flattened table
> for InvMixColumns (a la AES_T*). This will result in a faster implementation.
>
> Does it make sense to put this InvM
Compiling util/modules.c with modules enabled fails now.
Fix it by including qemu-common.h before #ifdef testing in module.c.
Signed-off-by: Fam Zheng
---
util/module.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/module.c b/util/module.c
index dc08c16..863a8a3 10064
On Sun, Feb 23, 2014 at 09:54:46AM +0800, Fam Zheng wrote:
> This is the common but non-trivial steps to assign or change the
> backing_hd of BDS.
>
> Signed-off-by: Fam Zheng
> ---
> block.c | 46 ++
> include/block/block.h | 1 +
> 2 f
This is a left-over from 4a1418e.
Signed-off-by: Hani Benhabiles
---
monitor.c | 4
1 file changed, 4 deletions(-)
diff --git a/monitor.c b/monitor.c
index aebcbd8..3863d83 100644
--- a/monitor.c
+++ b/monitor.c
@@ -2021,10 +2021,6 @@ int64_t dev_time;
static void do_info_profile(Monito
On 2/26/2014 1:22 PM, Tom Musta wrote:
> I see one problem with the PowerPC vncipher instruction. This instruction is
> not equivalent the aesdec. Moreover, the AddRoundKey (XOR) is performed
> *before*
> applying the InvMixColumns operation. So the AES_Te4 mapping is not correct
> for PPC.
s/
On Tue, Feb 25, 2014 at 1:39 AM, Alex Bennée wrote:
>
> Dann Frazier writes:
>
>> On Mon, Feb 17, 2014 at 6:40 AM, Alex Bennée wrote:
>>> Hi,
>>
>> Thanks to all involved for your work here!
>>
>>> After a solid few months of work the QEMU master branch [1] has now reached
>>> instruction featur
MacOSX doesn't pull .o files from .a archives if the symbol that it
requires is one which the .o file defines as a common symbol.
(Common symbols are those declared without "extern"; the linker
will merge together common symbols with the same name, so
redeclaring the same variable in two compilatio
Somebody may concisely refer tcg as a disassembler + a compiler (assembler).
I guess your question is how to calculate the value of i386 register
(%r10 in your case, the address for the helper function).
I might be wrong, my understanding is that it is calculated by the
assembler (to generate
On Sun, Feb 23, 2014 at 09:54:46AM +0800, Fam Zheng wrote:
> This is the common but non-trivial steps to assign or change the
> backing_hd of BDS.
>
> Signed-off-by: Fam Zheng
> ---
> block.c | 46 ++
> include/block/block.h | 1 +
> 2 f
"uname not i386 or x86_64" might be a better check -- restrict to the
archs where it actually works.
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https://bugs.launchpad.net/bugs/1243287
Title:
[KVM/QEMU][ARM][SAUCY] fails to boo
On 25 February 2014 13:33, Stefan Hajnoczi wrote:
> The following changes since commit c58e291591dbc1c846fa152d4792554803405ebb:
>
> Merge remote-tracking branch 'remotes/sstabellini/xen-140220' into staging
> (2014-02-24 16:12:55 +)
>
> are available in the git repository at:
>
>
> git:/
On Sun, Feb 23, 2014 at 09:54:50AM +0800, Fam Zheng wrote:
> This reuses the new bdrv_drop_intermediate.
>
> Signed-off-by: Fam Zheng
> ---
> block/stream.c | 30 +-
> 1 file changed, 1 insertion(+), 29 deletions(-)
>
> diff --git a/block/stream.c b/block/stream.c
>
From: Christoffer Dall
Save and restore the ARM KVM VGIC state from the kernel. We rely on
QEMU to marshal the GICState data structure and therefore simply
synchronize the kernel state with the QEMU emulated state in both
directions.
We take some care on the restore path to check the VGIC has b
On Wed, Feb 26, 2014 at 03:40:58PM +0100, Igor Mammedov wrote:
> From: Wanlong Gao
>
> Signed-off-by: Wanlong Gao
> Signed-off-by: Paolo Bonzini
> Signed-off-by: Igor Mammedov
> ---
> v2:
> - altered doc comment according to Eric Blake
> suggestions.
>
> Signed-off-by: Igor Mammedov
Implement the AArch64 view of the CPACR. The AArch64
CPACR is defined to have a lot of RES0 bits, but since
the architecture defines that RES0 bits may be implemented
as reads-as-written and we know that a v8 CPU will have
no registered coprocessors for cp0..cp13 we can safely
implement the whole r
On 24 February 2014 11:52, Gerd Hoffmann wrote:
> Hi,
>
> The input layer moves to a model modeled roughly after the linux
> event layer. It also uses qapi to create all the data types needed.
> First, because it is convinient to have all the support code generated,
> and also to make it easier
Add a cast to avoid an unintended sign extension that
would mean we returned 0x in the high 32 bits
for an IA0 read if bit 31 in the MAC address was 1.
(This is harmless since we'll only be doing 4 byte
reads, but it could be confusing, so best avoided.)
Signed-off-by: Peter Maydell
Revie
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits
to handle LPAE, but implemented as two separate uint32_t fields.
Combine them into a single uint64_t which can be used for all purposes.
Since this requires touching every use, take the opportunity to rename
the field to the a
There are various situations where we need to behave differently
depending on whether a given exception level is in AArch64 or
AArch32 state. The state of the current exception level is stored
in env->aarch64, but there's no equivalent guest-visible architected
state bits for the status of the exce
I just worked around this in cloud-init by disabling the smartOS datasource if
the uname arch is arm* or aarch*
http://bazaar.launchpad.net/~cloud-init-dev/cloud-init/trunk/view/head:/cloudinit/sources/DataSourceSmartOS.py
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d
On Wed, Feb 26, 2014 at 4:31 AM, Peter Maydell wrote:
> On 26 February 2014 03:32, Hu Tao wrote:
>> On Wed, Feb 26, 2014 at 10:49:59AM +0800, Hu Tao wrote:
>>> On Sat, Feb 15, 2014 at 04:07:24PM +, Peter Maydell wrote:
>>> > From: Rob Herring
>
>>> > /* Determine whether this address is
Correct some obviously nonsensical bit manipulation spotted by Coverity
when constructing the short-form PAR value for ATS operations.
Signed-off-by: Peter Maydell
Message-id: 1392659525-8335-1-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 4 ++--
1 file changed, 2 insertions
On Sun, Feb 23, 2014 at 09:54:49AM +0800, Fam Zheng wrote:
> Dropping intermediate could be useful both for commit and stream, and
> BDS refcnt plus bdrv_swap could do most of the job nicely. It also needs
> to work with op blockers.
>
> Signed-off-by: Fam Zheng
> ---
> block.c| 137
> +
** Branch linked: lp:cloud-init
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https://bugs.launchpad.net/bugs/1243287
Title:
[KVM/QEMU][ARM][SAUCY] fails to boot cloud-image due to host kvm fail
Status in QEMU:
Confirmed
Bug
The following changes since commit d5001cf787ad0514839a81d0f2e771e01e076e21:
xilinx: Delete hw/include/xilinx.h (2014-02-26 14:54:45 +1000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140226
for you to fetch changes up
From: Will Newton
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
Message-id: 1393411566-24104-2-git-send-email-will.new...@linaro.org
Signed-off-by: Peter Maydell
---
include/qemu/crc32c.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/crc32c.h b/i
From: Peter Crosthwaite
Use PRI formats as appropriate rather than raw %x and %d. This fixes
debug printfery on some host platforms. Fix types of debug only
variables as appropriate.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id:
dbb5f5fd048b2d4a3cb5c6357577d11211a7a5
On 2/24/2014 11:59 AM, Richard Henderson wrote:
> On 02/12/2014 01:23 PM, Tom Musta wrote:
>> +static uint8_t SBOX[256] = {
>
> I'm not keen on yet another copy of AES data.
>
> Please reuse "qemu/aes.h" as much as possible. Please see how we use those in
> target-i386; from a quick reading, the
On Tue, Feb 25, 2014 at 05:07:32PM +0800, Chen Fan wrote:
> Signed-off-by: Chen Fan
> ---
> hw/i386/pc.c | 40
> 1 file changed, 36 insertions(+), 4 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 348b15f..4e07ef9 100644
> --- a/hw/i386/
Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --g
We don't support letting the guest do debug, but Linux prods the
monitor debug system control register anyway, so implement a dummy
RAZ/WI version.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/targe
From: Peter Crosthwaite
When using event synchronisation, this particular debug printf floods.
Just delete it.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id:
dd94d19493f97c47497b9d8caf74ca43e70d58fd.1393372019.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Mayd
On Tue, Feb 25, 2014 at 05:07:31PM +0800, Chen Fan wrote:
[...]
> +Object *object_get_thread_from_index(int64_t cpu_index)
Probably the code that is going to call this function already knows what
will be the node/socket/core/thread IDs for the CPU. And if it doesn't,
we need to make the code node-
On 25 February 2014 11:50, Mark Cave-Ayland
wrote:
> Hi Peter,
>
> This branch contains updates for SPARC, particularly a new implementation of
> the CG3 framebuffer as
> reviewed on list, plus timer/hostid fixes from Olivier. Please pull.
Hi. This fails to build on 32 bit, I'm afraid:
/root/qe
On Mon, Feb 17, 2014 at 04:49:47PM +0100, Igor Mammedov wrote:
> From: Wanlong Gao
>
> libnuma choosed 128 for MAX_NODES, so we follow libnuma here.
>
> Signed-off-by: Wanlong Gao
> Signed-off-by: Paolo Bonzini
> Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
--
Eduardo
The raw read and write functions were using the ARM_CP_64BIT flag in
ri->type to determine whether to treat the register's state field as
uint32_t or uint64_t; however AArch64 register info structs don't use
that flag. Abstract out the "how big is the field?" test into a
function and fix it to work
Implement the AArch64 view of the system control register SCTLR_EL1.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index
On 24 February 2014 12:22, Gerd Hoffmann wrote:
> Hi,
>
> Short audio patch queue, with a single cleanup patch.
>
> please pull,
> Gerd
>
> The following changes since commit 105a060188dc6fdd4551571a966514d1a5f6815a:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-
On Wed, 2014-02-26 at 11:25 -0700, Alex Williamson wrote:
> The following changes since commit d5001cf787ad0514839a81d0f2e771e01e076e21:
>
> xilinx: Delete hw/include/xilinx.h (2014-02-26 14:54:45 +1000)
>
> are available in the git repository at:
>
> git://github.com/awilliam/qemu-vfio.git
From: Bandan Das
Certain cards such as the Broadcom BCM57810 have rom quirks
that exhibit unstable system behavior duing device assignment. In
the particular case of 57810, rom execution hangs and if a FLR
follows, the device becomes inoperable until a power cycle. This
change blacklists loading
From: Bandan Das
Setting opts before the realize property is set allows the
following patch to make decisions based on whether the user
specified "rombar". This also avoids having to create a new
tristate property especially for this purpose
Reviewed-by: Andreas Färber
Signed-off-by: Bandan Das
From: Markus Armbruster
readlink() doesn't write a terminating null byte.
assign_failed_examine() passes the unterminated string to strrchr().
Oops. Terminate it.
Spotted by Coverity.
Signed-off-by: Markus Armbruster
Reviewed-by: Peter Maydell
Signed-off-by: Alex Williamson
---
hw/i386/kvm
From: Markus Armbruster
readlink() returns the number of bytes written to the buffer, and it
doesn't write a terminating null byte. vfio_init() writes it itself.
Overruns the buffer when readlink() filled it completely.
Fix by treating readlink() filling the buffer completely as error,
like we
The following changes since commit d5001cf787ad0514839a81d0f2e771e01e076e21:
xilinx: Delete hw/include/xilinx.h (2014-02-26 14:54:45 +1000)
are available in the git repository at:
git://github.com/awilliam/qemu-vfio.git tags/vfio-pci-for-qemu-20140226.0
for you to fetch changes up to 4b9430
On Tue, 2014-02-25 at 18:47 -0500, Bandan Das wrote:
> v4:
> 1. Short Description of the issue in comments, pointer
> to qemu bug tracker in 2/2
> 2. Remove unnecessary check on rom_bar in vfio_pci_size_rom 2/2
> 3. No changes to 1/2 - Andreas, I have retained your "Reviewed-by"
> since the code ha
The ethernet device in the musicpal only has two tx queues,
but we modelled it with four CTDP registers, presumably a
cut and paste from the rx queue registers. Since the tx_queue[]
array is only 2 entries long this allowed a guest to overrun
this buffer. Remove the nonexistent registers.
Signed-o
From: Christoffer Dall
Update to tag v3.14-rc3 (6d0abeca3242a88cab8232e4acd7e2bf088f3bc2)
Signed-off-by: Christoffer Dall
Message-id: 1392687720-26806-2-git-send-email-christoffer.d...@linaro.org
Signed-off-by: Peter Maydell
---
linux-headers/asm-arm/kvm.h | 28 +++
On 24 February 2014 12:05, Gerd Hoffmann wrote:
> Hi,
>
> Pretty short this time, just a single bugfix.
>
> please pull,
> Gerd
>
> The following changes since commit 105a060188dc6fdd4551571a966514d1a5f6815a:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20140220
Implement the WFI instruction for A64; this just involves wiring
up the instruction, and adding a gen_a64_set_pc_im() which was
accidentally omitted from the A64 decoder top loop.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/translate-a64.c | 5 -
1 file change
Implement the AArch64 memory attribute registers. Since QEMU doesn't
model caches it does not need to care about memory attributes at all,
and we can simply make these read-as-written.
We did not previously implement the AArch32 versions of the MAIR
registers, which went unnoticed because of the o
From: Christoffer Dall
The GIC_SET_LEVEL macro unfortunately overwrote the entire level
bitmask instead of just or'ing on the necessary bits, causing active
level PPIs on a core to clear PPIs on other cores.
Cc: qemu-sta...@nongnu.org
Reported-by: Rob Herring
Signed-off-by: Christoffer Dall
Me
On 02/26/2014 10:16 AM, Max Reitz wrote:
>> * "x.y" (i.e., the reverse of what qdict_array_split() does).
>> * This operation is applied recursively for nested QDicts and QLists.
>> */
>>
>> With your new split rules, do we need a followup patch to qdict_flatten
>> that can regenerate the QDi
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)
visible to AArch64. These are mostly simple 64-bit extensions of the
existing 32 bit system registers and so can share reginfo definitions.
CTR needs to have a split definition, but we can clean up the
temporary user-mode implementatio
Implement the AArch64-specific ID and feature registers. Although
many of these are currently not used by the architecture (and so
always zero for all implementations), we define the full set of
fields in the ARMCPU struct for symmetry.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
In AArch64 the breakpoint and watchpoint registers are mandatory, so the
kernel always accesses them on bootup. Implement dummy versions, which
read as written but have no actual effect.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h| 4
target-arm/he
In ARMv5 level 2 page table descriptors, each 4K or 64K page is split into
four subpages, each of which can have different access permission settings,
which are specified by four two-bit fields in the l2 descriptor. A
long-standing cut-and-paste error meant we were using the wrong bits in
the virtu
The integrator's timer read/write functions log an error for
bad addresses in guest accesses, but were falling through and
using an out of bounds array index rather than returning early.
Fix this.
Signed-off-by: Peter Maydell
Reviewed-by: Paolo Bonzini
Reviewed-by: Andreas Färber
Message-id: 13
Implement the AArch64 view of the generic timer system registers.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 6 ++--
target-arm/helper.c | 83 ++---
2 files changed, 75 insertions(+), 14 deletions(-)
diff --git a/target-arm/cpu.h b/ta
Implement all the AArch64 cache invalidate and clean ops
(which are all NOPs since QEMU doesn't emulate the cache).
The only remaining unimplemented cache op is DC ZVA.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.c| 4 ++--
target-arm/helper.c | 47 ++
Fix incorrect use of sizeof() rather than ARRAY_SIZE() to guard
accesses into the mb_clock[] array, which was allowing a malicious
guest to overwrite the end of the array.
Signed-off-by: Peter Maydell
Reviewed-by: Paolo Bonzini
Reviewed-by: Andreas Färber
Message-id: 1392647854-8067-2-git-send-
Implement the AArch64 TLB invalidate operations. This is
the full set of TLBI ops defined for a CPU which doesn't
implement EL2 or EL3.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 73 +
1 file changed, 73 insertions(+)
diff --git a/
Implement the AArch64 MPIDR system register.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9dcdf8e..de70a92 100644
--- a/target-arm/hel
The Exynos4210 combiner has IIC_NIRQ inputs and IIC_NGRP outputs;
use the correct constant in the loop initializing our output
sysbus IRQs so that we don't overrun the output_irq[] array.
Signed-off-by: Peter Maydell
Message-id: 1392659611-8439-1-git-send-email-peter.mayd...@linaro.org
Reviewed-b
From: Peter Crosthwaite
This is the product of the data-width and the depth arguments, I.e the
depth of the FIFO is in terms of data entries and not bytes (which is
what the original implementation was suggesting). Fix.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id:
c
Implement the MSR (immediate) instructions, which can update the
PSTATE SP and DAIF fields.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 25 +
target-arm/translate-a64.c | 25
Define a dummy version of the AArch64 OSLAR_EL1 system register
which just ignores writes. Linux will always write to this (it
is the OS lock used for debugging), but we don't support debug.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 4
1 file cha
From: Will Newton
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8
and add a CPU feature flag to enable these instructions.
The CRC32-C implementation used is the built-in qemu implementation
and The CRC-32 implementation is from zlib. This requires adding zlib
to LIBS to ens
To avoid complication in code that otherwise would not need to
care about whether EL1 is AArch32 or AArch64, we should store
the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF
in AArch64) in one place consistently regardless of EL1's mode.
Since AArch64 has an extra enable bit (D for debu
Implement the A64 view of the VBAR system register.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 9 -
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4e87064..06
Implement the AArch64 TCR_EL1, which is the 64 bit view of
the AArch32 TTBCR. (The uses of the bits in the register are
completely different, but in any given situation the CPU will
always interpret them one way or the other. In fact for QEMU EL1
is always 64 bit, but we share the state field becau
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