Quoting Aurelien Jarno (2013-09-09 12:27:47)
> 32-bit versions of sar and shr ops should not propagate known-zero bits
> from the unused 32 high bits. For sar it could even lead to wrong code
> being generated.
>
> Cc: Richard Henderson
> Cc: Paolo Bonzini
> Cc: qemu-sta...@nongnu.org
> Signed-o
Signed-off-by: Jan Vesely
---
Tested on Ubuntu, Fedora, and HelenOS.
hw/usb/dev-hid.c | 67 +---
1 file changed, 59 insertions(+), 8 deletions(-)
diff --git a/hw/usb/dev-hid.c b/hw/usb/dev-hid.c
index 954cde1..53e7bd3 100644
--- a/hw/usb/dev-h
Signed-off-by: Jan Vesely
---
Tested on Ubuntu, Fedora, and HelenOS.
hw/usb/dev-hid.c | 67 +---
1 file changed, 59 insertions(+), 8 deletions(-)
diff --git a/hw/usb/dev-hid.c b/hw/usb/dev-hid.c
index 2966066..954cde1 100644
--- a/hw/usb/dev-h
We are using Qemu-1.7.0 with Xen-4.3.0 and Debian jessie. We are noticing
that when we transfer large files from our network to the guestOS via the e1000
virtual network device that we experience memory corruption on the guestOS.
We have debugged this problem and have determined where it app
Quoting Frank (2013-09-12 08:51:56)
> It is allocated by g_new0() in inet_parse(), so needs to be freed in
> qemu_rdma_data_init().
>
> From d7a8d1aad11fbe9af389cf9dd6cee14cc3249b1f Mon Sep 17 00:00:00 2001
> From: Frank Yang
> Date: Thu, 12 Sep 2013 21:37:56 +0800
> Subject: [PATCH] rdma: memor
On Sat, Feb 15, 2014 at 03:42:56PM +, Peter Maydell wrote:
> On 13 February 2014 05:07, wrote:
> > From: "Edgar E. Iglesias"
> >
> > cpu->exit_request is part of the execution environment and should
> > not be cleared when a CPU resets.
> >
> > Otherwise, we might deadlock QEMU if a CPU rese
Mike,
On 15 Feb 2014, at 20:33, Mike Day wrote:
>>
>> 2. You have introduced rcu not only to protect active_timers, the list of
>> active timers within one timerlist, but also to protect (I think)
>> the list of timerlists, as evidenced by the fact you have
>> reclaim_timer_list as well as
On 15 February 2014 19:05, Peter Maydell wrote:
> On 15 February 2014 19:01, Michael Tokarev wrote:
>> 15.02.2014 22:53, Peter Maydell wrote:
>>> Incidentally if you have a simple recipe for setting up a windows
>>> mingw build environment on Ubuntu (preferably not bleeding-edge
>>> Ubuntu) then
Alex Bligh writes:
> Some comments:
Thanks for the thorough review!
> 1. You seem to be removing the use of the active_timers_lock and replacing it
> by
>rcu (fine). However, you seem to have left the qemu_mutex_destroy in
>timerlist_free, and left the mutex in QEMUTimerList. Any reason
15.02.2014 23:05, Peter Maydell wrote:
> On 15 February 2014 19:01, Michael Tokarev wrote:
>> BTW, current debian wheezy catches these constants
>> in 32bits too. I mean, when the host is 32bits.
>
> Must be a new-gcc thing, then, maybe? My test 32 bit
> Linux host has gcc-4.6.3-1ubuntu5 and th
On 15 February 2014 19:01, Michael Tokarev wrote:
> 15.02.2014 22:53, Peter Maydell wrote:
>> Incidentally if you have a simple recipe for setting up a windows
>> mingw build environment on Ubuntu (preferably not bleeding-edge
>> Ubuntu) then I'm happy to add "compile-test for win32" to my
>> pull
15.02.2014 22:53, Peter Maydell wrote:
> Incidentally if you have a simple recipe for setting up a windows
> mingw build environment on Ubuntu (preferably not bleeding-edge
> Ubuntu) then I'm happy to add "compile-test for win32" to my
> pullreq application checklist.
Hm. I've never did that befo
On 15 February 2014 18:12, Peter Maydell wrote:
> Ugh, sorry about that. I thought I'd caught them but obviously the Windows
> 32 bit build is pickier than the Linux one (it's clearly right though).
Incidentally if you have a simple recipe for setting up a windows
mingw build environment on Ubunt
On 15 February 2014 17:34, Michael Tokarev wrote:
> Since this commit:
>
> commit 999b53ec8794f203964db3ecf939a3da5c4bc843
> Author: Claudio Fontana
> Date: Wed Feb 5 17:27:28 2014 +
>
> disas: Implement disassembly output for A64
>
> Use libvixl to implement disassembly output in d
13 февраля 2014 г. 16:03:12 GMT+04:00, Antonios Motakis
пишет:
>Extend -mem-path with additional properties:
>
> - prealloc=on|off - default off, same as -mem-prealloc
> - share=on|off - default off, memory is mmapped with MAP_SHARED
Maybe we should combine -m and -mem-path options together to f
Since this commit:
commit 999b53ec8794f203964db3ecf939a3da5c4bc843
Author: Claudio Fontana
Date: Wed Feb 5 17:27:28 2014 +
disas: Implement disassembly output for A64
Use libvixl to implement disassembly output in debug
logs for A64, for use with both AArch64 hosts and targets
Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h
Signed-off-by: Max Filippov
---
target-xtensa/core-dc232b.c | 8 +---
target-xtensa/core-dc233c.c | 8 +---
target-xtensa/c
Signed-off-by: Max Filippov
---
target-xtensa/cpu.c | 2 ++
target-xtensa/cpu.h | 4
target-xtensa/overlay_tool.h | 9 -
target-xtensa/translate.c| 9 +++--
4 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/target-xtensa/cpu.c b/target-xtensa/c
Hello,
this series collapses standard core configuration statements into a single
macro and adds support for two new special registers.
Max Filippov (2):
target-xtensa: refactor standard core configuration
target-xtensa: provide HW confg ID registers
target-xtensa/core-dc232b.c | 8 +-
Here's the latest patchset aimed towards implementing AArch64
system emulation.
Patch 1 is an actually working version of a fix for a problem
I tried to deal with incorrectly in the previous series.
Following patches are implementations of AArch64 views of various
system registers -- these general
If the image file cannot be opened and was created as a temporary file,
it should be deleted; thus, in this case, we should jump to the
"unlink_and_fail" label and not just to "fail".
Reported-by: Benoît Canet
Signed-off-by: Max Reitz
---
This patch's context depends on my bdrv_open()/bdrv_file_
The raw read and write functions were using the ARM_CP_64BIT flag in
ri->type to determine whether to treat the register's state field as
uint32_t or uint64_t; however AArch64 register info structs don't use
that flag. Abstract out the "how big is the field?" test into a
function and fix it to work
Implement the AArch64 view of the system control register SCTLR_EL1.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index
On 15 February 2014 12:18, Michael Tokarev wrote:
> This is a trivial-patches pull request for 2014-02-15.
> Amount of patches this time is small, but some of them deserves some
> explanation.
>
> vl: trim includes -- this one removes many #include statements from vl.c.
> I actually verified t
Add new helpers exception_with_syndrome (for generating an exception
with syndrome information) and exception_uncategorized (for generating
an exception with "Unknown or Uncategorized Reason", which have a syndrome
register value of zero), and use them to generate the correct syndrome
information f
On 14 February 2014 17:29, Stefan Hajnoczi wrote:
> The following changes since commit 0888a29caac6e1b668e498a0ad4d1fea15de012b:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
> (2014-02-13 15:02:04 +)
>
> are available in the git repository at:
>
>
> git://
From: Rob Herring
Add support for v8 page table walks. This supports stage 1 translations
for 4KB, 16KB and 64KB page sizes starting with 0 or 1 level.
Signed-off-by: Rob Herring
[PMM: fix style nits, fold in 16/64K page support patch, use
arm_el_is_aa64() to decide whether to do 64 bit page t
Define a dummy version of the AArch64 OSLAR_EL1 system register
which just ignores writes. Linux will always write to this (it
is the OS lock used for debugging), but we don't support debug.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 4
1 file cha
Implement the CurrentEL sysreg.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h | 3 ++-
target-arm/helper.c| 3 +++
target-arm/translate-a64.c | 7 +++
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/targe
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)
visible to AArch64. These are mostly simple 64-bit extensions of the
existing 32 bit system registers and so can share reginfo definitions.
CTR needs to have a split definition, but we can clean up the
temporary user-mode implementatio
Implement the AArch64 view of the generic timer system registers.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 6 ++--
target-arm/helper.c | 83 ++---
2 files changed, 75 insertions(+), 14 deletions(-)
diff --git a/target-arm/cpu.h b/ta
Implement the AArch64 memory attribute registers. Since QEMU doesn't
model caches it does not need to care about memory attributes at all,
and we can simply make these read-as-written.
We did not previously implement the AArch32 versions of the MAIR
registers, which went unnoticed because of the o
Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --g
Emit the correct MMU index information for loads and stores from
A64 code, rather than hardwiring it to "always kernel mode",
by storing the exception level in the TB flags, and make
cpu_mmu_index() return the right answer when the CPU is in
AArch64 mode.
Signed-off-by: Peter Maydell
---
target-
For AArch32 exceptions, the only information provided about
the cause of an exception is the individual exception type (data
abort, undef, etc), which we store in env->exception_index. For
AArch64, the CPU provides much more detail about the cause of
the exception, which can be found in the syndrom
For exceptions taken to AArch64, if a coprocessor/system register
access fails due to a trap or enable bit then the syndrome information
must include details of the failing instruction (crn/crm/opc1/opc2
fields, etc). Make the decoder construct the syndrome information
at translate time so it can b
Implement the AArch64 TLB invalidate operations. This is
the full set of TLBI ops defined for a CPU which doesn't
implement EL2 or EL3.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 73 +
1 file changed, 73 insertions(+)
diff --git a/
Implement the AArch64 view of the CPACR. The AArch64
CPACR is defined to have a lot of RES0 bits, but since
the architecture defines that RES0 bits may be implemented
as reads-as-written and we know that a v8 CPU will have
no registered coprocessors for cp0..cp13 we can safely
implement the whole r
Implement the AArch64-specific ID and feature registers. Although
many of these are currently not used by the architecture (and so
always zero for all implementations), we define the full set of
fields in the ARMCPU struct for symmetry.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
For the A64 instruction set, the only FP/Neon disable trap
is the CPACR FPEN bits, which may indicate "enabled", "disabled"
or "disabled for EL0". Add a bit to the AArch64 tb flags indicating
whether FP/Neon access is currently enabled and make the decoder
emit code to raise exceptions on use of FP
There are various situations where we need to behave differently
depending on whether a given exception level is in AArch64 or
AArch32 state. The state of the current exception level is stored
in env->aarch64, but there's no equivalent guest-visible architected
state bits for the status of the exce
Implement all the AArch64 cache invalidate and clean ops
(which are all NOPs since QEMU doesn't emulate the cache).
The only remaining unimplemented cache op is DC ZVA.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.c| 4 ++--
target-arm/helper.c | 47 ++
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits
to handle LPAE, but implemented as two separate uint32_t fields.
Combine them into a single uint64_t which can be used for all purposes.
Since this requires touching every use, take the opportunity to rename
the field to the a
In AArch64 the breakpoint and watchpoint registers are mandatory, so the
kernel always accesses them on bootup. Implement dummy versions, which
read as written but have no actual effect.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h| 4
target-arm/he
The current A32/T32 decoder bases its "is VFP/Neon enabled?" check
on the FPSCR.EN bit. This is correct if EL1 is AArch32, but for
an AArch64 EL1 the logic is different: it must act as if FPSCR.EN
is always set. Instead, trapping must happen according to CPACR
bits for cp10/cp11; these cover all of
Implement the A64 view of the VBAR system register.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 9 -
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4e87064..06
Implement the MSR (immediate) instructions, which can update the
PSTATE SP and DAIF fields.
Signed-off-by: Peter Maydell
---
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 25 +
target-arm/translate-a64.c | 25 -
3 files changed,
Implement the AArch64 TCR_EL1, which is the 64 bit view of
the AArch32 TTBCR. (The uses of the bits in the register are
completely different, but in any given situation the CPU will
always interpret them one way or the other. In fact for QEMU EL1
is always 64 bit, but we share the state field becau
Implement the AArch64 MPIDR system register.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f5d9d2f..c81e73f 100644
--- a/target-arm/hel
Because unallocated encodings generate different exception syndrome
information from traps due to FP being disabled, we can't do a single
"is fp access disabled" check at a high level in the decode tree.
To help in catching bugs where the access check was forgotten in some
code path, we set this fl
We don't support letting the guest do debug, but Linux prods the
monitor debug system control register anyway, so implement a dummy
RAZ/WI version.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/targe
To avoid complication in code that otherwise would not need to
care about whether EL1 is AArch32 or AArch64, we should store
the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF
in AArch64) in one place consistently regardless of EL1's mode.
Since AArch64 has an extra enable bit (D for debu
Implement the DAIF system register which is a view of the
DAIF bits in PSTATE.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 24
1 file changed, 24 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 367fbb
Implement the WFI instruction for A64; this just involves wiring
up the instruction, and adding a gen_a64_set_pc_im() which was
accidentally omitted from the A64 decoder top loop.
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-
On 13 February 2014 05:07, wrote:
> From: "Edgar E. Iglesias"
>
> cpu->exit_request is part of the execution environment and should
> not be cleared when a CPU resets.
>
> Otherwise, we might deadlock QEMU if a CPU resets while there is
> I/O going on.
>
> Signed-off-by: Edgar E. Iglesias
> ---
On 13 February 2014 15:30, Luiz Capitulino wrote:
> The following changes since commit 9d74f6fef0801ca2ce5c9d38d59b85bf03c27669:
>
> Merge remote-tracking branch 'remotes/alon/pull-libcacard.glusterfs' into
> staging (2014-02-12 17:53:31 +)
>
> are available in the git repository at:
>
>
>
On 12 February 2014 00:57, Jia Liu wrote:
>
> Hi Anthony,
>
> This is my OpenRISC patch queue for 1.8, it have been well tested, please
> pull.
>
> Thanks to Richard Henderson, he made the LD/ST updated.
Applied, thanks.
-- PMM
On 10 February 2014 16:19, Petar Jovanovic wrote:
> The following changes since commit 1f6b12f75f2c22f861d0202374033a7594c91707:
>
> Merge remote-tracking branch 'remotes/mwalle/tags/lm32-fixes/20140204' into
> staging (2014-02-08 15:57:51 +)
>
> are available in the git repository at:
>
>
On 10 February 2014 18:36, Andreas Färber wrote:
> Hello Peter,
>
> This is my QOM (devices) patch queue. Please pull.
>
> Regards,
> Andreas
>
> Cc: Peter Maydell
> Cc: Anthony Liguori
>
> Cc: Markus Armbruster
> Cc: Alexander Graf
> Cc: Stefan Hajnoczi
> Cc: Paolo Bonzini
>
> The following
Hi，
after testing your patch,the guest will send arp packet when it
configure vlan or alias on the virtio net.
But bridge or bond do not send arp. what's your opinion?
BTW,this feature need modify the driver of virtio net.
Only the newest linux kernel support it. So what's about old guest os?
Public bug reported:
The OS Plan 9 from Bell Labs runs fine in QEMU/KVM for the most part buy
is unable to boot its GUI when emulating a RTL8139 WiFi card. I hear
someone was able to get it working under a Windows XP host but I can't
seem to do it under a Gentoo host. If you have any idea what may
On 13 February 2014 09:16, Sebastian Huber
wrote:
> The GPTIMER uses 32-bit registers. Use a 64-bit operation to get the
> ptimer count, otherwise we end up with a count of 0 for GPTIMER counter
> values of 0x.
> ---
> hw/timer/grlib_gptimer.c |4 ++--
> 1 files changed, 2 insertions
From: Stewart Smith
Most distros package it as libfdt, and mentioning libfdt here makes it
much easier to find the package you're missing.
Signed-off-by: Stewart Smith
Reviewed-by: Stefan Weil
Signed-off-by: Michael Tokarev
---
configure |4 ++--
1 file changed, 2 insertions(+), 2 deleti
Refactor do_socketcall() to do argument conversion/checking first,
according to a lookup table (which call has how many args) and
by calling the right function second with ready-to-go arguments.
This ensures that all arguments are handled as abi_long, according
to socketcall prototype, and simplif
From: Sebastian Huber
A lot of real world LEON3 systems are shipped with the GRMON boot
loader. This boot loader initializes the stack pointer with the end of
RAM address. The application can use this to detect the RAM size of a
particular board variant.
Signed-off-by: Sebastian Huber
Reviewe
Over time, lots of stuff moved from vl.c into separate
files. But include statements has never been cleaned,
and they continue to carry lots of anymore-unused stuff.
Remove includes which are not relevant for vl.c anymore.
Apparently there are more includes like this, because
many are included fr
by default, patterns/names in .gitignore are applied
recursively to all subdirectories. So any name mentioned
in .gitignore is ignored in all subdirectores. This is good
for, say. object files (*.o), but not good for particular
names which should be ignored only in one directory. For
example, qe
The checksum calculation header exports a function that refers to
struct iov defined in iov.h. Without including the former, build
fails like this:
In file included from hw/net/fsl_etsec/rings.c:24:0:
include/net/checksum.h:51:31: error: ‘struct iovec’ declared inside parameter
list [-Werror
Signed-off-by: Michael Tokarev
---
vl.c |3 ---
1 file changed, 3 deletions(-)
diff --git a/vl.c b/vl.c
index a7b00cd..a7c3f8e 100644
--- a/vl.c
+++ b/vl.c
@@ -172,9 +172,6 @@ int main(int argc, char **argv)
#include "qapi/string-input-visitor.h"
#include "qom/object_interfaces.h"
-//#de
From: Stewart Smith
Modify feature_not_found to accept an optional second parameter to be
printed after the generic feature not found error.
Modify most calls to feature_not_found to provide hints as to the
packages that may be missing. The few calls remaining without a remedy
are ones I couldn'
From: Peter Crosthwaite
This was guarding against a full fifo rather than an empty fifo when
popping. Fix.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Martin Kletzander
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Michael Tokarev
---
hw/char/serial.c |2 +-
1 file changed, 1 ins
Thanks, applied to the trivial patches queue.
/mjt
13.02.2014 13:16, Sebastian Huber wrote:
> The GPTIMER uses 32-bit registers. Use a 64-bit operation to get the
> ptimer count, otherwise we end up with a count of 0 for GPTIMER counter
> values of 0x.
Signed-off-by?
Thanks,
/mjt
This is a trivial-patches pull request for 2014-02-15.
Amount of patches this time is small, but some of them deserves some
explanation.
vl: trim includes -- this one removes many #include statements from vl.c.
I actually verified that qemu builds fine on linux and several variants
of *BSD w
From: Stefan Weil
Signed-off-by: Stefan Weil
Reviewed-by: Laszlo Ersek
Reviewed-by: Andreas Färber
Signed-off-by: Michael Tokarev
---
scripts/switch-timer-api |2 +-
tests/i440fx-test.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/scripts/switch-timer-ap
On Fri, 14 Feb 2014 15:42:49 +0100
Alexander Graf wrote:
> [...]
> >> -M mac99 also fails miserably. It almost looks as if the mask cuts off
> >> some bits, but please investigate this yourself. I'll remove the patch
> >> from the queue meanwhile.
> >
> > Sigh, this whole series is just way too b
Mike,
Some comments:
1. You seem to be removing the use of the active_timers_lock and replacing it by
rcu (fine). However, you seem to have left the qemu_mutex_destroy in
timerlist_free, and left the mutex in QEMUTimerList. Any reason why we need
both?
2. You have introduced rcu not onl
Jeff Cody writes:
> On Fri, Feb 14, 2014 at 05:45:40PM +0100, Kevin Wolf wrote:
>> Am 11.02.2014 um 18:03 hat Paolo Bonzini geschrieben:
>> > Signed-off-by: Paolo Bonzini
>> > ---
>> > block/cow.c | 12 +++-
>> > 1 file changed, 3 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/bl
On 02/05/2014 07:44 AM, Chen Gang wrote:
> On 02/05/2014 12:18 AM, Aneesh Kumar K.V wrote:
>>
>> That is a bug. The snprintf usage with PATH_MAX is to prevent buffer
>> overflow and not to truncate. I guess we should fix path handling
>> and propagate error correctly.
>>
>> -aneesh
>>
>
> OK, tha
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