On Di, 2014-01-21 at 14:26 +0100, Markus Armbruster wrote:
> > +/* zero-length string, skip to avoid bogous end marker
> */ \
>
> s/bogous/bogus/
Applied spell fix and pushed.
cheers,
Gerd
In the function mirror_iteration() -> qemu_iovec_init(),
it allocates memory for op->qiov.iov, when the write request calls back,
but in the function mirror_iteration_done(), it only frees the op,
not free the op->qiov.iov, so this causes memory leak.
Signed-off-by: Zhang Min
---
block/mirror.c
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night. Christoffer, really appreciate
your time! We did not really reach agreement
during the chat and Christoffer asked me to follow
up on this thread.
Here it goes. Sorry, it is very long email.
I don't believe we can assi
On 21 January 2014 22:41, Alexander Graf wrote:
>
>
>> Am 22.01.2014 um 07:31 schrieb Anup Patel :
>>
>> On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
>> wrote:
>>> Hi Guys,
>>>
>>> Christoffer and I had a bit heated chat :) on this
>>> subject last night. Christoffer, really appreciate
>>> y
On 01/22/2014 04:20 PM, Alexey Kardashevskiy wrote:
> The existing load_elf() just returns -1 if it fails to load ELF. However
> it could be smarter than this and tell more about the failure such as
> wrong endianness or incompatible platform.
>
> This adds additional return codes for wrong archit
When cluster size is big enough it can lead offset overflow
in qcow2_alloc_clusters_at(). This patch fixes it.
The allocation each time is stopped at L2 table boundary
(see handle_alloc()), so the possible maximum bytes could be
2^(cluster_bits - 3 + cluster_bits)
so int is safe for cluster_bi
This series fixes several bugs of qcow2 when doing preallocation with a
cluster_size larger than the default value.
Hu Tao (4):
qcow2: remove n_start and n_end of qcow2_alloc_cluster_offset()
qcow2: fix offset overflow in qcow2_alloc_clusters_at()
qcow2: check for NULL l2meta
qemu-iotests:
Signed-off-by: Hu Tao
---
Note: the current largest test case number is 074, but Kevin suggested picking
079 as there are in-flight patches taken lower numbers.
tests/qemu-iotests/079 | 69 ++
tests/qemu-iotests/079.out | 32 +
In case of do preallocating metadata with a large cluster size,
qcow2_alloc_cluster_offset() can allocate nothing and returns
a NULL l2meta. This patch checks for it and link2 l2 with only
valid l2meta.
Replace 9 and 512 with BDRV_SECTOR_BITS, BDRV_SECTOR_SIZE
respectively while at the function.
n_start can be actually calculated from offset. The number of
sectors to be allocated(n_end - n_start) can be passed in in
num. By removing n_start and n_end, we can save two parameters.
The side effect is there is a bug in qcow2.c:preallocate() that
passes incorrect n_start to qcow2_alloc_cluster
Hi,Fam
I am very sorry for this patch,because I use Outlook to send this email.
Later on, I will submit the patch by git send-email again.
On 2014/1/22 11:41, Fam Zheng wrote:
> Hi,
>
> The patch itself looks good to me, but it has too many extra empty lines
> interleaved. Please try to use "git
My fault. Forgot const static. :-)
On 01/22/2014 02:13 PM, Richard Henderson wrote:
On 01/21/2014 08:59 PM, Xbing Wang wrote:
Making them static makes this function NOT thread-safe
Huh? Why in the world would you say that? They're read-only.
r~
> Am 22.01.2014 um 07:31 schrieb Anup Patel :
>
> On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
> wrote:
>> Hi Guys,
>>
>> Christoffer and I had a bit heated chat :) on this
>> subject last night. Christoffer, really appreciate
>> your time! We did not really reach agreement
>> during the
On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
wrote:
> Hi Guys,
>
> Christoffer and I had a bit heated chat :) on this
> subject last night. Christoffer, really appreciate
> your time! We did not really reach agreement
> during the chat and Christoffer asked me to follow
> up on this thread.
>
On 01/21/2014 08:59 PM, Xbing Wang wrote:
> Making them static makes this function NOT thread-safe
Huh? Why in the world would you say that? They're read-only.
r~
This flag will be used to decide whether to emulate some bits of
H_SET_MODE hypercall because some are POWER8-only.
While we are here, add 2.05 flag to POWER8 family too. POWER7/7+ already
has it.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/cpu.h| 2 ++
target-ppc/translate_i
Luiz, do you think this series is good enough?
ping?
On 01/21/2014 02:58 PM, Gonglei (Arei) wrote:
-Original Message-
From: Orit Wasserman [mailto:owass...@redhat.com]
Sent: Tuesday, January 21, 2014 8:24 PM
To: Gonglei (Arei); qemu-devel@nongnu.org; qemu-sta...@nongnu.org; Peter
Maydell; anth...@codemonkey.ws; pbonz...@redhat.com
Cc: che
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr_hcall.c | 26 ++
target-ppc/cpu.h | 2 ++
2 files changed, 28 insertions(+)
diff --git a/hw/ppc/spa
This changes resource code definitions to ones used in the host kernel.
This fixes H_SET_MODE_RESOURCE_LE (switch between big endian and
little endian) to sync registers from KVM before changing LPCR value.
This adds a set_spr() helper to update an SPR in a CPU's context to avoid
possible races a
This fixes H_SET_MODE.
Alexey Kardashevskiy (3):
target-ppc: introduce powerisa-207-server flag
spapr-hcall: fix little-endian resource handling in H_SET_MODE
spapr-hcall: add address-translation-mode-on-interrupt resource in
H_SET_MODE
hw/ppc/spapr_hcall.c| 64
These patches are version 3 to enalbe Intel MPX for KVM.
Version 1:
* Add some Intel MPX definiation
* Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features enable/disable
* vmx and msr handle for MPX support at KVM
* enalbe MPX feature for guest
Version 2:
* remove generic MPX
At the moment in the case of error, load_elf() returns -1 so load_kernel()
will not signal error at all.
Signed-off-by: Alexey Kardashevskiy
---
hw/moxie/moxiesim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c
index ef4f3a8..a87ca6
This makes use of new error codes which load_elf() can return.
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 851ce4b..18a4872 100644
--- a/hw/ppc/spapr.c
+++ b/hw
The first 2 patches are real fixes, the last two are for discussion
not sure we really need them). Thanks.
Alexey Kardashevskiy (4):
spapr: support only ELF kernel images
moxie: fix load_elf() usage
elf-loader: add more return codes
spapr: add more details error description of why load_e
The existing load_elf() just returns -1 if it fails to load ELF. However
it could be smarter than this and tell more about the failure such as
wrong endianness or incompatible platform.
This adds additional return codes for wrong architecture, wrong
endianness and if the image is not ELF at all.
Currently everybody uses ELF kernel images with "-kernel" option on
pseries machine but QEMU still tries to boot from an image even it
fails to recognize it is ELF. This produces undefined behaviour if
the user tries a kernel image compiled for another architecture.
This removes support of raw ker
Making them static makes this function NOT thread-safe (and they're
hidden in thousands of lines of codes), there will be boys who want the
whole file translate-a64.c to be thread-safe. What do you think?
Thanks.
- xbing
On 01/22/2014 03:53 AM, Peter Maydell wrote:
On 21 January 2014 19:37, R
Yes, I ignore this point. Thanks!
Jinsong
Paolo Bonzini wrote:
> The original patch from Liu Jinsong restricted them to reset or full
> state updates, but that's unnecessary (and wrong) since the BNDCFGS
> MSR has no side effects.
>
> Cc: Liu Jinsong
> Signed-off-by: Paolo Bonzini
> ---
> ta
On Wed, Jan 22, 2014 at 09:54:26AM +0800, Fam Zheng wrote:
> On Tue, 01/21 11:31, Jeff Cody wrote:
> > If the top image to commit is the active layer, and also larger than
> > the base image, then an I/O error will likely be returned during
> > block-commit.
> >
> > For instance, if we have a base
On 01/10/2014 07:20 PM, Alexey Kardashevskiy wrote:
> On 12/20/2013 12:16 AM, Alexey Kardashevskiy wrote:
>> On 12/10/2013 07:16 PM, Alexey Kardashevskiy wrote:
>>> On 12/03/2013 02:30 PM, Alexey Kardashevskiy wrote:
Hi!
This is some cleanup. Please, comment. Thanks!
>>>
>>>
>>> Ping
On 12/11/2013 09:22 PM, Alexey Kardashevskiy wrote:
> With the great help from Paolo, I am presenting yet another try of bootindex
> support on sPAPR, this time with some QOM fixes. Details are in the commit
> messages.
> Please, comment. Thanks.
>
> Alexey Kardashevskiy (5):
> boot: extend get
On Tue, Jan 21, 2014 at 12:04:47PM +0100, Kevin Wolf wrote:
> Am 21.01.2014 um 07:02 hat Hu Tao geschrieben:
> > On Tue, Jan 21, 2014 at 11:33:18AM +0800, Hu Tao wrote:
> > > On Mon, Jan 20, 2014 at 04:17:16PM +0100, Kevin Wolf wrote:
> > > > Am 20.01.2014 um 04:04 hat Hu Tao geschrieben:
> > > > >
Hi,
The patch itself looks good to me, but it has too many extra empty lines
interleaved. Please try to use "git send-email" to submit your patches, for
more information, follow the instructions as in:
http://wiki.qemu.org/Contribute/SubmitAPatch
On Tue, 01/21 11:43, Chentao (Boby) wrote:
> In t
Currently there is no way to query BlockStats of the backing chain. This
adds "backing" and "file" fields into BlockStats to make it possible.
The old optional field "parent", which has the information for "file",
is kept there for backward compatibility, as an alias for "file".
However field name
On Tue, Jan 21, 2014 at 08:12:14PM +, Peter Maydell wrote:
> Implement the MSR (immediate) instructions, which can update the
> PSTATE SP and DAIF fields.
> ---
> target-arm/cpu.h | 1 +
> target-arm/helper.h| 2 ++
> target-arm/op_helper.c | 25
On Tue, Jan 21, 2014 at 08:12:12PM +, Peter Maydell wrote:
> System mode store-exclusive use a different code path to usermode ones;
> implement this missing code, in a similar way to the 32 bit version.
>
> Signed-off-by: Peter Maydell
> ---
> target-arm/translate-a64.c | 68
>
On Tue, 01/21 11:31, Jeff Cody wrote:
> This updates the documentation for commiting snapshot images.
> Specifically, this highlights what happens when the base image
> is either smaller or larger than the snapshot image being committed.
>
> In the case of the base image being smaller, it is resiz
On Tue, 01/21 11:31, Jeff Cody wrote:
> Currently, if an image file is logically larger than its backing file,
> commiting it via 'qemu-img commit' will fail.
>
> For instance, if we have a base image with a virtual size 10G, and a
> snapshot image of size 20G, then committing the snapshot offline
On Tue, 01/21 11:31, Jeff Cody wrote:
> If the top image to commit is the active layer, and also larger than
> the base image, then an I/O error will likely be returned during
> block-commit.
>
> For instance, if we have a base image with a virtual size 10G, and a
> active layer image of size 20G,
On 01/21/2014 06:14 PM, Laszlo Ersek wrote:
it's in my review queue. The last version took a lot of energy on my
part to review (it's long and complex) so I'm still "gearing up".
I very much hope I can review this version by diffing it with the last
version, and checking the differences against
On 12/20/2013 10:36 AM, Alexey Kardashevskiy wrote:
> On 12/04/2013 01:09 PM, Alexey Kardashevskiy wrote:
>> On 12/03/2013 10:09 PM, Igor Mammedov wrote:
>>> On Tue, 3 Dec 2013 14:42:48 +1100
>>> Alexey Kardashevskiy wrote:
>>>
This adds suboptions support for -cpu. This keeps @cpu_model in
I have worked through this some more and have found some issues that I
have fixed in V3, which is now on the list
On Mon, Jan 20, 2014 at 11:11 AM, Alistair Francis
wrote:
> This patch implements the ARM PMCCNTR register including
> the disable and reset components of the PMCR register.
>
> Signe
This patch implements the ARM PMCCNTR register including
the disable and reset components of the PMCR register.
Signed-off-by: Alistair Francis
---
This patch assumes that non-invasive debugging is not permitted
when determining if the counter is disabled
V3: Fixed up incorrect reset, disable and
On 01/17/2014 10:44 AM, Peter Maydell wrote:
> +/* Common SHL/SLI - Shift left with an optional insert */
> +static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
> + bool insert, int shift)
> +{
> +tcg_gen_shli_i64(tcg_src, tcg_src, shift);
> +
On 01/17/2014 10:44 AM, Peter Maydell wrote:
> Alex Bennée (2):
> target-arm: A64: Add logic ops from SIMD 3 same group
> target-arm: A64: Add SIMD shift by immediate
>
> Peter Maydell (6):
> target-arm: A64: Add SIMD three-different multiply accumulate insns
> target-arm: A64: Add SIMD th
Implement the AArch64 memory attribute registers. Since QEMU doesn't
model caches it does not need to care about memory attributes at all,
and we can simply make these read-as-written.
We did not previously implement the AArch32 versions of the MAIR
registers, which went unnoticed because of the o
This is a chunk of patches which make a start on the AArch64
system emulation. Specifically, most of them are providing
AArch64 system registers used by Linux as it boots. There
are also a few patches adding extra instruction support, like
the system mode store-exclusives and MSR-immediate.
This t
In AArch64 the breakpoint and watchpoint registers are mandatory, so the
kernel always accesses them on bootup. Implement dummy versions, which
read as written but have no actual effect.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 4
target-arm/helper.c | 32
On Tue, 2014-01-21 at 11:21 +0100, Paolo Bonzini wrote:
> Il 21/01/2014 09:02, Vadim Rozenfeld ha scritto:
> > From: Vadim Rozenfeld
> >
> > Signed-off-by: Vadim Rozenfeld
> > ---
> > linux-headers/asm-x86/hyperv.h | 3 +++
> > linux-headers/linux/kvm.h | 1 +
> > target-i386/cpu-qom.h
On Sat, Jan 18, 2014 at 09:19:43AM -0800, rajan pathak wrote:
> I am looking forward to emulate single-chip Ethernet controller.
>
> I can find some of its source code online and it has two main part Ethernet
> PHY (any 1GB SGMII compatible)
> and Ethernet MAC .
>
> So ,DO I need to simply put th
Implement the AArch64 view of the system control register SCTLR_EL1.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c8b6cdb..16f1d27 100644
--- a/ta
Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/helper.c b/targe
System mode store-exclusive use a different code path to usermode ones;
implement this missing code, in a similar way to the 32 bit version.
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 68 ++
1 file changed, 62 insertions(+), 6 deleti
Implement the AArch64 MPIDR system register.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1f1dec1..ef74d10 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
Implement the AArch64 TLB invalidate operations. This is
the full set of TLBI ops defined for a CPU which doesn't
implement EL2 or EL3.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 76 +
1 file changed, 76 insertions(+)
diff --git a/
Make the cache ID system registers (CLIDR, CCSELR, CCSIDR, CTR)
visible to AArch64. These are mostly simple 64-bit extensions of the
existing 32 bit system registers and so can share reginfo definitions.
CTR needs to have a split definition, but we can clean up the
temporary user-mode implementatio
The SCTLR is full of bits for enabling or disabling various things, and so
there are many places in the code which check if certain bits are set.
Define some named constants for the SCTLR bits so these checks are easier
to read.
Signed-off-by: Peter Maydell
---
target-arm/cpu.c| 2 +-
targe
Implement the AArch64-specific ID and feature registers. Although
many of these are currently not used by the architecture (and so
always zero for all implementations), we define the full set of
fields in the ARMCPU struct for symmetry.
Signed-off-by: Peter Maydell
---
target-arm/cpu-qom.h | 10
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits
to handle LPAE, but implemented as two separate uint32_t fields.
Combine them into a single uint64_t which can be used for all purposes.
Since this requires touching every use, take the opportunity to rename
the field to the a
Log guest attempts to access unimplemented system registers via
the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
instruction sets). This is particularly useful for debugging
problems where the guest is trying to use a system register that
QEMU doesn't implement.
Signed-off-by: Pet
Define a dummy version of the AArch64 OSLAR_EL1 system register
which just ignores writes. Linux will always write to this (it
is the OS lock used for debugging), but we don't support debug.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 4
1 file changed, 4 insertions(+)
diff --gi
Implement the AArch64 TCR_EL1, which is the 64 bit view of
the AArch32 TTBCR. (The uses of the bits in the register are
completely different, but in any given situation the CPU will
always interpret them one way or the other. In fact for QEMU EL1
is always 64 bit, but we share the state field becau
We already implicitly rely on the exception level being
part of the TB flags for coprocessor access, so actually
include it. (This makes no difference for linux-user mode,
which is always in EL0, but will be needed for correct
operation in system emulation.)
Signed-off-by: Peter Maydell
---
targ
Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_*
constant to include all the ones currently supported by the kernel
headers we are using.
Signed-off-by: Peter Maydell
---
target-arm/kvm-consts.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git
Implement the AArch64 view of the generic timer system registers.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 6 +--
target-arm/helper.c | 115
2 files changed, 111 insertions(+), 10 deletions(-)
diff --git a/target-arm/cpu.h b/t
Implement the MSR (immediate) instructions, which can update the
PSTATE SP and DAIF fields.
---
target-arm/cpu.h | 1 +
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 25 +
target-arm/translate-a64.c | 24 +++-
4 files change
Implement the CurrentEL sysreg.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h | 3 ++-
target-arm/helper.c| 3 +++
target-arm/translate-a64.c | 7 +++
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1dce28b..2e04a
We don't support letting the guest do debug, but Linux prods the
monitor debug system control register anyway, so implement a dummy
RAZ/WI version.
---
target-arm/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ffe245f..69cce6f 100
Implement the A64 view of the VBAR system register.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 9 -
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a7d6274..6f4d174 100644
--- a/target-arm/cp
Implement the DAIF system register which is a view of the
DAIF bits in PSTATE.
TODO: include support for the MSR_i encodings?
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/help
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.
In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard
the use of them in check_ap() so that we don't get incorrect results
for ARMv8 CPUs.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 3 +++
1 file changed, 3
Implement all the AArch64 cache invalidate and clean ops
(which are all NOPs since QEMU doesn't emulate the cache).
The only remaining unimplemented cache op is DC ZVA.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 47 +++
1 file changed, 47 i
On 21 January 2014 19:37, Richard Henderson wrote:
> On 01/17/2014 10:44 AM, Peter Maydell wrote:
>> +NeonGenFn *ceqtstfns[3][2] = {
>
> You want all of these arrays to be static and const:
>
> static NeonGenFn * const ceqtstfns[3][2] = ...
I confess I couldn't figure out the ri
On Tue, Jan 21, 2014 at 01:24:02PM +0100, Gerd Hoffmann wrote:
> qemu may pass us zero-length strings for smbios fields, when starting
> qemu this way ...
>
> qemu -smbios type=1,version=,serial=test
>
> ... for example.
>
> Today we don't specifically handle them and simply append them t
On 01/17/2014 10:44 AM, Peter Maydell wrote:
> +switch (opcode) {
> +case 0x6: /* CMGT, CMHI */
> +{
> +NeonGenFn *ceqtstfns[3][2] = {
...
> +case 0x7: /* CMGE, CMHS */
> +{
> +NeonGenFn *ceqtstfns[3][2] = {
On 01/17/2014 10:44 AM, Peter Maydell wrote:
> +NeonGenFn *ceqtstfns[3][2] = {
You want all of these arrays to be static and const:
static NeonGenFn * const ceqtstfns[3][2] = ...
r~
On 01/17/2014 10:44 AM, Peter Maydell wrote:
> +/* AND, BIC, ORR, ORN */
> +if (extract32(size, 0, 1)) {
> +tcg_gen_not_i64(tcg_op2, tcg_op2);
> +}
> +if (extract32(size, 1, 1)) {
> +tcg_gen_or_i64(tcg_res[pass], tcg_op
On 01/17/2014 10:44 AM, Peter Maydell wrote:
> + * We implement this using setcond (!test) and subtracting 1.
FWIW -(test) is more space efficient for x86 host. I doubt there's any
space or speed impact either way for any other host.
r~
>From 31e68d752ac395dc6b65e6adf45be5324e92cdc8 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Fri, 13 Dec 2013 02:32:43 +0800
Subject: [PATCH v3 2/4] KVM/X86: Intel MPX vmx and msr handle
This patch handle vmx and msr of Intel MPX feature.
Signed-off-by: Xudong Hao
Signed-off-by: Liu Jinsong
>From c2b3b4347b4c8b0aa6b5e97c161fd4d34b0ef4d3 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Fri, 13 Dec 2013 02:34:48 +0800
Subject: [PATCH v3 4/4] KVM/X86: Enable Intel MPX for guest.
This patch enable Intel MPX feature to guest.
Signed-off-by: Xudong Hao
Signed-off-by: Liu Jinsong
---
a
>From d1992769911f34cb319fe638d32ae604bd2a6ce8 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Fri, 13 Dec 2013 02:33:08 +0800
Subject: [PATCH v3 3/4] KVM/X86: add MSR_IA32_BNDCFGS to msrs_to_save
Add MSR_IA32_BNDCFGS to msrs_to_save, and corresponding logic
to kvm_get/set_msr().
Signed-off-by:
>From 3155a190ce6ebb213e6c724240f4e6620ba67a9d Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Fri, 13 Dec 2013 02:32:03 +0800
Subject: [PATCH v3 1/4] KVM/X86: Fix xsave cpuid exposing bug
EBX of cpuid(0xD, 0) is dynamic per XCR0 features enable/disable.
Bit 63 of XCR0 is reserved for future exp
Apple hardware invariably adds "IRQNoFlags() {0, 8}" to HPET._CRS,
and, at least on piix+smp, an OS X guest will panic unless IRQNoFlags
is present. On the other hand, Windows XP bluescreens whenever
IRQNoFlags is present. This patch conditionally includes IRQNoFlags
only when detecting the presenc
18.01.2014 17:47, Martin Husemann wrote:
> Do not rely on int8_t (and friends) not being preprocessor
> symbols (or symbols expanding to themselves). On NetBSD (for example) the
> glue(u, SDATA_TYPE) results in u__int8_t, which is undefined. There is no way
> to stop cpp expanding inner macros,
On Tue, Jan 21, 2014 at 01:11:01PM -0500, Gabriel L. Somlo wrote:
> Apple hardware invariably adds "IRQNoFlags() {0, 8}" to HPET._CRS,
> and, at least on piix+smp, an OS X guest will panic unless IRQNoFlags
> is present. On the other hand, Windows XP bluescreens whenever
> IRQNoFlags is present. Th
On Tue, Jan 07, 2014 at 02:32:38PM +0100, Paolo Bonzini wrote:
> Il 07/01/2014 13:34, Wei Liu ha scritto:
> > On Mon, Jan 06, 2014 at 09:53:37PM +0100, Paolo Bonzini wrote:
> >> Il 06/01/2014 19:00, Andreas Färber ha scritto:
> >>> Am 06.01.2014 16:39, schrieb Anthony Liguori:
> We already hav
Paolo Bonzini wrote:
> Il 21/01/2014 16:25, Liu, Jinsong ha scritto:
>> Hmm? I remember I have sent out the rebased patches v3 last month
>> If you didn't receive them I'm OK to rebase and resend them. BTW,
>> what's the review remarks? I remember you commented that the patches
>> are fine. Any mis
On 01/21/14 18:11, Radim Krčmář wrote:
> KVM introduced internal error exit reason and suberror at the same time,
> and later extended it with internal error data.
> QEMU does not report suberror on hosts between these two events because
> we check for the extension. (half a year in 2009, but it is
It was muted in the previous commit 4bc74be9. Let's revive it since nothing
prevents us to do it.
With this patch, following command will work as other formats:
$ qemu-img map sheepdog:image
Cc: qemu-devel@nongnu.org
Cc: Kevin Wolf
Cc: Stefan Hajnoczi
Signed-off-by: Liu Yuan
---
block/sheepd
KVM introduced internal error exit reason and suberror at the same time,
and later extended it with internal error data.
QEMU does not report suberror on hosts between these two events because
we check for the extension. (half a year in 2009, but it is misleading)
Fix by removing KVM_CAP_INTERNAL_
On 01/21/2014 09:31 AM, Jeff Cody wrote:
> If the top image to commit is the active layer, and also larger than
> the base image, then an I/O error will likely be returned during
> block-commit.
>
> For instance, if we have a base image with a virtual size 10G, and a
> active layer image of size 2
If the top image to commit is the active layer, and also larger than
the base image, then an I/O error will likely be returned during
block-commit.
For instance, if we have a base image with a virtual size 10G, and a
active layer image of size 20G, then committing the snapshot via
'block-commit' w
Scenario:
- There is a non multifunction pci device A on 00:0X.0.
- Hot-plug another multifunction pci device B at 00:0X.1.
- The operation will fail of course.
- Try to hot-plug the B device 2-3 more times, qemu will crash.
Reason: The error flow leaves the B's address space into global a
On 01/21/2014 09:31 AM, Jeff Cody wrote:
> Currently, if an image file is logically larger than its backing file,
> commiting it via 'qemu-img commit' will fail.
s/commiting/committing/
>
> For instance, if we have a base image with a virtual size 10G, and a
> snapshot image of size 20G, then co
Il 21/01/2014 16:25, Liu, Jinsong ha scritto:
Hmm? I remember I have sent out the rebased patches v3 last month
If you didn't receive them I'm OK to rebase and resend them. BTW, what's
the review remarks? I remember you commented that the patches are fine.
Any misunderstanding please point out to
On 01/19/2014 07:53 AM, Alexander Graf wrote:
> We have cache pools of temporaries that we can reuse later when they've
> already been allocated before.
>
> These cache pools differenciate between the target TCG variable type they
> contain. So we have one pool for I32 and one pool for I64 variabl
On 01/21/2014 09:31 AM, Jeff Cody wrote:
> This updates the documentation for commiting snapshot images.
> Specifically, this highlights what happens when the base image
> is either smaller or larger than the snapshot image being committed.
>
> In the case of the base image being smaller, it is re
Am 21.01.2014 um 17:17 hat Eric Blake geschrieben:
> On 01/21/2014 09:14 AM, Jeff Cody wrote:
> > Important note: this patch should only be applied after patch
> > "block: do not allow read-only=on and snapshot=on to be used together"
> >
> > Now that 'read-only=on' and 'snapshot=on' are not allo
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