Hi Steven,
--disable-stack-protector would also be useful for platforms which make
debugging of executables with stack protection difficult. When I must
debug Windows executables, I always disable stack protection, because
otherwise the stack back traces are unreadable.
So, for MinGW it might be
On Tue, Jan 7, 2014 at 1:19 AM, Peter Maydell wrote:
> On 11 December 2013 13:56, Michel Pollet wrote:
>> Prototype driver for the mxs/imx23 uart IO block. This has no
>> real 'uart' functional code, apart from letting itself be
>> initialized by linux without generating a timeout error.
>>
>> Si
On 10 January 2014 21:51, Gabriel L. Somlo wrote:
> Signed-off-by: Gabriel Somlo
> ---
> Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Makefile b/Makefile
> index bdff4e4..807054b 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -290,7 +290,7 @@ common de-ch es
On 10 January 2014 19:05, Richard Henderson wrote:
> On 01/10/2014 09:12 AM, Peter Maydell wrote:
>> static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
>> {
>> /* Note that this is called with all non-FP cases from
>> * table C3-6 so it must UNDEF for entries not specifi
This wires up a spice port event on virtio-ports open/close, so the
client is notified when the other end is ready.
Signed-off-by: Marc-André Lureau
---
spice-qemu-char.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/spice-qemu-char.c b/spice-qemu
On Mon, Jan 6, 2014 at 4:12 PM, Stefan Hajnoczi wrote:
> On Mon, Jan 06, 2014 at 01:46:54PM +1000, Peter Crosthwaite wrote:
>> On Mon, Jan 6, 2014 at 1:27 PM, Stefan Hajnoczi wrote:
>> > On Thu, Jan 02, 2014 at 08:25:10PM +1000, Peter Crosthwaite wrote:
>> >> Hi Beniamino,
>> >>
>> >> On Thu, Jan
Am 10.01.2014 04:09, schrieb Wenchao Xia:
> 于 2014/1/10 0:25, Peter Lieven 写道:
>> Am 09.01.2014 09:29, schrieb Wenchao Xia:
>>> 于 2014/1/8 17:08, Peter Lieven 写道:
Signed-off-by: Peter Lieven
---
ui/vnc.c |9 +
1 file changed, 9 insertions(+)
diff --gi
On Sat, Jan 11, 2014 at 7:48 AM, Beniamino Galvani wrote:
> On Mon, Jan 06, 2014 at 02:12:27PM +0800, Stefan Hajnoczi wrote:
>> > >> More a comment for net in general, but I think sooner or later we need
>> > >> to move towards a split between phy and mac on the device level.
>> > >> continuing th
Signed-off-by: Gabriel Somlo
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index bdff4e4..807054b 100644
--- a/Makefile
+++ b/Makefile
@@ -290,7 +290,7 @@ common de-ch es fo fr-ca hu ja mk nl-be
pt sl tr \
bepocz
On Mon, Jan 06, 2014 at 02:12:27PM +0800, Stefan Hajnoczi wrote:
> > >> More a comment for net in general, but I think sooner or later we need
> > >> to move towards a split between phy and mac on the device level.
> > >> continuing the phy-within-mac philosophy is going to make the
> > >> socifica
On 01/10/2014 11:08 AM, Tom Musta wrote:
> This patch adds the non-signalling scalar conversion instructions:
>
> - VSX Scalar Convert Single Precision to Double Precision
> Non-Signalling (xscvspdpn)
> - VSX Scalar Convert Double Precision to Single Precision
> Non-Signalling (xscvdps
On 01/10/2014 11:08 AM, Tom Musta wrote:
> This patch adds the VSX Scalar Round to Single Precision (xsrsp)
> instruction.
>
> Signed-off-by: Tom Musta
> ---
> V6: New.
>
> target-ppc/fpu_helper.c | 17 +
> target-ppc/helper.h |1 +
> target-ppc/translate.c |2 ++
On 01/10/2014 11:08 AM, Tom Musta wrote:
> +static void gen_fmrgow(DisasContext *ctx)
> +{
> +TCGv_i64 a1;
> +if (unlikely(!ctx->fpu_enabled)) {
> +gen_exception(ctx, POWERPC_EXCP_FPU);
> +return;
> +}
> +a1 = tcg_temp_new_i64();
> +tcg_gen_shli_i64(a1, cpu_fpr[r
On 01/10/2014 11:07 AM, Tom Musta wrote:
> +#define MV_VSR(name, tcgop1, tcgop2, target, source)\
> +static void gen_##name(DisasContext *ctx) \
> +{ \
> +if (xS(ctx->opcode) < 32) {
On Fri, Jan 10, 2014 at 7:02 PM, Peter Maydell wrote:
> On 10 January 2014 08:47, Peter Crosthwaite
> wrote:
>> I'm trying to apply a QOMification change pattern to NAND and I notice
>> that OMAP gpmc has NAND support. However no one is using it - there
>> are no calls to the omap_gpmc_attach_nan
Am 10.01.2014 21:20, schrieb Peter Crosthwaite:
> On Sat, Jan 11, 2014 at 4:11 AM, Peter Maydell
> wrote:
>> On 2 January 2014 07:31, Peter Crosthwaite
>> wrote:
>>> The SLCR needs to be able to reset the CPUs, so link the CPUs to the
>>> SLCR.
>>
>>> @@ -496,10 +500,17 @@ static const MemoryRe
Parity should be set for a zero result.
Signed-off-by: Richard Henderson
---
target-i386/cc_helper.c | 2 +-
target-i386/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-i386/cc_helper.c b/target-i386/cc_helper.c
index ee04092..05dd12b 100644
--- a/target
This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.
The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V2: Updated conversion to single
On 11/28/13 17:03, Laszlo Ersek wrote:
> Mike,
>
> On 11/27/13 12:57, Gerd Hoffmann wrote:
>> Make the 32bit pci hole start at end of ram, so all possible address
>> space is covered. Of course the firmware can use less than that.
>> Leaving space unused is no problem, mapping pci bars outside th
This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.
Signed-off-by: Tom Musta
---
V6: New.
target-ppc/translate.c | 31 +++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz)
and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). These
instructions are unusual in that they are considered a floating
point instruction if the indexed VSR is in the first half of the
array (0-31) but they are considered vect
Am 10.01.2014 um 20:06 hat Peter Lieven geschrieben:
> Am 10.01.2014 20:04, schrieb Kevin Wolf:
> > Am 06.01.2014 um 07:49 hat Peter Lieven geschrieben:
> >> On 06.01.2014 06:40, Fam Zheng wrote:
> >>> On 2014年01月06日 01:21, Peter Lieven wrote:
> Signed-off-by: Peter Lieven
> ---
>
This patchs adds the VSX Logical instructions that are new with
ISA V2.07:
- VSX Logical Equivalence (xxleqv)
- VSX Logical NAND (xxlnand)
- VSX Logical ORC (xxlorc)
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V5: Changes to address tcg-debug compilation errors.
target-p
On Sat, Jan 11, 2014 at 4:11 AM, Peter Maydell wrote:
> On 2 January 2014 07:31, Peter Crosthwaite
> wrote:
>> The SLCR needs to be able to reset the CPUs, so link the CPUs to the
>> SLCR.
>
>> @@ -496,10 +500,17 @@ static const MemoryRegionOps slcr_ops = {
>> static int zynq_slcr_init(SysBusDe
Am 10.01.2014 um 20:03 hat Peter Feiner geschrieben:
> On Fri, Jan 10, 2014 at 1:26 PM, Kevin Wolf wrote:
> > Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:
> >> On 10.01.2014 18:55, Kevin Wolf wrote:
> >> >Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
> >> >there?
> >>
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +/* C6.3.31 DUP (element, scalar)
> + * 31 21 2016 1510 95 40
> + * +---++-+--+--+
> + * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
> + * +-
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +case 0: /* Replicate(Zeros(24):imm8, 2) */
> +case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
> +case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
> +case 3: /* Replicate(imm8:Zeros(24), 2) */
> +{
> +int shift = cmod
This patch adds the Single Precision VSX Scalar Fused Multiply-Add
instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp,
xsnmaddmsp, xsnmsubasp, xsnmsubmsp.
The existing VSX_MADD() macro is modified to support rounding of the
intermediate double precision result to single precision.
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> From: Alex Bennée
>
> This adds support for the all the AdvSIMD vector copy operations
> (ARM ARM 3.6.5).
>
> Signed-off-by: Alex Bennée
> Signed-off-by: Peter Maydell
> ---
> target-arm/translate-a64.c | 210
> ++
This is the fourth and final series of patches that add emulation support
to QEMU for the PowerPC Vector Scalar Extension (VSX).
This series adds the instructions that were newly introduced with Power ISA
V2.07. This includes 3 scalar load instructions, 2 scalar store instructions,
7 standard sin
This patch adds the VSX Scalar Reciprocal Square Root Estimate
Single Precision (xsrsqrtesp) instruction.
The existing VSX_RSQRTE() macro is modified to support rounding
of the intermediate double-precision result to single precision.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> From: Michael Matz
>
> Add support for the SIMD "across lanes" instruction group (C3.6.4).
>
> Signed-off-by: Michael Matz
> [PMM: Updated to current codebase, added fp min/max ops,
> added unallocated encoding checks]
> Signed-off-by: Peter Mayde
Am 10.01.2014 20:14, schrieb Kevin Wolf:
> Am 10.01.2014 um 20:06 hat Peter Lieven geschrieben:
>> Am 10.01.2014 20:04, schrieb Kevin Wolf:
>>> Am 06.01.2014 um 07:49 hat Peter Lieven geschrieben:
On 06.01.2014 06:40, Fam Zheng wrote:
> On 2014年01月06日 01:21, Peter Lieven wrote:
>> Sign
This patch adds the VSX Scalar Convert Unsigned Integer Doubleword
to Floating Point Format and Round to Single Precision (xscvuxdsp)
and VSX Scalar Convert Signed Integer Douglbeword to Floating Point
Format and Round to Single Precision (xscvsxdsp) instructions.
The existing integer to floating
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +for (i = 0; i < elements; i++) {
> +switch (opcode) {
> +case 1: /* UZP1/2 */
> +{
> +int midpoint = elements / 2;
> +if (i < midpoint) {
> +read_vec_element(s, tcg_res, rn, 2 * i + p
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t
> indices,
> + uint64_t rn, uint64_t numregs)
Better with rn and numregs uint32_t?
Otherwise,
Reviewed-by: Richard Henderson
r~
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +if (pos < 64) {
> +tcg_resl = do_ext64(s, rn, 1, rn, 0, pos);
> +tcg_resh = do_ext64(s, rm, 0, rn, 1, pos);
> +} else {
> +tcg_resl = do_ext64(s, rm, 0, rn, 1, pos - 64);
> +tcg_resh = do
This patch adds the non-signalling scalar conversion instructions:
- VSX Scalar Convert Single Precision to Double Precision
Non-Signalling (xscvspdpn)
- VSX Scalar Convert Double Precision to Single Precision
Non-Signalling (xscvdpspn)
Signed-off-by: Tom Musta
---
V6: New.
target-
This patch adds two store scalar instructions:
- Store VSX Scalar as Integer Word Indexed (stxsiwx)
- Store VSX Scalar Single-Precision Indexed (stxsspx)
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V5: Updated to address tcg-debug compliation errors.
target-ppc/translate.c
This patch adds the VSX Scalar Round to Single Precision (xsrsp)
instruction.
Signed-off-by: Tom Musta
---
V6: New.
target-ppc/fpu_helper.c | 17 +
target-ppc/helper.h |1 +
target-ppc/translate.c |2 ++
3 files changed, 20 insertions(+), 0 deletions(-)
diff --gi
This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp)
instruction.
The existing VSX_MUL macro is modified to support rounding of the
intermediate result to single precision.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V2: Updated conversion to single precision.
ta
This patch adds the VSX Scalar Reciprocal Estimate Single Precision
(xsresp) instruction.
The existing VSX_RE macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V2: Updated conversion
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp)
instruction.
The existing VSX_SQRT() macro is modified to support rounding of the
intermediate double-precision result to single-precision.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V2: Updated conversion t
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.
The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.
Signed-off-by: Tom Musta
Reviewed-by: Richard Hender
This patch adds the scalar load instructions introduced in ISA
V2.07:
- Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax)
- Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx)
- Load VSX Scalar Single-Precision Indexed (lxsspx)
Signed-off-by: Tom Musta
Reviewed-by: Richard
This patch refactors the lxsdx generator. Resuable code is isolated
into a macro. The macro will be used in subsequent patches in this
series to implement other scalar load instructions.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
target-ppc/translate.c | 31 +
This patch adds a flag to identify those VSX instructions that are
new to Power ISA V2.07. The flag is added to the Power 8 processor
initialization so that the P8 models understand how to decode and
emulate instructions in this category.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
This patch refactors the stxsdx instruction. Reusable code is
extracted into a macro which will be used in subsequent patches
in this series.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
target-ppc/translate.c | 27 +++
1 files changed, 15 insertions(+)
I can't find the patches in my inbox but this breaks because
test-vmstate.c ignores ftruncate errors which are marked as
warn_unused_result on Ubuntu.
Regards,
Anthony Liguori
On Tue, Dec 24, 2013 at 8:06 AM, Juan Quintela wrote:
> Hi Anthony
>
> This is the patches in the migration queue. Ple
On 13.12.2013 14:22, Kevin Wolf wrote:
Odd file sizes could make bdrv_aligned_preadv() shorten the request in
non-aligned ways. Fix it by rounding to the required alignment instead
of 512 bytes.
Signed-off-by: Kevin Wolf
---
block.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Am 10.01.2014 20:04, schrieb Kevin Wolf:
> Am 06.01.2014 um 07:49 hat Peter Lieven geschrieben:
>> On 06.01.2014 06:40, Fam Zheng wrote:
>>> On 2014年01月06日 01:21, Peter Lieven wrote:
Signed-off-by: Peter Lieven
---
tests/qemu-iotests/014|4 ++--
tests/qemu-iote
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
> {
> /* Note that this is called with all non-FP cases from
> * table C3-6 so it must UNDEF for entries not specifically
> * allocated to instructions in that table.
>
On Fri, Jan 10, 2014 at 1:26 PM, Kevin Wolf wrote:
> Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:
>> On 10.01.2014 18:55, Kevin Wolf wrote:
>> >Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
>> >there?
>>
>> Yes, feel free to.
>
> Thanks, applied to the block branch.
>
Am 06.01.2014 um 07:49 hat Peter Lieven geschrieben:
> On 06.01.2014 06:40, Fam Zheng wrote:
> >On 2014年01月06日 01:21, Peter Lieven wrote:
> >>Signed-off-by: Peter Lieven
> >>---
> >> tests/qemu-iotests/014|4 ++--
> >> tests/qemu-iotests/014.out|2 +-
> >> tests/qemu-i
Am 18.12.2013 19:14, schrieb Stefan Weil:
> Am 07.12.2013 16:25, schrieb Stefan Weil:
>> GTK uses different hardware keycodes on Windows hosts, so some special
>> handling is needed to get the QEMU keycode.
>>
>> Signed-off-by: Stefan Weil
>> ---
>> ui/gtk.c | 18 +++---
>> 1 file c
On 01/10/2014 10:37 AM, Peter Maydell wrote:
> On 10 January 2014 18:28, Richard Henderson wrote:
>> On 01/10/2014 10:18 AM, Peter Maydell wrote:
> Maybe better to hoist load of
> tcg_rn to before initial assignment of tcg_addr?
>>> Not sure what you have in mind here. Pulling the
>>> cpu_
Public bug reported:
Tested against qemu-1.7.0 as well as qemu-1.7.50 on Debian Sid
Steps To Reproduce
$ cat > prog.hex << EOF
7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
02 00 03 00 01 00 00 00 54 80 04 08 34 00 00 00
00 00 00 00 00 00 00 00 34 00 20 00 01 00 28 00
00 00 00 00 01 00 00
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +static inline AArch64DecodeFn *lookup_disas_fn(AArch64DecodeTable *table,
> + uint32_t insn)
Better make table const.
> +static AArch64DecodeTable data_proc_simd[] = {
So that you can make this const.
Am 10.01.2014 um 19:38 hat Max Reitz geschrieben:
> On 10.01.2014 19:26, Kevin Wolf wrote:
> >Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:
> >>On 10.01.2014 18:55, Kevin Wolf wrote:
> >>>Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
> >>>there?
> >>Yes, feel free to.
>
Am 10.01.2014 19:24, schrieb Paolo Bonzini:
> Il 10/01/2014 19:07, Peter Lieven ha scritto:
>>
>>
>> Von meinem iPad gesendet
>>
>> Am 10.01.2014 um 19:05 schrieb "Paolo Bonzini" :
>>
>>> Il 10/01/2014 18:16, ronnie sahlberg ha scritto:
There is a common exception though, for the case where yo
hi Stefan,
Off course we can develop this feature as open source software.
Not sure whether GSoC would be a good route, because as far as I know GSoC
projects will be completed by coming October.
Please let me know of any other possible way we can work together (i.e.
organizational approach).
B
I'm working through the backlog from the holidays. I should be
through the full backlog today for PULL requests.
On Fri, Jan 10, 2014 at 10:06 AM, Paolo Bonzini wrote:
> Il 10/01/2014 18:29, Stefan Weil ha scritto:
>> Ping.
>>
>> QEMU compilation is broken on Debian hosts since several weeks now
On 10 January 2014 18:28, Richard Henderson wrote:
> On 01/10/2014 10:18 AM, Peter Maydell wrote:
>>> > Maybe better to hoist load of
>>> > tcg_rn to before initial assignment of tcg_addr?
>> Not sure what you have in mind here. Pulling the
>> cpu_reg_sp() call out one level like:
>>
>> if (is
Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:
> On 10.01.2014 18:55, Kevin Wolf wrote:
> >Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
> >there?
>
> Yes, feel free to.
Thanks, applied to the block branch.
Peter, no need for a second version of the patch then. :-)
>
On 10.01.2014 19:26, Kevin Wolf wrote:
Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:
On 10.01.2014 18:55, Kevin Wolf wrote:
Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
there?
Yes, feel free to.
Thanks, applied to the block branch.
Peter, no need for a second ve
On 13.12.2013 14:22, Kevin Wolf wrote:
Signed-off-by: Kevin Wolf
---
block.c | 52 +++
block/backup.c| 7 ++-
include/block/block_int.h | 4 ++--
3 files changed, 42 insertions(+), 21 deletions(-)
diff --git a/
On 01/10/2014 10:18 AM, Peter Maydell wrote:
>> > Maybe better to hoist load of
>> > tcg_rn to before initial assignment of tcg_addr?
> Not sure what you have in mind here. Pulling the
> cpu_reg_sp() call out one level like:
>
> if (is_postidx) {
> int rm = extract32(insn, 16, 5);
>
On 10 January 2014 18:05, Richard Henderson wrote:
> On 01/10/2014 09:12 AM, Peter Maydell wrote:
>> +TCGMemOp memop = MO_TE + size;
>
> Double space after =. Multiple occurrences.
Just this one plus its copy-n-paste in do_vec_st, I think.
>> +if (is_postidx) {
>> +int rm = ext
Il 10/01/2014 19:07, Peter Lieven ha scritto:
>
>
>
> Von meinem iPad gesendet
>
> Am 10.01.2014 um 19:05 schrieb "Paolo Bonzini" :
>
>> Il 10/01/2014 18:16, ronnie sahlberg ha scritto:
>>>
>>> There is a common exception though, for the case where you read past
>>> the end of file.
>>> So sho
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +tcg_gen_add_i64(cpu_reg_sp(s, rn), cpu_reg(s, rn), cpu_reg(s,
> rm));
Same cpu_reg_sp bug as patch 1.
r~
On 2 January 2014 07:31, Peter Crosthwaite wrote:
> The SLCR needs to be able to reset the CPUs, so link the CPUs to the
> SLCR.
> @@ -496,10 +500,17 @@ static const MemoryRegionOps slcr_ops = {
> static int zynq_slcr_init(SysBusDevice *dev)
> {
> ZynqSLCRState *s = ZYNQ_SLCR(dev);
> +
On 13.12.2013 14:22, Kevin Wolf wrote:
This is going to become the bdrv_co_do_preadv() equivalent for writes.
In this patch, however, just a function taking byte offsets is created,
it doesn't align anything yet.
Signed-off-by: Kevin Wolf
---
block.c | 23 +--
1 file chan
On 2 January 2014 07:30, Peter Crosthwaite wrote:
> Added Linux SMP support for the Xilinx Zynq platform (2x CPUs are
> supported)
>
> Signed-off-by: Peter Crosthwaite
> ---
> Changed from v3:
> Author reset
> s/zynq_cpus/cpus
> simplified custom secondary bootloader
> Rebased
> Changed from v2:
Von meinem iPad gesendet
Am 10.01.2014 um 19:05 schrieb "Paolo Bonzini" :
> Il 10/01/2014 18:16, ronnie sahlberg ha scritto:
>>
>> There is a common exception though, for the case where you read past
>> the end of file.
>> So short reads should normally not happen. Unless QEMU or the guest
>>
On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +TCGMemOp memop = MO_TE + size;
Double space after =. Multiple occurrences.
> +if (is_postidx) {
> +int rm = extract32(insn, 16, 5);
> +if (rm == 31) {
> +tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
> +
On 10.01.2014 18:55, Kevin Wolf wrote:
Am 10.01.2014 um 18:27 hat Max Reitz geschrieben:
On 09.01.2014 11:59, Kevin Wolf wrote:
[ CCing Max, who was recently active in this area, for another opinion ]
Am 08.01.2014 um 20:43 hat Peter Feiner geschrieben:
When a backing file is opened such that
Il 10/01/2014 18:16, ronnie sahlberg ha scritto:
>
> There is a common exception though, for the case where you read past
> the end of file.
> So short reads should normally not happen. Unless QEMU or the guest
> sends a request to libnfs to read past the end of the file.
Yes, this can happen in
Il 10/01/2014 18:29, Stefan Weil ha scritto:
> Ping.
>
> QEMU compilation is broken on Debian hosts since several weeks now.
> These block patches include the fix. I'd appreciate if they could be pulled.
And also all the other pull requests. Seriously, if it was not for the
few email messages on
Am 10.01.2014 um 18:27 hat Max Reitz geschrieben:
> On 09.01.2014 11:59, Kevin Wolf wrote:
> >[ CCing Max, who was recently active in this area, for another opinion ]
> >
> >Am 08.01.2014 um 20:43 hat Peter Feiner geschrieben:
> >>When a backing file is opened such that (1) a protocol is directly
>
Implement the SIMD ld/st single structure instructions.
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 141 -
1 file changed, 139 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 4
From: Alex Bennée
Add decode skeleton and function placeholders for all the SIMD data
processing instructions. Due to the complexity of this part of the
table the normal extract and switch approach gets very messy very
quickly, so we use a simple data-driven pattern-and-mask approach.
Signed-off
Am 20.12.2013 16:46, schrieb Stefan Hajnoczi:
> Happy holidays to all! I'll be back on January 2nd. Kevin is also away so
> there will be no block pull request next Friday.
>
> If there is anything urgent, please contact me at stefa...@gmail.com.
>
> The following changes since commit f8251db12
Add support for the SIMD EXT instruction (the only one in its
group, C3.6.1).
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 62 +-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/tra
From: Michael Matz
Add support for the SIMD TBL/TBLX instructions (group C3.6.2).
Signed-off-by: Michael Matz
[PMM: rewritten to do more of the decode in translate-a64.c,
and to do only one 64 bit pass at a time in the helper]
Signed-off-by: Peter Maydell
---
target-arm/helper-a64.c| 31
From: Alex Bennée
This patch adds support for the AdvSIMD modified immediate group
(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf
[AJB: new decode struct, minor bug fixes, optimisation]
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
--
This is an initial set of patches which make a start on SIMD (Neon)
emulation in the A64 decoder. The patches implement all the SIMD
load/store operations, provide a decoder skeleton for the SIMD
dp instructions, and implement all the instructions in the ARM ARM's
groupings C3.6.1 through C3.6.7.
On 09.01.2014 11:59, Kevin Wolf wrote:
[ CCing Max, who was recently active in this area, for another opinion ]
Am 08.01.2014 um 20:43 hat Peter Feiner geschrieben:
When a backing file is opened such that (1) a protocol is directly
used as the block driver and (2) the block driver has bdrv_file
From: Alex Bennée
This adds support support for the SIMD load/store
multiple category of instructions.
This also brings in a couple of helper functions for manipulating
sections of the SIMD registers:
* do_vec_get - fetch value from a slice of a vector register
* do_vec_set - set a slice of
From: Michael Matz
Add support for the SIMD "across lanes" instruction group (C3.6.4).
Signed-off-by: Michael Matz
[PMM: Updated to current codebase, added fp min/max ops,
added unallocated encoding checks]
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 177 +++
Add support for the SIMD scalar copy instruction group (C3.6.7),
which consists of the single instruction DUP (element, scalar).
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 42 +-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --gi
On Fri, Jan 10, 2014 at 8:10 AM, Peter Lieven wrote:
>
> Ronnie, can you also give a short advise on Kevin's question about short
> reads.
> I think they can happen if we read beyond past EOF or not?
>
Short reads should normally not happen in libnfs itself since servers
are often careful always
From: Michael Matz
Add support for the SIMD ZIP/UZIP/TRN instruction group
(C3.6.3).
Signed-off-by: Michael Matz
[PMM: use new do_vec_get/set etc functions and generally update to new
codebase standards; refactor to pull per-element loop outside switch]
Signed-off-by: Peter Maydell
---
targe
From: Alex Bennée
This adds support for the all the AdvSIMD vector copy operations
(ARM ARM 3.6.5).
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 210 -
1 file changed, 209 insertions(+), 1 deletion(-)
dif
On Fri, 10 Jan 2014 10:35:14 -0500
"Gabriel L. Somlo" wrote:
> On Fri, Jan 10, 2014 at 01:37:14PM +0100, Paolo Bonzini wrote:
> > Il 09/01/2014 22:44, Gabriel L. Somlo ha scritto:
> > > 1. hardcode "IRQNoFlags(){2, 8}" and require -no-hpet to prevent XP
> > >from bluescreening. Basically, thi
** Description changed:
This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on
linux kernel 3.5.0 (64-bit).
Whenever I run qemu (both i386 and x86_64) to use the en-us language (even
though it is the default), I get "Warning: no scancode found for keysym X" (X
is an intege
Am 10.01.2014 16:46, schrieb Kevin Wolf:
> Am 10.01.2014 um 16:05 hat Peter Lieven geschrieben:
>> On 10.01.2014 15:49, ronnie sahlberg wrote:
>>> On Fri, Jan 10, 2014 at 4:30 AM, Paolo Bonzini wrote:
Il 10/01/2014 13:12, Peter Lieven ha scritto:
> Then I shall convert everything to a qap
** Description changed:
- This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on
linux kernel 3.5.0 (64-bit).
+ This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on
linux kernel 3.5.0 (64-bit). (Haven't confirmed this for other targets).
Whenever I run qem
On Fri, Jan 10, 2014 at 04:17:14PM +0100, Igor Mammedov wrote:
> On Thu, 9 Jan 2014 17:12:41 -0200
> Eduardo Habkost wrote:
>
> > The original SeaBIOS code used the RamSize variable, that was used by
> > SeaBIOS for the size of RAM below 4GB, not for all RAM. When copied to
> > QEMU, the code wa
On Fri, Jan 10, 2014 at 03:52:54PM +, Anthony PERARD wrote:
> Signed-off-by: Anthony PERARD
Reviewed-by: Konrad Rzeszutek Wilk
I saw myself and was going to post a fix, but you beat me to it.
> ---
> hw/xen/xen_pt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --gi
** Description changed:
This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on
linux kernel 3.5.0 (64-bit).
Whenever I run qemu (both i386 and x86_64) to use the en-us language (even
though it is the default), I get "Warning: no scancode found for keysym X" (X
is an intege
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