>From 256484fd75d4eb4d248e5e0f493f16182da59dc2 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Wed, 4 Dec 2013 16:56:49 +0800
Subject: [PATCH v2 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also add corresponding part
>From cb3b12dd9873929b3a03214e3aa0ee5297e75119 Mon Sep 17 00:00:00 2001
From: Liu Jinsong
Date: Tue, 3 Dec 2013 04:17:50 +0800
Subject: [PATCH v2 1/2] target-i386: fix cpuid leaf 0x0d
Fix cpuid leaf 0x0d which incorrectly parsed eax and ebx.
However, before this patch the CPUID worked fine -- th
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
Version 1:
* Fix cpuid leaf 0x0d bug which incorrectly parsed eax and ebx;
* Expose
Paolo Bonzini wrote:
> Il 02/12/2013 17:42, Liu, Jinsong ha scritto:
>> From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00
>> 2001 From: Liu Jinsong
>> Date: Tue, 3 Dec 2013 05:08:19 +0800
>> Subject: [PATCH 2/2] target-i386: Intel MPX
>>
>> Add some MPX related definiation, and ha
On 2 December 2013 17:06, Peter Maydell wrote:
> On 6 November 2013 14:21, Ard Biesheuvel wrote:
>> This adds support for the AESE/AESD/AESMC/AESIMC instructions that
>> are available on some v8 implementations of Aarch32.
>>
>> Signed-off-by: Ard Biesheuvel
>
> Hi; thanks for this patch. I have
On 2013年12月04日 14:34, Benoît Canet wrote:
Le Wednesday 04 Dec 2013 à 14:12:19 (+0800), Fam Zheng a écrit :
On 2013年12月04日 13:20, Benoît Canet wrote:
Le Wednesday 04 Dec 2013 à 11:47:22 (+0800), Fam Zheng a écrit :
On 2013年12月03日 21:26, Benoît Canet wrote:
---
block.c | 64
So I've hit a bit of a init ordering issue that I'm not sure how best to solve,
Just some background:
In order for the virt GPU and the UI layer (SDL or GTK etc) to
interact properly over OpenGL use, I have created and OpenGL provider
in the console, and the UI layer can register callbacks for a s
On Tue, Dec 3, 2013 at 7:42 PM, Markus Armbruster wrote:
> Peter Crosthwaite writes:
>
>> This is a boiler-plate _nofail variant of qemu_opts_create. Remove and
>> use error_abort in call sites.
>>
>> A null argument needs to be added for the id field in affected callsites
>> due to inconsistency
This write-1-clear logic was incorrect. It was always clearing w1c
bits regardless of whether the written value was 1 or not. i.e. it
was implementing a write-anything-to-clear strategy.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
---
hw/net/cadence_gem.c | 13 ++---
1
The real hardware prefetches rx buffer descriptors ASAP and
potentially throws relevant interrupts following the fetch
even in the absence of a received packet.
Reported-by: Deepika Dhamija
Signed-off-by: Peter Crosthwaite
---
changed since v1:
Fixed function indentation (PMM review).
hw/net/c
Le Wednesday 04 Dec 2013 à 14:12:19 (+0800), Fam Zheng a écrit :
> On 2013年12月04日 13:20, Benoît Canet wrote:
> >Le Wednesday 04 Dec 2013 à 11:47:22 (+0800), Fam Zheng a écrit :
> >>On 2013年12月03日 21:26, Benoît Canet wrote:
> >>>---
> >>> block.c | 64
> >>> ++
Am 04.12.2013 07:27, schrieb Antony Pavlov:
> scripts/checkpatch.pl reports about some style problems,
> this commit fixes some of them:
Reviewed-by: Stefan Weil
Return false from can_receive() when no valid buffer descriptor is
available. Ensures against mass packet droppage in some applications.
Signed-off-by: Peter Crosthwaite
---
changed since v1:
Typos ("dont" "cant" "recieve") (PMM review)
hw/net/cadence_gem.c | 11 ++-
1 file changed, 10
The Specific address registers can be enabled or disabled by software.
QEMU was assuming they were always enabled. Implement the
disable/enable feature. SARs are disabled by writing to the lower half
register. They are re-enabled by then writing the upper half.
Reported-by: Deepika Dhamija
Signed
Bytes_to_copy was being updated before its final use where it
advances the rx buffer pointer. This was causing total mayhem,
where packet data for any subsequent fragments was being fetched
from the wrong place.
Reported-by: Deepika Dhamija
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter May
Signed-off-by: Peter Crosthwaite
---
hw/net/cadence_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 07e6fe7..8cfad04 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1246,6 +1246,7 @@ static const VMStateDescription vmst
On 2013年12月04日 13:20, Benoît Canet wrote:
Le Wednesday 04 Dec 2013 à 11:47:22 (+0800), Fam Zheng a écrit :
On 2013年12月03日 21:26, Benoît Canet wrote:
---
block.c | 64 +--
block/blkverify.c | 2 +-
include/block/block.h
Currently this just floods indicating that can_receive has been called
by the net framework. Instead, save the result of the most recent
can_receive callback as state and only print a message if the result
changes (indicating some sort of actual state change in GEM). Make said
debug message more me
The minimum packet size is 64, however this is before FCS stripping
occurs. So when FCS stripping the minimum packet size is 60. Fix.
Reported-by: Deepika Dhamija
Signed-off-by: Peter Crosthwaite
---
changed since v1: Setup bytes_to_copy before minimum size padding.
hw/net/cadence_gem.c | 13 +
Bit 27 of the RX buffer desc word 1 should be set when the packet was
accepted due to specific address register match. Implement.
This feature is absent from the Xilinx documentation (UG585) but the
behaviour is tested as accurate on real hardware.
Reported-by: Deepika Dhamija
Signed-off-by: Pet
The various Rx packet address matching mode flags were not being set in
the rx descriptor. Implement.
Reported-by: Deepika Dhamija
Signed-off-by: Peter Crosthwaite
---
changed since v1:
s/PROM_ACCEPT/PROMISCUOUS_ACCEPT to be more self documenting
Add full return code comment on accept function (
There was a replication of the rx descriptor address walking logic.
Reorder the flow control to remove. This refactoring also obsoletes
the local variables packet_desc_addr and last_desc_addr.
Signed-off-by: Peter Crosthwaite
---
hw/net/cadence_gem.c | 37 +
This has no real hardware analog and asserting correctness of DMA
addresses is not a perhiperal level problem. Delete.
Signed-off-by: Peter Crosthwaite
---
changed since v1:
Delete the check completely
hw/net/cadence_gem.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/hw/net/caden
From: "Edgar E. Iglesias"
We were updating the ownership bit of all descriptors if packets
get split and written through several descriptors.
Signed-off-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
---
hw/net/cadence_gem.c | 33 --
Cadence GEM has a MAC level loopback mode. Implement. Use the same basic
operation as the already implemented PHY loopback.
Reported-by: Deepika Dhamija
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi Peter,
This series updated cadence GEM (ethernet in Zynq) with a number of
bugfixes and enhancements. Most of this has come out of some stress
testing we have done internally.
I have also testing briefly using mainline Linux GEM driver.
root@zynq:~# wget
http://people.debian.org/~aurel32/qemu
On Wed, Dec 4, 2013 at 1:42 AM, Paolo Bonzini wrote:
> From: Hervé Poussineau
>
> We should not modify the type hash table while it is being iterated on.
> Assert that it does not happen.
>
> Signed-off-by: Hervé Poussineau
> Signed-off-by: Paolo Bonzini
> ---
> qom/object.c | 4
> 1 file
On 12/04/2013 01:47 AM, Eduardo Habkost wrote:
> On Tue, Dec 03, 2013 at 02:30:48PM +0100, Andreas Färber wrote:
>> Am 03.12.2013 00:03, schrieb Alexey Kardashevskiy:
>>> On 12/03/2013 09:09 AM, Andreas Färber wrote:
Am 02.12.2013 18:06, schrieb Michael Tokarev:
> 25.11.2013 07:39, Alexey
On Mon, Dec 2, 2013 at 10:26 PM, Peter Maydell wrote:
> On 2 December 2013 07:14, Peter Crosthwaite
> wrote:
>> The minimum packet size is 64, however this is before FCS stripping
>> occurs. So when FCS stripping the minimum packet size is 60. Fix.
>>
>> Reported-by: Deepika Dhamija
>> Signed-of
On 11/16/2013 03:58 AM, Alexey Kardashevskiy wrote:
> On 16.11.2013 0:15, Alexander Graf wrote:
>>
>>
>> Am 15.11.2013 um 00:12 schrieb Alexey Kardashevskiy :
>>
>>> At the moment only a whole CPU core can be assigned to a KVM. Since
>>> POWER7/8 support several threads per core, we want all thread
Le Wednesday 04 Dec 2013 à 09:07:02 (+0800), Fam Zheng a écrit :
> Whitespace changes to align columns.
>
> Signed-off-by: Fam Zheng
> ---
> tests/qemu-iotests/common | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/tests/qemu-iotests/common b/tests/qemu
Le Wednesday 04 Dec 2013 à 11:35:51 (+0800), Fam Zheng a écrit :
> On 2013年12月03日 21:26, Benoît Canet wrote:
> >---
> > block.c | 64
> > +--
> > block/blkverify.c | 2 +-
> > include/block/block.h | 16 +---
> > i
Le Wednesday 04 Dec 2013 à 11:47:22 (+0800), Fam Zheng a écrit :
> On 2013年12月03日 21:26, Benoît Canet wrote:
> >---
> > block.c | 64
> > +--
> > block/blkverify.c | 2 +-
> > include/block/block.h | 16 +---
> > i
Le Wednesday 04 Dec 2013 à 11:51:26 (+0800), Fam Zheng a écrit :
> On 2013年12月03日 21:26, Benoît Canet wrote:
> >Signed-off-by: Benoit Canet
> >---
> > blockdev.c | 49 +
> > hmp.c| 4 +++-
> > qapi-schema.json | 13 ++---
>
The initial problem was if the user ejects a ISO/DVD mounted in Fedora19,
the block device went into weird state when QEMU's monitor reported that
it is locked, has medium but tray open (some debug output is below).
Please comment. Thanks!
[root@localhost ~]# mount /dev/cdrom /mnt
mount: /dev/sr
This prevents the guest from preventing DVD medium removal when
there is no medium.
Without this, if the user has ejected a DVD, it is possible to
have a block device with an open tray, no media but locked.
Signed-off-by: Alexey Kardashevskiy
---
hw/scsi/scsi-disk.c | 1 -
1 file changed, 1 del
This makes scsi_command_name() public.
This makes use of scsi_command_name() in debug output for scsi-disk and
spapr-vscsi host bus adapter.
Signed-off-by: Alexey Kardashevskiy
---
hw/scsi/scsi-bus.c| 5 -
hw/scsi/scsi-disk.c | 3 ++-
hw/scsi/spapr_vscsi.c | 5 +++--
include/block/scs
Normally the user is expected to eject DVD if it is not locked by
the guest. eject_device() makes few checks and calls bdrv_close()
if DVD is not in use.
However it is still possible to eject DVD even if it is in use.
For that, QEMU sets "eject requested" flag, the guest reads it, issues
ALLOW_MED
On Mon, Dec 2, 2013 at 10:31 PM, Peter Maydell wrote:
> On 2 December 2013 07:16, Peter Crosthwaite
> wrote:
>
> Missing apostrophe in Subject.
>
>> Return false from can_recieve() when no valid buffer descriptor is
>
> "can_receive"
>
>> available. Ensures against mass packet droppage in some ap
On Mon, Dec 2, 2013 at 10:30 PM, Peter Maydell wrote:
> On 2 December 2013 07:15, Peter Crosthwaite
> wrote:
>> Currently this just floods indicating that can_receive has been called
>> by the net framework. Instead, save the result of the most recent
>> can_recieve callback as state and only pri
On Mon, Dec 2, 2013 at 10:14 PM, Peter Maydell wrote:
> On 2 December 2013 07:11, Peter Crosthwaite
> wrote:
>> The real hardware prefetches rx buffer descriptors ASAP and
>> potentially throws relevant interrupts following the fetch
>> even in the absence of a recieved packet.
>>
>> Reported-by:
On 2013年12月03日 21:26, Benoît Canet wrote:
---
block.c | 64 +--
block/blkverify.c | 2 +-
include/block/block.h | 16 +---
include/block/block_int.h | 9 ---
4 files changed, 75 insertions(+), 16 deletio
On 2013年12月03日 21:26, Benoît Canet wrote:
Signed-off-by: Benoit Canet
---
blockdev.c | 49 +
hmp.c| 4 +++-
qapi-schema.json | 13 ++---
qmp-commands.hx | 11 ++-
4 files changed, 64 insertions(+), 13 delet
On Mon, Dec 2, 2013 at 10:23 PM, Peter Maydell wrote:
> On 2 December 2013 07:13, Peter Crosthwaite
> wrote:
>> The Specific address registers can be enabled or disabled by software.
>> QEMU was assuming they where always enabled. Implement the
>
> "were"
>
Fixed
>> disable/enable feature. SARs
On 2013年12月03日 21:26, Benoît Canet wrote:
---
block.c | 64 +--
block/blkverify.c | 2 +-
include/block/block.h | 16 +---
include/block/block_int.h | 9 ---
4 files changed, 75 insertions(+), 16 deletio
On Mon, Dec 2, 2013 at 10:19 PM, Peter Maydell wrote:
> On 2 December 2013 07:12, Peter Crosthwaite
> wrote:
>> The various Rx packet address matching mode flags were not being set in
>> the rx descriptor. Implement.
>
>> -#define GEM_RX_REJECT 1
>> -#define GEM_RX_ACCEPT 0
>> +#define GEM_RX_R
On Mon, Dec 2, 2013 at 10:12 PM, Peter Maydell wrote:
> On 2 December 2013 07:11, Peter Crosthwaite
> wrote:
>> There was a replication of the rx descriptor address walking logic.
>> Reorder the flow control to remove. This refactoring also obsoletes
>> the local variables packet_desc_addr and la
On 2013年12月03日 21:26, Benoît Canet wrote:
---
blockdev.c | 8
qapi-schema.json | 32
2 files changed, 40 insertions(+)
diff --git a/blockdev.c b/blockdev.c
index a474bb5..824e718 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -1940,6 +1940,14 @@
于 2013/12/3 21:45, Stefan Hajnoczi 写道:
On Fri, Nov 22, 2013 at 12:27:09PM +0800, Wenchao Xia wrote:
+nbd_snapshot_port=10850
+nbd_snapshot_img="nbd:127.0.0.1:$nbd_snapshot_port"
+
+_export_nbd_snapshot()
+{
+$QEMU_NBD -v -t -b 127.0.0.1 -p $nbd_snapshot_port "$TEST_IMG" -l $1 &
Please use
于 2013/12/3 19:02, Stefan Hajnoczi 写道:
On Fri, Nov 22, 2013 at 12:27:10PM +0800, Wenchao Xia wrote:
diff --git a/qemu-img-cmds.hx b/qemu-img-cmds.hx
index da1d965..9a8153b 100644
--- a/qemu-img-cmds.hx
+++ b/qemu-img-cmds.hx
@@ -34,7 +34,7 @@ STEXI
ETEXI
DEF("convert", img_convert,
-"co
On Thu, 2013-11-28 at 15:48 +0100, Igor Mammedov wrote:
> On Wed, 9 Oct 2013 17:43:18 +0800
> Chen Fan wrote:
>
> > After ACPI get a signal to eject a vCPU, then it will notify
> > the vCPU thread to exit in KVM, and the vCPU must be removed from CPU list，
> > before the vCPU really removed, ther
On Thu, 2013-11-28 at 15:41 +0100, Igor Mammedov wrote:
> On Wed, 9 Oct 2013 17:43:08 +0800
> Chen Fan wrote:
>
> > Via implementing ACPI standard methods _EJ0 in bios, after Guest OS hot
> > remove
> > one vCPU, it is able to send a signal to QEMU, then QEMU could notify
> > the assigned vCPU o
Peter Crosthwaite wrote:
On Tue, Dec 3, 2013 at 7:11 PM, liguang wrote:
Signed-off-by: liguang
---
default-configs/arm-softmmu.mak |2 +
hw/timer/Makefile.objs |2 +
hw/timer/allwinner-a10_pit.c | 253 ++
Mix of _
On 12/03/2013 10:09 PM, Igor Mammedov wrote:
> On Tue, 3 Dec 2013 14:42:48 +1100
> Alexey Kardashevskiy wrote:
>
>> This adds suboptions support for -cpu. This keeps @cpu_model in order not
>> to break the existing architectures/machines.
>>
>> Cc: Andreas Färber
>> Signed-off-by: Alexey Kardas
Format "raw" doesn't always work on certain file systems (e.g. tmpfs).
Use qcow2 to make the allocation status explicit and split into a new
case.
Signed-off-by: Fam Zheng
Reviewed-by: Wenchao Xia
---
tests/qemu-iotests/048 | 27 ---
tests/qemu-iotests/048.out | 16 -
te
This series adds cache mode option in the iotests framework. Test cases are
updated to make use of cache mode and mask supported modes.
v6: [05] Recover disappeared two lines. (Benoît)
Added Wenchao's reviewed-by lines to other patches.
v5: Fix help test for "-c mode". (Wenchao)
v4: Address
Reviewed-by: Wenchao Xia
Quoting Peter Maydell (2013-12-03 18:38:54)
> On 4 December 2013 00:33, Michael Roth wrote:
> > In any case, ping? :)
>
> Who are you directing that ping at? This patch is commit 45d285abd7028 in
> master (Paolo put it in his pull request for 1.7, and kindly humoured my
> laziness by adding the C
The option sets cache mode used in the tests. "-nocache" is changed to
an alias to "-c none", and internally passes "-t none" to qemu-io.
Python scripts will make use of option this in the next commit.
Signed-off-by: Fam Zheng
Reviewed-by: Wenchao Xia
---
tests/qemu-iotests/check | 2 +-
tes
On 12/03/13 12:15, Paolo Bonzini wrote:
> Il 03/12/2013 14:25, Stefano Stabellini ha scritto:
>> CC'ing Paolo and xen-devel.
>> The original thread is here:
>>
>> http://marc.info/?l=xen-devel&m=135718999710640
>>
>> On Mon, 2 Dec 2013, Don Slutz wrote:
>>> Public bug reported:
>>>
>>>lt LINK l
So that the tests can run faster.
Signed-off-by: Fam Zheng
Reviewed-by: Wenchao Xia
---
tests/qemu-iotests/common | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qemu-iotests/common b/tests/qemu-iotests/common
index 4743c9e..b2a0944 100644
--- a/tests/qemu-iotests/comm
This replaces _unsupported_qemu_io_options and check for support of
current cache mode, and allow to provide a default if user didn't
specify.
Signed-off-by: Fam Zheng
Reviewed-by: Wenchao Xia
---
tests/qemu-iotests/026 | 3 ++-
tests/qemu-iotests/039 | 3 ++-
tests/qemu-iotests/0
Whitespace changes to align columns.
Signed-off-by: Fam Zheng
---
tests/qemu-iotests/common | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tests/qemu-iotests/common b/tests/qemu-iotests/common
index b2a0944..8b4e22c 100644
--- a/tests/qemu-iotests/common
+++
This will allow overriding cache mode from the "-c mode" option.
Signed-off-by: Fam Zheng
Reviewed-by: Wenchao Xia
---
tests/qemu-iotests/iotests.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py
index fb10ff4.
On 2013年12月03日 22:31, Benoît Canet wrote:
Le Tuesday 03 Dec 2013 à 16:25:26 (+0800), Fam Zheng a écrit :
-o options -o options to pass to qemu-img create/convert
--Toutput timestamps
--r randomize test order
These two lines
On 12/04/2013 01:32 PM, Peter Maydell wrote:
> You're right that we can just make this function return the TCGv
> temp rather than making the caller pass one in. Are you suggesting
> the 64-bit case should return cpu_X[reg] rather than a copy of it,
> though? I think it would be pretty hard to reas
On 4 December 2013 00:33, Michael Roth wrote:
> In any case, ping? :)
Who are you directing that ping at? This patch is commit 45d285abd7028 in
master (Paolo put it in his pull request for 1.7, and kindly humoured my
laziness by adding the CC: stable line in the process). If you intended to
ping
Quoting Peter Maydell (2013-11-05 13:36:57)
> On 5 November 2013 19:31, Andreas Färber wrote:
> > Am 05.11.2013 20:09, schrieb Peter Maydell:
> >> I don't think there's any need to respin a patch
> >> just because somebody thinks it might be worth
> >> applying to stable.
> >
> > Point is, if you
On 4 December 2013 00:10, Richard Henderson wrote:
> On 12/04/2013 10:51 AM, Peter Maydell wrote:
>> @@ -184,6 +184,18 @@ static TCGv_i64 cpu_reg(DisasContext *s, int reg)
>> }
>> }
>>
>> +/* read a cpu register in 32bit/64bit mode to dst */
>> +static void read_cpu_reg(DisasContext *s, TCGv
On 12/04/2013 04:58 AM, Tom Musta wrote:
> This is the fourth and final series of patches that add emulation support
> to QEMU for the PowerPC Vector Scalar Extension (VSX).
>
> This series adds the instructions that were newly introduced with Power ISA
> V2.07. This includes 3 scalar load instru
On 12/04/2013 04:58 AM, Tom Musta wrote:
> This patch adds the Single Precision VSX Scalar Fused Multiply-Add
> instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp,
> xsnmaddmsp, xsnmsubasp, xsnmsubmsp.
>
> The existing VSX_MADD() macro is modified to support rounding of the
> inter
On 4 December 2013 00:03, Richard Henderson wrote:
> On 12/04/2013 10:51 AM, Peter Maydell wrote:
>> +if (cond < 0x0e) {
>> +/* genuinely conditional branches */
>> +int label_nomatch = gen_new_label();
>> +arm_gen_test_cc(cond ^ 1, label_nomatch);
>> +gen_goto_
On 4 December 2013 00:07, Richard Henderson wrote:
> On 12/04/2013 10:51 AM, Peter Maydell wrote:
>> +label_nomatch = gen_new_label();
>> +if (op) { /* TBNZ */
>> +tcg_gen_brcondi_i64(TCG_COND_EQ, tcg_cmp, 0, label_nomatch);
>> +} else { /* TBZ */
>> +tcg_gen_brcondi_i6
On 3 December 2013 23:15, Christopher Covington wrote:
> Hi Claudio, Peter,
>
> On 12/03/2013 04:51 PM, Peter Maydell wrote:
>> From: Claudio Fontana
>>
>> Decode the various kinds of system instructions:
>> hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
>> sync instructions, which
On Mon, Dec 2, 2013 at 10:04 PM, Peter Maydell wrote:
> On 2 December 2013 07:10, Peter Crosthwaite
> wrote:
>> This has no real hardware analog. Leave the error message in is as
>> it is almost certainly a guest error, but fallthrough to the expected
>> behaviour.
>
> Maybe we should qemu_log_ma
Andreas Färber wrote:
Am 03.12.2013 13:01, schrieb Peter Crosthwaite:
On Tue, Dec 3, 2013 at 7:11 PM, liguang wrote:
Signed-off-by: liguang
---
hw/arm/Makefile.objs |2 +-
hw/arm/cubieboard.c | 33 +
2 files changed, 34 insertions(+), 1 dele
Peter Crosthwaite wrote:
On Tue, Dec 3, 2013 at 7:11 PM, liguang wrote:
Signed-off-by: liguang
---
hw/arm/Makefile.objs |2 +-
hw/arm/cubieboard.c | 33 +
2 files changed, 34 insertions(+), 1 deletions(-)
create mode 100644 hw/arm/cubieboard.c
d
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> @@ -184,6 +184,18 @@ static TCGv_i64 cpu_reg(DisasContext *s, int reg)
> }
> }
>
> +/* read a cpu register in 32bit/64bit mode to dst */
> +static void read_cpu_reg(DisasContext *s, TCGv_i64 dst, int reg, int sf)
> +{
> +if (reg == 31) {
>
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> +label_nomatch = gen_new_label();
> +if (op) { /* TBNZ */
> +tcg_gen_brcondi_i64(TCG_COND_EQ, tcg_cmp, 0, label_nomatch);
> +} else { /* TBZ */
> +tcg_gen_brcondi_i64(TCG_COND_NE, tcg_cmp, 0, label_nomatch);
> +}
> +
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> +if (cond < 0x0e) {
> +/* genuinely conditional branches */
> +int label_nomatch = gen_new_label();
> +arm_gen_test_cc(cond ^ 1, label_nomatch);
> +gen_goto_tb(s, 0, addr);
> +gen_set_label(label_nomatch);
>
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> Implement BR, BLR and RET. This is all of the 'unconditional
> branch (register)' instruction category except for ERET
> and DPRS (which are system mode only).
>
> Signed-off-by: Alexander Graf
> [claudio: reimplemented on
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> The A32/T32 gen_intermediate_code_internal() is complicated because it
> has to deal with:
> * conditionally executed instructions
> * Thumb IT blocks
> * kernel helper page
> * M profile exception-exit special casing
>
> None of these apply to A6
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> From: Claudio Fontana
>
> Decode the various kinds of system instructions:
> hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
> sync instructions, which include CLREX, DSB, DMB, ISB
> msr_i, which move immediate to processor state field
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> From: Claudio Fontana
>
> Provide a skeleton for a64 instruction decoding in translate-a64.c,
> by dividing instructions into the classes defined by the
> ARM Architecture Reference Manual(DDI0487A_a) section C3.
>
> Signed-off-by: Claudio Fontana
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> We will need helpers that only make sense with AArch64. Add
> helper-a64.{c,h} files as stubs that we can fill with these
> helpers in the following patches.
>
> Signed-off-by: Alexander Graf
> Signed-off-by: Peter Maydell
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> Register the aarch64-fpu XML and implement the necessary
> read/write handlers so we can support reading and writing
> of FP registers in the gdb stub.
>
> Signed-off-by: Peter Maydell
> ---
> configure |2 +-
> gdb-xml/aarch64-fpu
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> The information which AArch32 holds in the FPSCR is split for
> AArch64 into two logically distinct registers, FPSR and FPCR.
> Since they are carefully arranged to use non-overlapping bits,
> we leave the underlying state in the same place, and provid
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> When executing translation blocks we need to be able to recover
> our program counter. Add a method to set it for AArch64 CPUs.
> This covers user-mode, but for system mode emulation we will
> need to check if the CPU is in a
Hi Claudio, Peter,
On 12/03/2013 04:51 PM, Peter Maydell wrote:
> From: Claudio Fontana
>
> Decode the various kinds of system instructions:
> hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
> sync instructions, which include CLREX, DSB, DMB, ISB
> msr_i, which move immediate to pr
The information which AArch32 holds in the FPSCR is split for
AArch64 into two logically distinct registers, FPSR and FPCR.
Since they are carefully arranged to use non-overlapping bits,
we leave the underlying state in the same place, and provide
accessor functions which just update the appropriat
From: Alexander Graf
We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with these
helpers in the following patches.
Signed-off-by: Alexander Graf
Signed-off-by: Peter Maydell
---
target-arm/Makefile.objs |2 +-
target-arm/helper-a
From: Alexander Graf
Implement the B and BL instructions (PC relative branches and calls).
For convenience in managing TCG temporaries which might be generated
if a source register is the zero-register XZR, we provide a simple
mechanism for creating a new temp which is automatically freed at the
Register the aarch64-fpu XML and implement the necessary
read/write handlers so we can support reading and writing
of FP registers in the gdb stub.
Signed-off-by: Peter Maydell
---
configure |2 +-
gdb-xml/aarch64-fpu.xml | 86 +++
The A32/T32 gen_intermediate_code_internal() is complicated because it
has to deal with:
* conditionally executed instructions
* Thumb IT blocks
* kernel helper page
* M profile exception-exit special casing
None of these apply to A64, so putting the "this is A64 so
call the A64 decoder" check
Hi; this patchset represents the first bit of output of the work
we've been doing in Linaro to help get the SuSE A64 instruction
emulation upstream. Since code review on the 60-patch set Alex
posted suggested that we should rework the decoder skeleton to more
closely match the ARM ARM documentation
From: Alexander Graf
This patch adds emulation for the conditional branch (b.cond) instruction.
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder structure,
reused arm infrastructure for checking the flags]
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
On 12/03/13 18:23, Markus Armbruster wrote:
> Laszlo Ersek writes:
>
>> This patch allows the user to usefully specify
>>
>> -drive file=img_1,if=pflash,format=raw,readonly \
>> -drive file=img_2,if=pflash,format=raw
>>
>> on the command line. The flash images will be mapped under 4G in their
From: Alexander Graf
When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
This covers user-mode, but for system mode emulation we will
need to check if the CPU is in an AArch32 execution state.
Signed-off-by: Alexander Graf
Quoting Alex Bligh (2013-12-03 15:17:11)
> --On 3 December 2013 14:03:04 -0600 Michael Roth
> wrote:
>
> >> Note this will not apply to 1.5 and 1.6 as is.
> >
> > What needs to be changed? Wouldn't this patch also restore the 250hz
> > frequency for 1.6, as it was pre-0.14?
>
> The function nam
From: Claudio Fontana
Provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) section C3.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
target-arm/translate-a64
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