Peter Crosthwaite writes:
> Hi,
>
> On Thu, Nov 28, 2013 at 11:24 AM, Igor Mammedov wrote:
>> in case if caller setting property doesn't care about error and
>> passes in NULL as errp argument but error occurs in property setter,
>> it is silently discarded leaving object in undefined state.
>>
于 2013/11/28 8:48, Luiz Capitulino 写道:
On Wed, 13 Nov 2013 09:44:52 +0800
Wenchao Xia wrote:
Nested structure is not supported now, so following define is not valid:
{ 'event': 'EVENT_C',
'data': { 'a': { 'a_a', 'str', 'a_b', 'str' }, 'b': 'int' }
I think your general approach is reasonab
On Mon, 14 Oct 2013 19:20:45 +0200
Michael Walle wrote:
>
> Am Montag, 14. Oktober 2013, 18:29:24 schrieb Michael Walle:
> > This is a pull for various updates and fixes for the LatticeMico32 target.
> >
> > Please pull.
> >
> > changes since v1:
> > - rebased
> > - dropped patch "target-lm3
> > >>I understood the proposal was also to eliminate the
> > >>synchronize_rcu(), so while new interrupts would see the new
> > >>routing table, interrupts already in flight could pick up the old one.
> >Isn't that always the case with RCU? (See my answer above: "the
> >v
Signed-off-by: Antony Pavlov
Reviewed-by: Richard Henderson
---
hw/mips/mips_malta.c | 25 +
include/hw/mips/bios.h | 3 ++-
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 05c8771..604832f 100644
--- a
The ARM A9 MPCore has a timer that is global to all CPUs in the mpcore.
The timer is shared but each CPU has a private independent comparator
and interrupt.
Based on version contributed by Francois LEGAL.
Signed-off-by: François LEGAL
[PC changes:
* New commit message
* Re-implemented as singl
From: François LEGAL
Add the global timer to A9 MPCore.
Signed-off-by: François LEGAL
[PC Changes:
* new commit message
* split off original version as a separate patch
* Rebased against new mpcore implementation (with struct embedding)
]
Signed-off-by: Peter Crosthwaite
---
changed from v2
The header file sizes.h is used in linux kernel,
barebox bootloader and u-boot bootloader. It provides
the short and easy-to-read names for power-of-two
numbers. The numbers like this are othen used
for memory range sizes.
Signed-off-by: Antony Pavlov
Reviewed-by: Richard Henderson
---
include/
[PATCH 1/2] include/qemu: introduce sizes.h
[PATCH 2/2] hw/mips: use sizes.h macros
The sizes.h macros is a easy-to-read method of
power-of-two memory sizes representation. The sizes.h
macros are actively used in linux kernel and other
projects, so let's use them in QEMU too.
To make it consistent for easier code reading. The order in which
variables are defined and functions are called is set to match the
address map ordering.
The new consistent order of doing stuff is:
SCU -> GIC -> MPTimer -> WDT.
0 functional change.
Signed-off-by: Peter Crosthwaite
---
hw/c
Hi Peter,
Another spin of the ARM MPCore global timer work. Patches 1 & 2 are some
trivial cleanup to MPCore I did along the way.
Regards,
Peter
François LEGAL (1):
cpu/a9mpcore: Add Global Timer
Peter Crosthwaite (3):
cpu/a9mpcore: rename timerbusdev variable
cpu/a9mpcore: reorder opera
Rename this variable for consistency with the above defined mptimerdev
variable.
Signed-off-by: Peter Crosthwaite
---
hw/cpu/a9mpcore.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 918a7d1..1123101 100644
--- a/hw/cpu/a9
于 2013/11/26 0:47, Luiz Capitulino 写道:
On Wed, 13 Nov 2013 06:25:00 +0800
Wenchao Xia wrote:
This series is respined from RFC series at:
http://lists.nongnu.org/archive/html/qemu-devel/2013-11/msg00363.html
Patch 1-6 add support for enum as discriminator.
Patch 7 improve enum name generation,
Erik de Castro Lopo wrote:
> Erik de Castro Lopo wrote:
>
> > mle...@mega-nerd.com wrote:
> >
> > >
> > > Changes from original:
> > >
> > > * Call host's libc functions directly rather than _syscall*() (as
> > > suggested
> > > by Peter Maydell).
> > > * Remove un-needed #defines.
> > >
>
Hi,
On Thu, Nov 28, 2013 at 11:24 AM, Igor Mammedov wrote:
> in case if caller setting property doesn't care about error and
> passes in NULL as errp argument but error occurs in property setter,
> it is silently discarded leaving object in undefined state.
>
> As result it leads to hard to find
On 11/27/2013 06:24 PM, Igor Mammedov wrote:
> in case if caller setting property doesn't care about error and
> passes in NULL as errp argument but error occurs in property setter,
> it is silently discarded leaving object in undefined state.
>
> As result it leads to hard to find bugs, so if cal
The object-cast and class-cast caches cannot be shared because class
caching is conditional on the target type not being an interface and
object caching is unconditional. Leads to a bug when a class cast
to an interface follows an object cast to the same interface type:
FooObject = FOO(obj);
FooCl
On Wed, Nov 27, 2013 at 6:12 PM, Richard Henderson wrote:
> On 11/27/2013 08:41 PM, Xin Tong wrote:
> > I am trying to implement a out-of-line TLB lookup for QEMU
> softmmu-x86-64 on
> > x86-64 machine, potentially for better instruction cache performance, I
> have a
> > few questions.
> >
> > 1
Hi, Any comments for it? respin?
>> > I don't think a workqueue is even needed. You just need to use
>> > call_rcu to free "old" after releasing kvm->irq_lock.
>> >
>> > What do you think?
>>
>> It should be rate limited somehow. Since it guest triggarable guest
>> may cause host to allocate a lot of memory this way.
>
Why do
On 2013年11月27日 00:13, Paolo Bonzini wrote:
Il 26/11/2013 05:05, Fam Zheng ha scritto:
--- a/blockdev.c
+++ b/blockdev.c
@@ -1001,6 +1001,11 @@ SnapshotInfo
*qmp_blockdev_snapshot_delete_internal_sync(const char *device,
return NULL;
}
+if (bdrv_op_is_blocked(bs, BLOCK_OP_TY
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
Signed-off-by: Peter Crosthwaite
---
hw/arm/highbank.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --gi
Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the SCU base address.
Needed to boot Linux on the xilinx_zynq machine model.
Signed-off-by: Peter Crosthwaite
---
changed since v1:
use error report rather than fprintf(stderr
rename
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite
---
changed since v1:
use error report rather than fprintf(stderr
hw/arm/xilinx_zynq.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/arm/xilinx_zynq
Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.
So I have kinda tested this. I booted an ARM kernel on Highbank with the
stock Highbank DTB. It doesnt boot (and I will be doing something
wrong),
The reset Value of the CP15 CBAR is a vendor (machine) configurable
property. If ARM_FEATURE_CBAR is set, add it as a property at
post_init time.
Signed-off-by: Peter Crosthwaite
---
Change since v1:
Re-implement as dynamic property
target-arm/cpu.c | 14 ++
1 file changed, 14 inser
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite
---
changed since v1:
use error_report rather than fprintf(stderr
hw/arm/highbank.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/arm/highbank.c b/h
Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendor specific
so its best implemented as a CPU property (otherwise we would need
vendor specific child classes for every ARM implementation).
This patch prepares support for converting
Currently the uintXX property adders make a read only property. This
is not useful for devices that want to create board (or container)
configurable dynamic device properties. Fix by trivally adding property
setters to object_property_add_uintXX.
Signed-off-by: Peter Crosthwaite
---
qom/object.
Hi Peter,
This patch series fixed the Configuration base address init logic for
ARM CPUs, most notably for A9. Fixes both Zynq and Highbank which both
had broken CBAR.
Regards,
Peter
Changed since v1:
Fix QOM to support writeable dynamic properties
Use dynamic props instead (PMM/AF discussion)
U
** Changed in: qemu (Debian)
Status: Confirmed => Fix Released
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https://bugs.launchpad.net/bugs/739785
Title:
qemu-i386 user mode can't fork (bash: fork: Invalid argument)
Stat
Thanks for reporting this bug. Is there any other reproducer you can
give us?
** No longer affects: kvm (Ubuntu)
** Also affects: qemu (Ubuntu)
Importance: Undecided
Status: New
** Changed in: qemu (Ubuntu)
Status: New => Incomplete
** Changed in: qemu
Status: New => In
I am wondering what are some of the use cases for QEMU as an instruction
set emulator(not KVM). I know QEMU is used for the android emulator and
QEMU is used to host a few cycle accurate simulators ?
what else ?
Thank you,
Xin
On 11/27/2013 08:41 PM, Xin Tong wrote:
> I am trying to implement a out-of-line TLB lookup for QEMU softmmu-x86-64 on
> x86-64 machine, potentially for better instruction cache performance, I have a
> few questions.
>
> 1. I see that tcg_out_qemu_ld_slow_path/tcg_out_qemu_st_slow_path are
> gen
Hi LIuis
we can probably generate vector intrinsics using the tcg, e.g. add support
to tcg to emit vector instructions directly in code cache
why would a larger TLB make some operations slower, the TLB is a
direct-mapped hash and lookup should be O(1) there. In the cputlb, the
CPU_TLB_SIZE is a
Signed-off-by: Fam Zheng
---
tests/qemu-iotests/059| 5 +
tests/qemu-iotests/059.out| 5 +
tests/qemu-iotests/sample_images/iotest-version3.vmdk.bz2 | Bin 0 -> 414 bytes
3 files changed, 10 insertions(+)
create mode
On Wed, Nov 27, 2013 at 9:47 PM, Peter Maydell wrote:
> On 27 November 2013 11:39, Peter Crosthwaite
> wrote:
>> Is the "periphbase" ever runtime configurable? If not I'm not sure we
>> need the "reset".
>
> You can't runtime configure it (it's a bunch of signals into the
> core that determine wh
Signed-off-by: Fam Zheng
---
block/vmdk.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/block/vmdk.c b/block/vmdk.c
index a7ebd0f..6fd20dc 100644
--- a/block/vmdk.c
+++ b/block/vmdk.c
@@ -605,13 +605,20 @@ static int vmdk_open_vmdk4(BlockDriverState *bs,
hea
According to an update on VMware Knowledge Base [KB 2064959], we should be safe
to open version 3 as read only. This is meaningful as an compatibility
improvement, so let's enable it.
v2: [01] Parentheses around "flags & BDRV_O_RDWR". (Paolo)
Add comments. (Stefan)
Fam Zheng (2):
vmdk
On Thu, 14 Nov 2013 11:54:13 +0100
Stefan Hajnoczi wrote:
> This series decouples readline.c from the QEMU monitor and then reuses it in
> qemu-io. This adds history and command completion to the qemu-io interactive
> prompt.
I don't know what's the state of this series, but I reviewed the HMP
in case if caller setting property doesn't care about error and
passes in NULL as errp argument but error occurs in property setter,
it is silently discarded leaving object in undefined state.
As result it leads to hard to find bugs, so if caller doesn't
care about error it must be sure that prope
On Wed, 2013-11-27 at 07:00 -0700, Eric Blake wrote:
> On 10/09/2013 03:43 AM, Chen Fan wrote:
> > Signed-off-by: Chen Fan
> > ---
> > hw/i386/pc.c | 6 ++
> > hw/i386/pc_piix.c| 3 ++-
> > include/hw/boards.h | 2 ++
> > include/hw/i386/pc.h | 1 +
> > qapi-schema.json |
On Wed, 13 Nov 2013 09:44:52 +0800
Wenchao Xia wrote:
> Nested structure is not supported now, so following define is not valid:
> { 'event': 'EVENT_C',
> 'data': { 'a': { 'a_a', 'str', 'a_b', 'str' }, 'b': 'int' }
I think your general approach is reasonable, but there are a number of
details
This patch allows the user to usefully specify
-drive file=img_1,if=pflash,format=raw,readonly \
-drive file=img_2,if=pflash,format=raw
on the command line. The flash images will be mapped under 4G in their
reverse unit order -- that is, with their base addresses progressing
downwards, in inc
Signed-off-by: Igor Mammedov
---
v3:
- cpu_x86_properties changed to x86_cpu_properties,
upstream rebase on top of it.
v2:
- afaerber: inline property definition inside of
property array.
---
target-i386/cpu.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
dif
features family, model, stepping, level, hv_spinlocks are treated similarly
when passed from command line, so it's not necessary to handle each of them
individually. Collapse them to one catch-all branch which will treat
any not explicitly handled feature in format 'foo=val'.
PS:
Any unknown featu
* check "if (model_id == NULL)" looks unnecessary now, since all
builtin model-ids are not NULL and user shouldn't be able to set
it NULL (cpumodel string parsing code takes care of it, if feature
is specified as "model-id=" on command line, its parsing will
result in an empty string as value).
Si
Signed-off-by: Igor Mammedov
---
v3:
- cpu_x86_properties changed to x86_cpu_properties
upstream, rebase on top of it.
v2:
- afaerber: inline property definition inside of
property array.
---
target-i386/cpu.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
d
Signed-off-by: Igor Mammedov
---
v22:
- cpu_x86_properties changed to x86_cpu_properties,
upstream rebase on top of it.
---
target-i386/cpu.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 0f1066a..8a1f786 1
in generic case errp may be NULL and if an Error gets raised in visitor
but not set to *errp for the lack of pointer, value might be uninitialized:
object_property_parse(obj, "invalid value", "foo", NULL);
and accessed futher in property setter leading to incorrect property
value of object instance
This resolves the build issue with building the ROMs on OpenBSD on x86 archs.
As of OpenBSD 5.3 the compiler builds PIE binaries by default and thus the
whole OS/packages and so forth. The ROMs need to have PIE disabled. This
is my initial attempt at trying to get somehting upstream so that QEMU
bo
features check, enforce, hv_relaxed and hv_vapic are treated as boolean set to
'on'
when passed from command line, so it's not neccessary to handle each of them
separetly. Collapse them to one catch-all branch which will treat
any feature in format 'foo' as boolean set to 'on'.
PS:
Any unknown fe
Signed-off-by: Igor Mammedov
---
v2:
- cpu_x86_properties changed to x86_cpu_properties,
upstream rebase on top of it.
---
target-i386/cpu.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 34d3968..0f1066a 10
Signed-off-by: Igor Mammedov
---
v2:
fix conflict when removing kvm_feature_name[] with "kvm_pv_unhalt"
added by f010bc6 "target-i386: add feature kvm_pv_unhalt", earlier
patch "target-i386: set [+-]feature using static properties" were
ammended to include "feat-kvm-pv-unhalt" as static proper
- it breaks compatibility with previous output format by printing all features
in one string with "feat-" prefixes and all "_" replaced by "-"
Signed-off-by: Igor Mammedov
---
target-i386/cpu.c | 44 ++--
1 file changed, 10 insertions(+), 34 deletions(-)
helper to find a static property corresponding to a specific bit
in a specified field.
Signed-off-by: Igor Mammedov
---
hw/core/qdev-properties.c| 15 +++
include/hw/qdev-properties.h | 13 +
2 files changed, 28 insertions(+)
diff --git a/hw/core/qdev-properties.c b/
* Define static properties for cpuid feature bits
* property names of CPUID feature bits are changed to have "feat-"
prefix, so that it would be easy to distinguish them from other
properties.
* Convert [+-]cpuid_features to a set(QDict) of key, value pairs, where
+foo => (f
Signed-off-by: Igor Mammedov
---
target-i386/cpu.c | 33 ++---
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 1503e9a..5c3455f 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1119,24 +1119,6 @@ sta
Signed-off-by: Igor Mammedov
---
v3:
- cpu_x86_properties changed to x86_cpu_properties,
upstream rebase on top of it.
v2:
- afaerber: inline property definition inside of
property array.
---
target-i386/cpu.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
Signed-off-by: Igor Mammedov
---
v4:
- fix invalid use of error_is_set(errp) if errp == NULL
v3:
- cpu_x86_properties changed to x86_cpu_properties
upstream, rebase on top of it.
v2:
- afaerber: inline property definition inside of
property array.
---
target-i386/cpu.c | 29 +
Signed-off-by: Igor Mammedov
---
v3:
- cpu_x86_properties changed to x86_cpu_properties,
upstream rebase on top of it.
v2:
- afaerber: inline property definition inside of
property array.
---
target-i386/cpu.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
d
Changes since v9:
* rebased on top of https://github.com/afaerber/qemu-cpu/commits/qom-cpu-next
based on v1.7.0-rc2 release, fixing several conflicts
* skipped patches already commited to qom-cpu-next
* fixed conflit introduced by
f010bc6 "target-i386: add feature kvm_pv_unhalt",
patc
On Wed, Nov 27, 2013 at 11:32:51AM -0800, Anthony Liguori wrote:
> Brad Smith writes:
>
> > This resolves the build issue with building the ROMs on OpenBSD on x86
> > archs.
> > As of OpenBSD 5.3 the compiler builds PIE binaries by default and thus the
> > whole OS/packages and so forth. The ROM
I downloaded 1.7.0-rc2 and compiled it. Running it, I see the version
number reported as 1.6.92!?
In any case, I don't see any improvement, ie. the bug is still there.
Regards,
-Martin
On 28/11/13 01:58, Paolo Bonzini wrote:
> Hi, please test qemu 1.7.0-rc. There were several changes to the
On 11/27/2013 12:56 AM, Claudio Fontana wrote:
> On 09/27/2013 09:42 PM, Richard Henderson wrote:
>> On 09/26/2013 05:48 PM, Alexander Graf wrote:
>>> +if (setflags) {
>>> +tcg_dst = cpu_reg(dest);
>>> +} else {
>>> +tcg_dst = cpu_reg_sp(dest);
>>> +}
>>
>> Never sp for
** Summary changed:
- ps segfaults with qemu-arm-static
+ ps segfaults with qemu-{arm,armel,mips,powerpc}-static
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https://bugs.launchpad.net/bugs/1254672
Title:
ps segfaults with qemu
On Wed, 27 Nov 2013 18:55:57 +0100
Andreas Färber wrote:
> Am 16.07.2013 00:25, schrieb Igor Mammedov:
> > Signed-off-by: Igor Mammedov
> > ---
> > v2:
> > - rebase on top of hyperv_spinlock_attempts in X86CPU
> > ---
> > target-i386/cpu.c | 48 +++-
I'll have a look at it now.
Regards,
-Martin
On 28/11/13 01:58, Paolo Bonzini wrote:
> Hi, please test qemu 1.7.0-rc. There were several changes to the timer
> machinery that can help this bug.
>
--
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Christchurch | All sensitiv
Laszlo Ersek writes:
> On 11/27/13 18:22, Markus Armbruster wrote:
>
>> Perhaps the proper way to back partially writable flash contents isn't
>> splitting it into two devices, but backing a single device with a COW.
>> The backing file has initial contents (say BIOS image), the delta may
>> have
Leaving the backing file open although it is not needed anymore can
cause problems if it is opened through a block driver which allows
exclusive access only and if the create function of the block driver
used for the top image (the one being created) tries to close and reopen
the image file (which
As we will not have a cpu_x86_find_by_name() function anymore,
move the KVM default-vendor hack to instance_init.
Unfortunately we can't move that code to class_init because it depends
on KVM being initialized.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 32 +++---
Register separate QOM classes for each x86 CPU model.
This will allow management code to more easily probe what each CPU model
provides, by simply creating objects using the appropriate class name,
without having to restart QEMU.
This also allows us to eliminate the qdev_prop_set_globals_for_type
As we will initialize the X86CPU fields on instance_init eventually,
move the code that initializes the X86CPU data based on the CPU model
name closer to the object_new() call.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
As the new X86CPU subclass code is going to change lots of the code
invoving x86_def_t, let's rename the struct to match coding style first.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/targe
There isn't any kind of "registration" involved in cpu_x86_register()
anymore: it is simply looking up a CPU model name and loading the model
definition data into the X86CPU object. Rename it to x86_cpu_load_def()
to reflect what it does.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 6
As eventually the x86_def_t data is going to be provided by the CPU
class, it's better to not touch it, and handle the special cases on the
X86CPU object itself.
Current behavior of the code should stay exactly the same.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 11 ++-
1 f
I want to try to get this in 1.8, because I have found one additional use-case
for the new subclasses:
libvirt needs to be able to query details about the existing CPU models, and it
can't do that today without restarting QEMU every time. Having separate classes
for each CPU model allows libvirt t
Kevin Wolf writes:
> Am 26.11.2013 um 19:02 hat Anthony Liguori geschrieben:
>> Max Reitz writes:
>>
>> > This series fixes the drive-mirror blockjob in case of "none" sync mode
>> > to always use the old (current) image file as the backing file of the
>> > newly created mirrored file (in case
The compiler is capable of eliminating the KVM-specific function calls
as long as the calling function has an assert(kvm_enabled()) line, so we
don't need to wrap all KVM-specific inside #ifdefs.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 13 ++---
1 file changed, 2 insertion
Brad Smith writes:
> This resolves the build issue with building the ROMs on OpenBSD on x86 archs.
> As of OpenBSD 5.3 the compiler builds PIE binaries by default and thus the
> whole OS/packages and so forth. The ROMs need to have PIE disabled. This
> is my initial attempt at trying to get someh
qemu_co_queue_wait_insert_head() is unused in qemu code base now.
Signed-off-by: Marc-André Lureau
---
include/block/coroutine.h | 6 --
qemu-coroutine-lock.c | 8
2 files changed, 14 deletions(-)
diff --git a/include/block/coroutine.h b/include/block/coroutine.h
index 4d5c0cf.
This patch adds a _PXM method to ACPI CPU objects for the pc machine. The _PXM
value is derived from the passed in guest info, same way as CPU SRAT entries.
Currently, CPU SRAT entries are only enabled for cpus that are already present
in the system. The SRAT entries for hotpluggable processors ar
On Wed, 27 Nov 2013 18:55:57 +0100
Andreas Färber wrote:
> Am 16.07.2013 00:25, schrieb Igor Mammedov:
> > Signed-off-by: Igor Mammedov
> > ---
> > v2:
> > - rebase on top of hyperv_spinlock_attempts in X86CPU
> > ---
> > target-i386/cpu.c | 48 +++-
Il 27/11/2013 18:55, Andreas Färber ha scritto:
> Am 16.07.2013 00:25, schrieb Igor Mammedov:
>> Signed-off-by: Igor Mammedov
>> ---
>> v2:
>> - rebase on top of hyperv_spinlock_attempts in X86CPU
>> ---
>> target-i386/cpu.c | 48 +++-
>> 1 file change
On 11/20/2013 07:38 PM, Igor Mammedov wrote:
> - implements QEMU hardware part of memory hotplug protocol
> described at "docs/specs/acpi_mem_hotplug.txt"
> - handles only memory add notification event for now
>
> Signed-off-by: Igor Mammedov
> ---
> +0xa00:
> + read access:
> + [0x0-0x3
Am 16.07.2013 00:25, schrieb Igor Mammedov:
> Signed-off-by: Igor Mammedov
> ---
> v2:
> - rebase on top of hyperv_spinlock_attempts in X86CPU
> ---
> target-i386/cpu.c | 48 +++-
> 1 file changed, 47 insertions(+), 1 deletion(-)
>
> diff --git a/targ
On 11/27/13 18:22, Markus Armbruster wrote:
> Perhaps the proper way to back partially writable flash contents isn't
> splitting it into two devices, but backing a single device with a COW.
> The backing file has initial contents (say BIOS image), the delta may
> have additional contents (say non-
Igor Mammedov writes:
> On Wed, 27 Nov 2013 15:35:09 +0100
> Markus Armbruster wrote:
>
>> Igor Mammedov writes:
>>
>> > On Tue, 26 Nov 2013 15:49:05 +0100
>> > Markus Armbruster wrote:
>> >
>> >> Igor Mammedov writes:
>> >>
>> >> > On Thu, 21 Nov 2013 11:12:43 +0100
>> >> > Markus Armbrust
Laszlo Ersek writes:
> On 11/27/13 15:45, Markus Armbruster wrote:
>> Laszlo Ersek writes:
>>
>>> On 11/27/13 14:52, Markus Armbruster wrote:
Jordan Justen writes:
> On Tue, Nov 26, 2013 at 5:32 AM, Laszlo Ersek wrote:
>> On 11/26/13 13:36, Markus Armbruster wrote:
>>
>>
Il 27/11/2013 18:02, Markus Armbruster ha scritto:
> I have to admit I can't tell offhand what the heck QMP's netdev_add
> accepts, because I don't understand what "'*props:': '**'" means in
> qapi-schema.json. Even today, we permit code to serve as documentation
> and specification for new featur
Paolo Bonzini writes:
> Il 27/11/2013 15:15, Markus Armbruster ha scritto:
>> This is unfortunately a counter-example to the rule that HMP commands
>> should always be implemented in terms of their QMP counterparts. I do
>> not believe this is really a problem. It can be fixed la
On Tue, Nov 26, 2013 at 12:17:09PM +0100, Paolo Bonzini wrote:
> Il 26/11/2013 12:07, Lei Li ha scritto:
> > For this, I am not quite sure I understand it correctly, seems the latest
> > update of post copy migration was sent on last Oct, would you please give
> > some insights on what else could I
On Wed, Nov 27, 2013 at 03:35:53PM +0100, Paolo Bonzini wrote:
> > +
> > +len = numa_info[nodeid].node_mem;
> > +bind_mode = node_parse_bind_mode(nodeid);
> > +unsigned long *nodes = numa_info[nodeid].host_mem;
> > +
> > +/* This is a workaround for a long standing bug in Linux'
> >
On Wed, 27 Nov 2013 08:25:22 -0700
Eric Blake wrote:
> On 11/20/2013 07:38 PM, Igor Mammedov wrote:
> > Provides framework for splitting host RAM allocation/
> > policies into a separate backend that could be used
> > by devices. It would allow to separate host specific
> > options from device mo
Il 27/11/2013 15:15, Markus Armbruster ha scritto:
>>> >> This is unfortunately a counter-example to the rule that HMP commands
>>> >> should always be implemented in terms of their QMP counterparts. I do
>>> >> not believe this is really a problem. It can be fixed later; for now, I
>>> >> think
Il 27/11/2013 15:37, Igor Mammedov ha scritto:
> It looks like "realize" for -object / object-add implemented via
> an interface.
It does---but without unrealize and with the additional get_base_path.
> Maybe it should be renamed from QOMCommandLineIface to QOMRealizeIface
> and s/complete/realiz
Il 27/11/2013 16:53, Igor Mammedov ha scritto:
> Patch looks good,
> Please add patch to update hw/i386/ssdt-proc.hex.generated for hosts without
> iasl
> for completness
Also please rename PXM to CPXM or CPPX for consistency.
Paolo
>> >
>> > ---
>> > hw/i386/acpi-build.c |5 +
>> >
On Wed, 27 Nov 2013 16:21:23 +0100
Paolo Bonzini wrote:
> Il 27/11/2013 15:37, Igor Mammedov ha scritto:
> > It looks like "realize" for -object / object-add implemented via
> > an interface.
>
> It does---but without unrealize and with the additional get_base_path.
>
> > Maybe it should be ren
On Wed, 27 Nov 2013 14:02:43 +0100
Vasilis Liaskovitis wrote:
> This patch adds a _PXM method to ACPI CPU objects for the pc machine. The _PXM
> value is derived from the passed in guest info, same way as CPU SRAT entries.
>
> Currently, CPU SRAT entries are only enabled for cpus that are alread
On Wed, Nov 27, 2013 at 10:06:29AM +0800, Fam Zheng wrote:
> According to an update on VMware Knowledge Base [KB 2064959], we should be
> safe
> to open version 3 as read only. This is meaningful as an compatibility
> improvement, so let's enable it.
Acked-by: Stefan Hajnoczi
But please add a c
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