Hi,
>> Well, we also want to clean up the registers, so how about:
>>
>> BAR0: legacy, as is. If you access this, don't use the others.
Ok.
>> BAR1: new format virtio-pci layout. If you use this, don't use BAR0.
>> BAR2: virtio-cfg. If you use this, don't use BAR0.
Why use two bars for thi
From: Isaku Yamahata
Factor out smram/pam logic for later use.
Which will be used by q35 too.
[jba...@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |1 +
hw/pam.c | 120 +
From: Jason Baron
Add piix style acpi hotplug to q35.
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 172 +++-
hw/acpi_ich9.h | 10 +++
2 files changed, 181 insertions(+), 1 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index
Currently the savevm code contains a VMSTATE_STRUCT_VARRAY_POINTER_INT32
helper (a variably sized array with the number of elements in an int32_t),
but not VMSTATE_STRUCT_VARRAY_POINTER_UINT32 (... with the number of
elements in a uint32_t). This patch (trivially) fixes the deficiency.
Signed-off
This is the second posting of a patch series to make straightforward
extensions to the savevm / vmstate / migration infrastructure. This
is chiefly extra helper macros in vmstate.h to fill trivial gaps in
functionality.
v1->v2:
* Fixed small style bug
* Added new extension in patch 7/7
This patch adds some extra FPU state to CPUPPCState. Specifically,
fpscr is extended to a target_ulong bits, since some recent (64 bit)
CPUs now have more status bits than fit inside 32 bits. Also, we add
the 32 VSR registers present on CPUs with VSX (these extend the
standard FP regs, which toge
The current savevm code includes VMSTATE helpers for a number of commonly
used data types, but not for the float64 type used by the internal floating
point emulation code. This patch fixes the deficiency.
Signed-off-by: David Gibson
---
savevm.c | 23 +++
vmstate.h | 15
The savevm code contains VMSTATE_ helpers for a number of commonly used
types, but not for target_phys_addr_t. This patch fixes that deficiency
implementing VMSTATE_TPA helpers in terms of VMSTATE_UINT32 or
VMSTATE_UINT64 helpers as appropriate.
Signed-off-by: David Gibson
---
targphys.h | 11
Currently the pseries machine code allows a callback to be registered
for a hypercall number twice, as long as it's the same callback the second
time. We don't test for duplicate registrations of RTAS callbacks at all
so it will effectively be last registratiojn wins.
This was originally done bec
The vmstate infrastructure includes a VMS_MULTIPY flag, and associated
VMSTATE_VBUFFER_MULTIPLY helper macro. These can be used to save a
variably sized buffer where the size in bytes of the buffer isn't directly
accessible as a structure field, but an element count from which the size
can be deri
This adds an _EQUAL VMSTATE helper for target_ulongs, defined in terms of
VMSTATE_UINT32_EQUAL or VMSTATE_UINT64_EQUAL as appropriate.
Signed-off-by: David Gibson
---
hw/hw.h |6 ++
vmstate.h |7 +--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/hw.h b/hw/h
The VMSTATE_BUFFER_MULTIPLY macro is misnamed - it actually specifies
a variably sized buffer with VMS_VBUFFER, so should be named
VMSTATE_VBUFFER_MULTIPLY. This patch fixes this (the macro had no current
users under either name).
In addition, unlike the other VMSTATE_VBUFFER variants, this macro
Hi Alex,
Here are some assorted pending pseries patches which should be ready
to go. This clears the decks ready for a big series to add
savevm/migration support for pseries.
From: Jan Kiszka
[jba...@redhat.com: add PCI_CLASS_SERIAL_SMBUS definition]
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pci.c |1 +
hw/pci_ids.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index c457d50..62276ef 100644
--
Hi,
Qemu bits for q35 support, I'm posting the seabios changes separately. The
patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
qemu command line. Hopefully, we can make it the default for x86 at some future
point when we feel comfortable with it.
Since q35 patches have be
The savevm code already includes a number of *_EQUAL helpers which act as
sanity checks verifying that the configuration of the saved state matches
that of the machine we're loading into to work. Variants already exist
for 8 bit 16 bit and 32 bit integers, but not 64 bit integers. This patch
fill
From: Isaku Yamahata
Adds pci id constants which will be used by q35.
[jba...@redhat.com: move #define PCI_CLASS_SERIAL_SMBUS to another patch]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci_ids.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw
Am 09.10.2012 00:19, schrieb Richard Henderson:
On 10/08/2012 01:45 PM, Michael Roth wrote:
/* Alpha and SH4 user mode emulations and Softmmu call GETPC().
For all others, GETPC remains undefined (which makes TCI a little faster.
*/
-# if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA)
At present, using 'system_powerdown' from the monitor or otherwise
instructing qemu to (cleanly) shut down a pseries guest will not work,
because we did not have a method of signalling the shutdown request to the
guest.
PAPR does include a usable mechanism for this, though it is rather more
involv
From: Isaku Yamahata
This was totally off: The CC registers are 16 bit (stored as little
endian), their offsets run in reverse order, and D26IR as well as D25IR
have 4 bytes offset to their successors.
Reported-by: Jan Kiszka
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/q3
From: Jason Baron
This allows q35 to pass/set the size of the pcie window in its update routine.
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 21 -
hw/pcie_host.h |8 +---
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie
From: Isaku Yamahata
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pc.c | 15 +++
hw/pc.h |1 +
hw/pc_piix.c |
With PAPR guests, hypercalls allow registration of the Virtual Processor
Area (VPA), SLB shadow and dispatch trace log (DTL), each of which allow
for certain communication between the guest and hypervisor. Currently, we
store the addresses of the three areas and the size of the dtl in
CPUPPCState.
From: Jason Baron
Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks.
This allows q35 to specify its default disk type. It also allows q35 to
differentiate between ahci and ide disks, such that -drive if=ide does not
result in the creating of an ahci disk. This is importan
From: Jan Kiszka
Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers
an assertion.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/q35.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/q35.c b/hw/q35.c
index ff570ce..5d256cb 10
From: Isaku Yamahata
pci capability must be in PCI space.
It can't lay in PCIe extended config space.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index f855cf3..85ebef6 1
From: Isaku Yamahata
Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
standardized. PCI bridge swizzle is common logic, by introducing
this function duplicated swizzle logic will be avoided later.
[jba...@redhat.com: drop opaque argument]
Signed-off-by: Isaku Yamahata
Signe
> > Since the topic has come up, what is the process for vetting a
> > maintainer?
>
> Well, I can tell you the process I went through in becoming a
> co-maintainer for the ARM target (about a year or so ago now).
> Basically I started out by doing a bunch of work that seemed
> to need doing and t
From: Jason Baron
Automatically, locate the required q35 dsdt table on load. Otherwise we error
out. This could be done in the bios, but its harder to produce a good error
message.
Signed-off-by: Jason Baron
---
hw/pc.c | 19 +++
hw/pc.h |2 ++
hw/pc_piix.c |
From: Jason Baron
Let's use PCIExpressHost with QOM.
Acked-by: Andreas Färber
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 14 ++
hw/pcie_host.h |4
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index e2fd276..027ba05
From: Jan Kiszka
Both bits are added to the write-1-to-clear mask by default. As the
smbus device does not allow writes at all, we have to remove it from
that mask, also to avoid triggering a runtime assertion.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/q35_smbus.c |4 +++
From: Jason Baron
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Signed-off-by: Jason Baron
---
hw/pc.c | 24
hw/pc.h |2 ++
hw/pc_piix.c | 25 +
3 files changed, 2
From: Jason Baron
If -L is specified, and qemu does not find the bios file in , then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Signed-off-by: Jason Baron
---
vl.c | 36 +---
1 fi
From: Jason Baron
The current QEMUMachine definition has a 'use_scsi' field to indicate if a
machine type should use scsi by default. However, Q35 wants to use ahci by
default. Thus, introdue a new field in the QEMUMachine defintion, mach_if.
This field should be initialized by the machine type
From: Jan Kiszka
Same as for i44fx: KVM does not support SMM yet. Signal it initialized
to Seabios to avoid failures.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi
From: Jan Kiszka
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pc_q35.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index b6a619a..48083bb 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -69,6 +69,7 @@
#include "mc146818rtc.
Anthony Liguori writes:
> We'll never remove legacy so we shouldn't plan on it. There are
> literally hundreds of thousands of VMs out there with the current virtio
> drivers installed in them. We'll be supporting them for a very, very
> long time :-)
You will be supporting this for qemu on x86
On 10/05/2012 04:14 PM, Stefan Hajnoczi wrote:
> On Sun, Sep 23, 2012 at 10:37:09AM +0800, Dave Young wrote:
>> For the serial number decreasing issue, I think there's only these two ways
>> to
>> select, there's no ideal way to resolve this issue.
>> My use case for this is for the kdump kernel
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, October 09, 2012 1:54 AM
> To: Alexander Graf
> Cc: Andreas Färber; Bhushan Bharat-R65777; Avi Kivity; qemu-...@nongnu.org;
> qemu-devel@nongnu.org; Bhushan Bharat-R65777
> Subject: Re: [Qemu-devel] [PATCH 3/3] Adding BAR0 fo
Rusty Russell writes:
> Anthony Liguori writes:
>> Gerd Hoffmann writes:
>>
>>> Hi,
>>>
> So we could have for virtio something like this:
>
> Capabilities: [??] virtio-regs:
> legacy: BAR=0 offset=0
> virtio-pci: BAR=1 offset=1000
>
+##
+# Support building shared library libqblock
+libqblock.la:
+ $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C libqblock
V="$(V)" TARGET_DIR="$*/" libqblock.la,)
Does not work for out of tree build:
$ make -C obj-am
Anthony Liguori writes:
> Gerd Hoffmann writes:
>
>> Hi,
>>
So we could have for virtio something like this:
Capabilities: [??] virtio-regs:
legacy: BAR=0 offset=0
virtio-pci: BAR=1 offset=1000
virtio-cfg: BAR
Hi Johnson,
On Tue, Oct 9, 2012 at 1:19 AM, aurel...@aurel32.net
wrote:
> On Mon, Oct 08, 2012 at 05:11:00PM +, Johnson, Eric wrote:
>> > -Original Message-
>> > From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
>> > bounces+ericj=mips@nongnu.org] On Behalf Of
On Tue, 2012-10-09 at 00:44 +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 08, 2012 at 04:09:48PM -0600, Alex Williamson wrote:
> > On Mon, 2012-10-08 at 23:50 +0200, Michael S. Tsirkin wrote:
> > > On Mon, Oct 08, 2012 at 03:11:37PM -0600, Alex Williamson wrote:
> > > > On Mon, 2012-10-08 at 23:40
Hi,
Some comments inline, I've a version with all the comments fixed here:
http://cgit.freedesktop.org/~jwrdegoede/qemu/commit/?h=qemu-kvm-1.2-usbredir&id=5e342d2d2186757cc41b2f834e3503cf10e98c2b
On 09/22/2012 01:29 AM, Jan Kiszka wrote:
From: Jan Kiszka
This follows the logic of host-linux:
On Mon, Oct 08, 2012 at 04:09:48PM -0600, Alex Williamson wrote:
> On Mon, 2012-10-08 at 23:50 +0200, Michael S. Tsirkin wrote:
> > On Mon, Oct 08, 2012 at 03:11:37PM -0600, Alex Williamson wrote:
> > > On Mon, 2012-10-08 at 23:40 +0200, Michael S. Tsirkin wrote:
> > > > On Mon, Oct 08, 2012 at 01:
On 10/08/2012 01:45 PM, Michael Roth wrote:
> /* Alpha and SH4 user mode emulations and Softmmu call GETPC().
> For all others, GETPC remains undefined (which makes TCI a little faster.
> */
> -# if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4)
> +# if defined(CONFIG
On Mon, 2012-10-08 at 23:50 +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 08, 2012 at 03:11:37PM -0600, Alex Williamson wrote:
> > On Mon, 2012-10-08 at 23:40 +0200, Michael S. Tsirkin wrote:
> > > On Mon, Oct 08, 2012 at 01:27:33PM -0600, Alex Williamson wrote:
> > > > On Mon, 2012-10-08 at 22:15
On Mon, Oct 08, 2012 at 03:11:37PM -0600, Alex Williamson wrote:
> On Mon, 2012-10-08 at 23:40 +0200, Michael S. Tsirkin wrote:
> > On Mon, Oct 08, 2012 at 01:27:33PM -0600, Alex Williamson wrote:
> > > On Mon, 2012-10-08 at 22:15 +0200, Michael S. Tsirkin wrote:
> > > > On Mon, Oct 08, 2012 at 09:
On Monday, October 08, 2012 11:32:54 PM Hans de Goede wrote:
> Hi,
>
> On 10/08/2012 10:18 PM, Shawn Starr wrote:
> > On Monday, October 08, 2012 10:10:49 PM Hans de Goede wrote:
> >> Hi,
> >>
> >> On 10/08/2012 06:11 PM, Johannes Stezenbach wrote:
> >>
> >>
> >>
> >> > I also wonder if this
Hi,
On 10/08/2012 10:18 PM, Shawn Starr wrote:
On Monday, October 08, 2012 10:10:49 PM Hans de Goede wrote:
Hi,
On 10/08/2012 06:11 PM, Johannes Stezenbach wrote:
> I also wonder if this is not a generic problem
for all emulated hw if the driver uses some timeout?
Yes it likely is, be
On 10/08/2012 04:08:31 PM, Alexander Graf wrote:
On 08.10.2012, at 23:05, Scott Wood wrote:
> On 10/08/2012 03:48:42 PM, Alexander Graf wrote:
>> On 08.10.2012, at 22:20, Scott Wood wrote:
>> > On 10/08/2012 07:23:52 AM, Alexander Graf wrote:
>> >> On PPC, we don't have PIO. So usually PIO spac
Am 08.10.2012 15:17, schrieb Andreas Färber:
Hi Peter,
Am 08.10.2012 08:39, schrieb Peter Crosthwaite:
Im currently investigating the possibility of building QEMU with
multiple CPU architectures active concurrently. That is, I have a
binary with both an target-arm and target-microblaze and wish
On Mon, 2012-10-08 at 23:40 +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 08, 2012 at 01:27:33PM -0600, Alex Williamson wrote:
> > On Mon, 2012-10-08 at 22:15 +0200, Michael S. Tsirkin wrote:
> > > On Mon, Oct 08, 2012 at 09:58:32AM -0600, Alex Williamson wrote:
> > > > Michael, Jan,
> > > >
> >
On 08.10.2012, at 23:05, Scott Wood wrote:
> On 10/08/2012 03:48:42 PM, Alexander Graf wrote:
>> On 08.10.2012, at 22:20, Scott Wood wrote:
>> > On 10/08/2012 07:23:52 AM, Alexander Graf wrote:
>> >> On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is
>> >> accessible via MMIO.
On 10/08/2012 03:48:42 PM, Alexander Graf wrote:
On 08.10.2012, at 22:20, Scott Wood wrote:
> On 10/08/2012 07:23:52 AM, Alexander Graf wrote:
>> On PPC, we don't have PIO. So usually PIO space behind a PCI
bridge is
>> accessible via MMIO. Do this mapping explicitly by mapping the PIO
spac
Am 08.10.2012 22:45, schrieb Michael Roth:
commit c28ae41 introduced GETPC() usage for sparc, which is currently
not defined when building with --enable-tcg-interpreter. Add sparc to
the list of targets we selectively define GETPC() for.
Signed-off-by: Michael Roth
---
exec-all.h |3 ++-
Am 08.10.2012 22:01, schrieb Michael S. Tsirkin:
On Wed, Oct 03, 2012 at 11:11:02PM +0200, Stefan Weil wrote:
The current check will give a wrong result for gcc-5.x with x < 4.
Using QEMU_GNUC_PREREQ is simpler and fixes that issue.
Signed-off-by: Stefan Weil
---
With current gcc versions (gc
Gerd Hoffmann writes:
> Hi,
>
>>> So we could have for virtio something like this:
>>>
>>> Capabilities: [??] virtio-regs:
>>> legacy: BAR=0 offset=0
>>> virtio-pci: BAR=1 offset=1000
>>> virtio-cfg: BAR=1 offset=1800
>>
>> This would be
Peter Maydell writes:
> On 8 October 2012 21:23, Anthony Liguori wrote:
>> It may be possible to cheat and compile the TCG + CPU code multiple
>> times as dynamic libraries. You can then load the libraries with
>> dlopen() with local symbol resolution.
>
> ...and when the common code wants to (
On 08.10.2012, at 22:20, Scott Wood wrote:
> On 10/08/2012 07:23:52 AM, Alexander Graf wrote:
>> On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is
>> accessible via MMIO. Do this mapping explicitly by mapping the PIO space
>> of our PCI bus into a memory region that lives in
commit c28ae41 introduced GETPC() usage for sparc, which is currently
not defined when building with --enable-tcg-interpreter. Add sparc to
the list of targets we selectively define GETPC() for.
Signed-off-by: Michael Roth
---
exec-all.h |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
On Mon, Oct 08, 2012 at 01:27:33PM -0600, Alex Williamson wrote:
> On Mon, 2012-10-08 at 22:15 +0200, Michael S. Tsirkin wrote:
> > On Mon, Oct 08, 2012 at 09:58:32AM -0600, Alex Williamson wrote:
> > > Michael, Jan,
> > >
> > > Any comments on these? I'd like to make the PCI changes before I upd
On 8 October 2012 21:23, Anthony Liguori wrote:
> It may be possible to cheat and compile the TCG + CPU code multiple
> times as dynamic libraries. You can then load the libraries with
> dlopen() with local symbol resolution.
...and when the common code wants to (say) call cpu_exit() on a
partic
Peter Maydell writes:
> On 8 October 2012 07:39, Peter Crosthwaite
> wrote:
>> Im currently investigating the possibility of building QEMU with
>> multiple CPU architectures active concurrently. That is, I have a
>> binary with both an target-arm and target-microblaze and wish to run
>> them as
On 10/08/2012 02:04:43 PM, Alexander Graf wrote:
On 08.10.2012, at 20:00, Andreas Färber wrote:
> Am 08.10.2012 18:46, schrieb Bharat Bhushan:
>> #define BINARY_DEVICE_TREE_FILE"mpc8544ds.dtb"
>> #define UIMAGE_LOAD_BASE 0
>> -#define DTC_LOAD_PAD 0x180
>> +#defi
On 10/08/2012 07:23:52 AM, Alexander Graf wrote:
On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is
accessible via MMIO. Do this mapping explicitly by mapping the PIO
space
of our PCI bus into a memory region that lives in memory space.
Signed-off-by: Alexander Graf
---
On Monday, October 08, 2012 10:10:49 PM Hans de Goede wrote:
> Hi,
>
> On 10/08/2012 06:11 PM, Johannes Stezenbach wrote:
>
>
>
> > I also wonder if this is not a generic problem
> >
> > for all emulated hw if the driver uses some timeout?
>
> Yes it likely is, because the emulated timer int
Hi,
>> So we could have for virtio something like this:
>>
>> Capabilities: [??] virtio-regs:
>> legacy: BAR=0 offset=0
>> virtio-pci: BAR=1 offset=1000
>> virtio-cfg: BAR=1 offset=1800
>
> This would be a vendor specific PCI capability so
Erm
This was supposed to be a reply to the "Re: [PATCH v2] usb-redir: Allow to attach
USB 2.0 devices to 1.1 host controller"
thread, in that context is should make more sense :)
Regards,
Hans
On 10/08/2012 10:12 PM, Hans de Goede wrote:
Hi,
Funny that you ping about this just now, as I wa
Hi,
Funny that you ping about this just now, as I wanted to work on
this today, but sofar I did not get around to it. Maybe tonight I will :)
Long story short: Yes I've some remarks, but I pan to fix those myself and
then merge it in my tree.
I'll get back to you when this is done.
Regards,
H
Hi,
On 10/08/2012 06:11 PM, Johannes Stezenbach wrote:
> I also wonder if this is not a generic problem
for all emulated hw if the driver uses some timeout?
Yes it likely is, because the emulated timer interrupt will
try to make up for time lost when the vm was not running
(in either hyperv
On 8 October 2012 18:19, Johnson, Eric wrote:
> Peter Maydell wrote:
>> I also note that target-mips/ is currently in the "Odd Fixes"
>> maintenance state -- is anybody at MIPS in a position to step
>> up and help with bug fixing and patch review of that area?
>
> MIPS has been considering several
On Mon, 2012-10-08 at 22:15 +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 08, 2012 at 09:58:32AM -0600, Alex Williamson wrote:
> > Michael, Jan,
> >
> > Any comments on these? I'd like to make the PCI changes before I update
> > vfio-pci to make use of the new resampling irqfd in kvm. We don't
On Mon, Oct 08, 2012 at 09:58:32AM -0600, Alex Williamson wrote:
> Michael, Jan,
>
> Any comments on these? I'd like to make the PCI changes before I update
> vfio-pci to make use of the new resampling irqfd in kvm. We don't have
> anyone officially listed as maintainer of pci-assign since it's
On 08.10.2012, at 20:00, Andreas Färber wrote:
> Am 08.10.2012 18:46, schrieb Bharat Bhushan:
>> PCI Root complex have TYPE-1 configuration header while PCI endpoint
>> have type-0 configuration header. The type-1 configuration header have
>> a BAR (BAR0). In Freescale PCI controller BAR0 is used
On Wed, Oct 03, 2012 at 11:11:02PM +0200, Stefan Weil wrote:
> The current check will give a wrong result for gcc-5.x with x < 4.
> Using QEMU_GNUC_PREREQ is simpler and fixes that issue.
>
> Signed-off-by: Stefan Weil
> ---
>
> With current gcc versions (gcc-4.x) there is no problem.
> Neverthe
On 08.10.2012, at 19:21, Andreas Färber wrote:
> Am 08.10.2012 18:46, schrieb Bharat Bhushan:
>> All devices are also placed under CCSR memory region.
>> The CCSR memory region is exported to pci device. The MSI interrupt
>> generation is the main reason to export the CCSR region to PCI device.
>
On 08.10.2012, at 18:46, Bharat Bhushan wrote:
> it was wrongly using serial_hds[0] instead of serial_hds[1]
>
> Signed-off-by: Bharat Bhushan
Thanks, applied to ppc-next.
Alex
> ---
> hw/ppc/e500.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/hw/ppc/e500.c
Jan Kiszka writes:
> On 2012-09-11 17:53, Jan Kiszka wrote:
>> Our one and only BIOS depends on a writable shadowed BIOS in the ISA
>> range. As we have no interface to control the write property, make that
>> region writable by default.
>>
>> Signed-off-by: Jan Kiszka
>> ---
>>
>> This unbrea
okay, now I see that this lacks a lot of "presentation".
This is a patch to fix a problem on signal masks, and solves a certain
problem when the client is "playing the game" of sigsegv mask/unmask.
I will explain it a little more on a better patch. This should have
been explained on the 00/00 cove
** Changed in: qemu (openSUSE)
Importance: Unknown => Critical
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https://bugs.launchpad.net/bugs/156085
Title:
Could not open /proc/bus/usb/devices
Status in QEMU:
Fix Released
St
On Mon, Oct 08, 2012 at 07:07:08PM +0200, Jan Kiszka wrote:
> As the block layer may decide to flush bottom-halfs while the machine is
> still initializing (e.g. to read geometry data from the disk), our
> postponed open event may be processed before the last frontend
> registered with a muxed char
Am 08.10.2012 18:46, schrieb Bharat Bhushan:
> PCI Root complex have TYPE-1 configuration header while PCI endpoint
> have type-0 configuration header. The type-1 configuration header have
> a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
> address space to CCSR address space
On 2012-09-22 11:29, Jan Kiszka wrote:
> From: Jan Kiszka
>
> This follows the logic of host-linux: If a 2.0 device has no ISO
> endpoint and no interrupt endpoint with a packet size > 64, we can
> attach it also to an 1.1 host controller. In case the redir server does
> not report endpoint sizes
On 2012-09-11 17:53, Jan Kiszka wrote:
> Our one and only BIOS depends on a writable shadowed BIOS in the ISA
> range. As we have no interface to control the write property, make that
> region writable by default.
>
> Signed-off-by: Jan Kiszka
> ---
>
> This unbreaks isapc for TCG, and keep it w
Am 08.10.2012 18:46, schrieb Bharat Bhushan:
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index 1949c81..b3e6a1e 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
[...]
> @@ -478,8 +481,12 @@ void ppce500_init(PPCE500Params *params)
> vmstate_register_ram_global(ram);
> memory_region_a
Am 08.10.2012 18:46, schrieb Bharat Bhushan:
> All devices are also placed under CCSR memory region.
> The CCSR memory region is exported to pci device. The MSI interrupt
> generation is the main reason to export the CCSR region to PCI device.
> This put the requirement to move mpic under CCSR regi
On Mon, Oct 08, 2012 at 08:42:03AM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target-sparc/translate.c | 1 +
> 1 file changed, 1 insertion(+)
>
> This should fix the boot problem that Aurelien saw. It also showed
> up in some userland speed testing I'm trying to
On Mon, Oct 08, 2012 at 05:11:00PM +, Johnson, Eric wrote:
> > -Original Message-
> > From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> > bounces+ericj=mips@nongnu.org] On Behalf Of Jia Liu
> > Sent: Monday, October 08, 2012 1:51 AM
> > To: qemu-devel@nongnu.o
> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Peter Maydell
> Sent: Friday, October 05, 2012 8:07 AM
> To: Kotler, Reed
> Cc: Lau, David; Fuhler, Rich; Gilmore, Douglas; qemu-devel@nongnu.org;
> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Jia Liu
> Sent: Monday, October 08, 2012 1:51 AM
> To: qemu-devel@nongnu.org
> Cc: aurel...@aurel32.net
> Subject: [Qemu-devel] [PATCH v10 14/14] t
On 2012-10-08 19:07, Aurelien Jarno wrote:
> On Mon, Oct 08, 2012 at 08:52:30AM +0200, Jan Kiszka wrote:
>> On 2012-10-06 04:13, Peter Maydell wrote:
>>> On 5 October 2012 19:01, Jan Kiszka wrote:
I'm not a fan of this either, but the alternatives are way more
complicated. We either need
All devices are also placed under CCSR memory region.
The CCSR memory region is exported to pci device. The MSI interrupt
generation is the main reason to export the CCSR region to PCI device.
This put the requirement to move mpic under CCSR region, but logically
all devices should be under CCSR. S
On Mon, Oct 08, 2012 at 08:52:30AM +0200, Jan Kiszka wrote:
> On 2012-10-06 04:13, Peter Maydell wrote:
> > On 5 October 2012 19:01, Jan Kiszka wrote:
> >> I'm not a fan of this either, but the alternatives are way more
> >> complicated. We either need to rewrite the chardev subsystem,
> >> specif
As the block layer may decide to flush bottom-halfs while the machine is
still initializing (e.g. to read geometry data from the disk), our
postponed open event may be processed before the last frontend
registered with a muxed chardev. Until the semantics of BHs have been
clarified, use an expired
Peter Maydell writes:
> On 8 October 2012 14:29, Anthony Liguori wrote:
>> This is wrong.
>>
>> Container properties are added by the user. You will turn a gracefully
>> failure (during hotplug) into an abort().
>
> No, it's turning a bug into an abort -- we don't handle trying to
> create two
Am 08.10.2012 18:46, schrieb Bharat Bhushan:
> it was wrongly using serial_hds[0] instead of serial_hds[1]
>
> Signed-off-by: Bharat Bhushan
Reviewed-by: Andreas Färber
Andreas
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SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffe
PCI Root complex have TYPE-1 configuration header while PCI endpoint
have type-0 configuration header. The type-1 configuration header have
a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
address space to CCSR address space. This can used for 2 purposes: 1)
for MSI interrupt
it was wrongly using serial_hds[0] instead of serial_hds[1]
Signed-off-by: Bharat Bhushan
---
hw/ppc/e500.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index d23f9b2..1949c81 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -496,7 +496
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