On 2012-06-21 08:46, Alexey Kardashevskiy wrote:
>
> Ok, another try. Is it any better now? :)
No - posted the old version accidentally?
Jan
>
>
> Normally QEMU expects the guest to initialize MSI/MSIX vectors.
> However on POWER the guest uses RTAS subsystem to configure MSI/MSIX and
> does
Ok, another try. Is it any better now? :)
Normally QEMU expects the guest to initialize MSI/MSIX vectors.
However on POWER the guest uses RTAS subsystem to configure MSI/MSIX and
does not write these vectors to device's config space or MSIX BAR.
On the other hand, msi_notify()/msix_notify() wri
Hi,
>>> Why leave pci accessors and not implement usb_memory_rw() wrappers?
>>
>> Well, "usb" is a bit too generic, ehci and ohci would each need to have
>> their own sets of wrappers. But yes, that's possible... is it really
>> worth it ? There's nothing fundamentally wrong with using the dma_*
The sizep arg is populated with the size of the loaded device tree. Since this
is one of those informational "please populate" type arguments it should be
optional. Guarded writes to *sizep against NULL accordingly.
Signed-off-by: Peter A. G. Crosthwaite
---
device_tree.c |8 ++--
1 file
On Tue, 2012-06-19 at 21:14 +0200, Alexander Graf wrote:
> This patch adds a helper to search for a node's phandle by its path. This
> is especially useful when the phandle is part of an array, not just a single
> cell in which case qemu_devtree_setprop_phandle would be the easy choice.
>
> Signed
On Tue, 2012-06-19 at 21:14 +0200, Alexander Graf wrote:
> Phandles are the fancy device tree name for "pointer to another node".
> To create a phandle property, we most likely want to reference to the
> node we're pointing to by its path. So create a helper that allows
> us to do so.
>
> Signed-o
On Tue, 2012-06-19 at 21:14 +0200, Alexander Graf wrote:
> We have device tree helpers that allow us to create single cell (u32)
> wide properties. However, when creating properties that contain an array of
> cells, we need to jump through hoops, manually passing in an array with
> converted endian
Add OpenRISC system instructions.
Signed-off-by: Jia Liu
---
target-openrisc/Makefile.objs |3 +-
target-openrisc/helper.h |4 +
target-openrisc/sys_helper.c | 244 +
target-openrisc/translate.c | 10 ++
4 files changed, 260 insertions(+
Add QEMU OpenRISC linux user support.
Signed-off-by: Jia Liu
---
configure |1 +
default-configs/or32-linux-user.mak |1 +
linux-user/elfload.c| 41 +++
linux-user/main.c | 100 +++
linux-user/signal.c
Add OpenRISC timer support.
Signed-off-by: Jia Liu
---
hw/openrisc_timer.c | 130 +++
1 file changed, 130 insertions(+)
diff --git a/hw/openrisc_timer.c b/hw/openrisc_timer.c
index df384f6..25cde1a 100644
--- a/hw/openrisc_timer.c
+++ b/hw/openri
Add a IIS dummy board.
Signed-off-by: Jia Liu
---
hw/openrisc/Makefile.objs |2 +-
hw/openrisc_sim.c | 160 +
2 files changed, 161 insertions(+), 1 deletion(-)
create mode 100644 hw/openrisc_sim.c
diff --git a/hw/openrisc/Makefile.objs b
Add OpenRISC Programmable Interrupt Controller support.
Signed-off-by: Jia Liu
---
hw/openrisc_pic.c | 48
1 file changed, 48 insertions(+)
diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c
index 0d14bbe..76bd792 100644
--- a/hw/openrisc_pic.c
Add OpenRISC exception support.
Signed-off-by: Jia Liu
---
target-openrisc/Makefile.objs |4 ++--
target-openrisc/excp.c| 27 +++
target-openrisc/excp.h| 28
target-openrisc/excp_helper.c | 27
Add OpenRISC MMU support.
Signed-off-by: Jia Liu
---
target-openrisc/cpu.h| 75 +++-
target-openrisc/mmu.c| 199 +-
target-openrisc/mmu_helper.c | 20 +
3 files changed, 292 insertions(+), 2 deletions(-)
diff --git a/t
I am trying to compile the very last qemu with vfio_pci enabled. VFIO_PCI is
added as below:
./configure:
case "$target_arch2" in
i386|x86_64|ppc64)
if test "$vfio_pci" = "yes" -a "$target_softmmu" = "yes" ; then
echo "CONFIG_VFIO_PCI=y" >> $config_target_mak
fi
esac
./Mak
Add OpenRISC linux syscall, signal and termbits.
Signed-off-by: Jia Liu
---
linux-user/openrisc/syscall.h | 24 ++
linux-user/openrisc/syscall_nr.h| 506 +++
linux-user/openrisc/target_signal.h | 26 ++
linux-user/openrisc/termbits.h | 294 +++
Add OpenRISC float instruction helpers.
Signed-off-by: Jia Liu
---
target-openrisc/Makefile.objs |2 +-
target-openrisc/fpu_helper.c | 275 +
target-openrisc/helper.h | 33 +
3 files changed, 309 insertions(+), 1 deletion(-)
create mode 1
Add testcases for OpenRISC.
Signed-off-by: Jia Liu
---
tests/tcg/openrisc/Makefile | 71 +++
tests/tcg/openrisc/test_add.c| 34 +
tests/tcg/openrisc/test_addc.c | 39 +++
tests/tcg/openrisc/test_addi.c | 31
tests/
Add OpenRISC int instruction helpers.
Signed-off-by: Jia Liu
---
target-openrisc/Makefile.objs |2 +-
target-openrisc/helper.h |5 +++
target-openrisc/int_helper.c | 85 +
3 files changed, 91 insertions(+), 1 deletion(-)
create mode 100644
Add OpenRISC gdb stub support.
Signed-off-by: Jia Liu
---
gdbstub.c | 64 +
1 file changed, 64 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
index 08cf864..5d37dd9 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1155,6 +1155,68 @@ stat
Add OpenRISC instruction tanslation routines.
Signed-off-by: Jia Liu
---
target-openrisc/translate.c | 1676 +++
1 file changed, 1676 insertions(+)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 1d87d76..300236f 100644
--- a/
Add OpenRISC interrupt support.
Signed-off-by: Jia Liu
---
cpu-exec.c | 17 +
target-openrisc/Makefile.objs |2 +-
target-openrisc/cpu.h |9 ++-
target-openrisc/helper.h| 25 +++
target-openrisc/intrpt.c
Add OpenRISC target stubs and cpu support.
Signed-off-by: Jia Liu
---
arch_init.c |2 +
arch_init.h |1 +
configure| 14 +-
cpu-exec.c |2 +
default-configs/or32-softmmu.mak |4 +
elf.h
Add OpenRISC machine.
Signed-off-by: Jia Liu
---
target-openrisc/cpu.h | 67 -
target-openrisc/machine.c | 22 ++-
2 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 0
This is the OpenCores OpenRISC 1200 support for QEMU.
Full implementation of the system-model and linux-user-model support.
OpenRISC 1200 is a OpenCores open source CPU,
its architecture manual can be found at
http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf
A OpenRISC Linux ke
On Thu, 2012-06-21 at 11:45 +1000, David Gibson wrote:
> > Why should this be in the core API? Shouldn't this be a helper on
> > top of the DMA API?
>
> Well, I was hoping to avoid having to allocate a temporary buffer of
> zeroes, which is necessary to do this in terms of the existing
> cpu_phys
On Wed, Jun 20, 2012 at 04:16:47PM -0500, Anthony Liguori wrote:
[snip]
> >diff --git a/qemu-common.h b/qemu-common.h
> >index 8f87e41..80026af 100644
> >--- a/qemu-common.h
> >+++ b/qemu-common.h
> >@@ -264,6 +264,7 @@ typedef struct EventNotifier EventNotifier;
> > typedef struct VirtIODevice Vi
On Wed, Jun 20, 2012 at 04:15:13PM -0500, Anthony Liguori wrote:
> On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
> >From: David Gibson
> >
> >This patch adds cpu_physical_memory_set() function. This is equivalent to
> >calling cpu_physical_memory_write() with a buffer filled with a charact
On Thu, Jun 21, 2012 at 11:45:14AM +1000, David Gibson wrote:
> On Wed, Jun 20, 2012 at 04:15:13PM -0500, Anthony Liguori wrote:
> > On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
> > >From: David Gibson
> > >
> > >This patch adds cpu_physical_memory_set() function. This is equivalent to
>
On Wed, Jun 20, 2012 at 01:52:12PM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2012-06-20 at 13:14 +1000, David Gibson wrote:
> > So, in fact the original comment is a bit out of date. With the
> > current version of this series, then a guest attempt to invalidate
> > will be delayed until the
On Thu, Jun 21, 2012 at 07:29:23AM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2012-06-20 at 16:14 -0500, Anthony Liguori wrote:
>
> > Why not make life easy and fix dma_addr_t to 64-bit?
>
> No opinion on my side, that's from the original patch series, I suppose
> the goal was to avoid the ov
Hi Max,
On Thu, Jun 21, 2012 at 4:10 AM, Max Filippov wrote:
> Signed-off-by: Max Filippov
> ---
> default-configs/or32-softmmu.mak | 2 +-
> hw/openrisc_sim.c | 24 +++-
> 2 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/default-configs
Ping!
Id really appreciate some input on this issue (rather than going ahead
and doing it to discover that someone disagrees with the approach).
Regards,
Peter
On Mon, Jun 18, 2012 at 3:13 PM, Peter Crosthwaite
wrote:
> HI All,
>
> Have another one of these long RFCs for you all RE some QOM
> r
Ping!
We good to go on this one? Whose queue should this go in or should I PULL?
On Thu, Jun 14, 2012 at 12:12 PM, Peter Crosthwaite
wrote:
> ergh,
>
> series version number is incorrect, this is v4.
>
> On Thu, Jun 14, 2012 at 12:20 PM, Peter A. G. Crosthwaite
> wrote:
>> [Original cover by Ig
On 06/20/2012 06:10 PM, Alexander Graf wrote:
>
> On 21.06.2012, at 01:07, Scott Wood wrote:
>
>> On 06/20/2012 05:59 PM, Alexander Graf wrote:
>>>
>>> On 21.06.2012, at 00:26, Scott Wood wrote:
>>>
On 06/20/2012 03:11 PM, Alexander Graf wrote:
> +/* XXX better abstract into Emb.xxx
Hi!
As one of many people who was not even able to order a RPi yet, I gave
qemu a try to test my bare metal arm code at. Thanks so much for qemu,
it works great. Nevertheless I have to use one of the supported boards
(versatilepb in my case) to run my code and that means having to
compile differen
On 21.06.2012, at 01:07, Scott Wood wrote:
> On 06/20/2012 05:59 PM, Alexander Graf wrote:
>>
>> On 21.06.2012, at 00:26, Scott Wood wrote:
>>
>>> On 06/20/2012 03:11 PM, Alexander Graf wrote:
+/* XXX better abstract into Emb.xxx features */
+if (version == fsl_e5500) {
+
On 06/20/2012 05:59 PM, Alexander Graf wrote:
>
> On 21.06.2012, at 00:26, Scott Wood wrote:
>
>> On 06/20/2012 03:11 PM, Alexander Graf wrote:
>>> +/* XXX better abstract into Emb.xxx features */
>>> +if (version == fsl_e5500) {
>>> +spr_register(env, SPR_BOOKE_EPCR, "EPCR",
>>>
On 21.06.2012, at 00:26, Scott Wood wrote:
> On 06/20/2012 03:11 PM, Alexander Graf wrote:
>> +/* XXX better abstract into Emb.xxx features */
>> +if (version == fsl_e5500) {
>> +spr_register(env, SPR_BOOKE_EPCR, "EPCR",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> +
On 06/20/2012 05:26 PM, Peter Maydell wrote:
On 20 June 2012 22:14, Anthony Liguori wrote:
Why not make life easy and fix dma_addr_t to 64-bit?
...for that matter weren't we tossing around the idea of just
making target_phys_addr_t 64 bits for everything? (I actually
want to do this for targe
On 06/20/2012 03:11 PM, Alexander Graf wrote:
> +/* XXX better abstract into Emb.xxx features */
> +if (version == fsl_e5500) {
> +spr_register(env, SPR_BOOKE_EPCR, "EPCR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_gene
On 20 June 2012 22:14, Anthony Liguori wrote:
> Why not make life easy and fix dma_addr_t to 64-bit?
...for that matter weren't we tossing around the idea of just
making target_phys_addr_t 64 bits for everything? (I actually
want to do this for target-arm anyway; last time I did some
quick smoke-
On Wed, 2012-06-20 at 16:40 -0500, Anthony Liguori wrote:
> Well let's return void in the DMA methods and let the IOMMUs assert on error.
> At least that will avoid surprises until someone decides they care enough
> about
> errors to touch all callers.
>
> I think silently failing a memcpy() c
On 06/20/2012 04:40 PM, Michael S. Tsirkin wrote:
On Wed, Jun 20, 2012 at 04:16:47PM -0500, Anthony Liguori wrote:
diff --git a/qemu-common.h b/qemu-common.h
index 8f87e41..80026af 100644
--- a/qemu-common.h
+++ b/qemu-common.h
@@ -264,6 +264,7 @@ typedef struct EventNotifier EventNotifier;
ty
On Wed, Jun 20, 2012 at 04:46:49PM -0500, Anthony Liguori wrote:
> On 06/20/2012 04:42 PM, Michael S. Tsirkin wrote:
> >On Wed, Jun 20, 2012 at 04:38:30PM -0500, Anthony Liguori wrote:
> >>On 06/20/2012 04:32 PM, Michael S. Tsirkin wrote:
> >>>On Wed, Jun 20, 2012 at 04:16:47PM -0500, Anthony Liguo
On Wed, 2012-06-20 at 16:25 -0500, Anthony Liguori wrote:
> So this cancellation stuff is hopelessly broken
>
> It's simply not possible to fully cancel pending DMA in a synchronous
> callback.
Well, at least for PAPR H_PUT_TCE, cancellation must be synchronous, ie
the hypercall must not return
On 06/20/2012 04:42 PM, Michael S. Tsirkin wrote:
On Wed, Jun 20, 2012 at 04:38:30PM -0500, Anthony Liguori wrote:
On 06/20/2012 04:32 PM, Michael S. Tsirkin wrote:
On Wed, Jun 20, 2012 at 04:16:47PM -0500, Anthony Liguori wrote:
diff --git a/hw/pci.h b/hw/pci.h
index 7f223c0..ee669d9 100644
-
On Wed, Jun 20, 2012 at 04:38:30PM -0500, Anthony Liguori wrote:
> On 06/20/2012 04:32 PM, Michael S. Tsirkin wrote:
> >On Wed, Jun 20, 2012 at 04:16:47PM -0500, Anthony Liguori wrote:
> >>>diff --git a/hw/pci.h b/hw/pci.h
> >>>index 7f223c0..ee669d9 100644
> >>>--- a/hw/pci.h
> >>>+++ b/hw/pci.h
>
On 06/20/2012 04:36 PM, Benjamin Herrenschmidt wrote:
Cc: Gerd Hoffmann
Cc: Michael S. Tsirkin
Signed-off-by: David Gibson
Signed-off-by: Benjamin Herrenschmidt
So... the DMA api is designed to allow for partial result returns which I
presume an implementation would use as a simplification.
On Wed, Jun 20, 2012 at 04:16:47PM -0500, Anthony Liguori wrote:
> >diff --git a/qemu-common.h b/qemu-common.h
> >index 8f87e41..80026af 100644
> >--- a/qemu-common.h
> >+++ b/qemu-common.h
> >@@ -264,6 +264,7 @@ typedef struct EventNotifier EventNotifier;
> > typedef struct VirtIODevice VirtIODev
On 06/20/2012 04:32 PM, Michael S. Tsirkin wrote:
On Wed, Jun 20, 2012 at 04:16:47PM -0500, Anthony Liguori wrote:
diff --git a/hw/pci.h b/hw/pci.h
index 7f223c0..ee669d9 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -558,10 +558,16 @@ static inline uint32_t pci_config_size(const PCIDevice *d)
}
On 06/20/2012 04:30 PM, Benjamin Herrenschmidt wrote:
On Wed, 2012-06-20 at 16:15 -0500, Anthony Liguori wrote:
On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
From: David Gibson
This patch adds cpu_physical_memory_set() function. This is equivalent to
calling cpu_physical_memory_write(
On Wed, 2012-06-20 at 16:21 -0500, Anthony Liguori wrote:
> Again, you return an error but ignore it now.
>
> In the very least, on error you should scrub the passed in buffer to avoid
> leaking data to the guest.
>
> You can imagine a malicious guest programming the IOMMU with invalid mappings
> > Cc: Gerd Hoffmann
> > Cc: Michael S. Tsirkin
> >
> > Signed-off-by: David Gibson
> > Signed-off-by: Benjamin Herrenschmidt
>
>
> So... the DMA api is designed to allow for partial result returns which I
> presume an implementation would use as a simplification.
>
> But none of these caller
> > /* DMA access functions */
> > +static inline DMAContext *pci_dma_context(PCIDevice *dev)
> > +{
> > +/* Stub for when we have no PCI iommu support */
> > +return NULL;
> > +}
>
> Why is all of this stuff static inline?
Why not ? Not doing so is gratuitous bloat & overhead
> >
On Wed, Jun 20, 2012 at 04:16:47PM -0500, Anthony Liguori wrote:
> >diff --git a/hw/pci.h b/hw/pci.h
> >index 7f223c0..ee669d9 100644
> >--- a/hw/pci.h
> >+++ b/hw/pci.h
> >@@ -558,10 +558,16 @@ static inline uint32_t pci_config_size(const PCIDevice
> >*d)
> > }
> >
> > /* DMA access functions *
On Wed, 2012-06-20 at 16:15 -0500, Anthony Liguori wrote:
> On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
> > From: David Gibson
> >
> > This patch adds cpu_physical_memory_set() function. This is equivalent to
> > calling cpu_physical_memory_write() with a buffer filled with a character,
On 06/20/2012 01:59 AM, Amit Shah wrote:
The Linux kernel already has a virtio-rng driver, this is the device
implementation.
When the guest asks for entropy from the virtio hwrng, it puts a buffer
in the vq. We then put entropy into that buffer, and push it back to
the guest.
The chardev conn
On Wed, 2012-06-20 at 16:14 -0500, Anthony Liguori wrote:
> Why not make life easy and fix dma_addr_t to 64-bit?
No opinion on my side, that's from the original patch series, I suppose
the goal was to avoid the overhead/bloat on 32-bit only
platforms/targets.
Cheers,
Ben.
On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
From: David Gibson
One new complication raised by IOMMU support over only handling DMA
directly to physical addresses is handling dma_memory_map() case
(replacing cpu_physical_memory_map()) when the IOMMU translation the
IOVAs covered by such
On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
From: David Gibson
dma-helpers.c contains a number of helper functions for doing
scatter/gather DMA, and various block device related DMA. Currently,
these directly access guest memory using cpu_physical_memory_*(),
assuming no IOMMU transla
On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
From: David Gibson
The OHCI device emulation can provide both PCI and SysBus OHCI
implementations. Because of this, it was not previously converted to
use the PCI DMA helper functions.
This patch converts it to use the new universal DMA hel
On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
From: David Gibson
Not that long ago, every device implementation using DMA directly
accessed guest memory using cpu_physical_memory_*(). This meant that
adding support for a guest visible IOMMU would require changing every
one of these devi
On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
From: David Gibson
This patch adds cpu_physical_memory_set() function. This is equivalent to
calling cpu_physical_memory_write() with a buffer filled with a character,
ie, a memset of target memory.
It uses a small temporary buffer on the s
On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
From: David Gibson
A while back, we introduced the dma_addr_t type, which is supposed to
be used for bus visible memory addresses. At present, this is an
alias for target_phys_addr_t, but this will change when we eventually
add support for g
On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
This is a rebase of the iommu series and the barrier patch together
on top of current qemu.
As for our discussions about doing things with Memory Regions etc
I eventually came to the conclusion that we should just apply this
first :-)
My rea
Does it always crash with the same bug check code?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1014681
Title:
BSOD with newer host kernels (x64) and W2k8S guest (x64)
Status in QEMU:
New
Bug
This patch set adds support to emulate an e5500 based virtual machine. We don't
have a machine model for that one yet, but with this patch set applied we can
fake the compatibility property of the MPC8544DS model into P5020DS, which
gets guest kernels working for me.
The patch set is based on my r
Device trees usually have a node /compatible, which indicate which machine
type we're looking at. For quick prototyping, it can be very useful to change
the contents of that node via the command line.
Thus, introduce a new option to -machine called dt_compatible, which when
set changes the /compat
Introduce 'isa_setup_iommu()' to allow chipsets to associate an iommu mapping
function with the isa bus. This allows isa devices which sit behind an iommu
to be correctly configured. This is based on Benjamin Herrenschmidt's iommu
series. It has no consumers for now.
Signed-off-by: Jason Baron
--
Provide infastructure for iommu support to the existing isa dma engine. This
allows chipsets to support an iommu sitting between memory and the dma engine.
Code is layered on top of Benjamin Herrenschmidt's generic iommu infastructure.
In addition, the patch more tightly couples isa devices with t
(removed r...@hydra11.kio from CC)
On Tue, Jun 19, 2012 at 03:45:27PM -0700, Chegu Vinod wrote:
> From: root
>
> Changes since v1:
>
>
> - Use bitmap functions that are already in qemu (instead
>of cpu_set_t macro's)
> - Added a check for endvalue >= max_cpus.
> - Fix to
Recent u-boot has different defines for its gzip extract buffer, but the
common ground seems to be 64MB. So let's bump it up to that, enabling me
to load my test image again ;).
Signed-off-by: Alexander Graf
---
hw/loader.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --gi
Whatever we pass in to qemu_devtree_setprop to put into the device tree
will not get modified by that function, so it can easily be declared const.
Signed-off-by: Alexander Graf
---
device_tree.c |2 +-
device_tree.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
Some machines have MSR bits they reset with as enabled. Don't hardcode the
logic, but let the individual core implementations save their own reset
mask into an env variable.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h|1 +
target-ppc/translate_init.c | 14 --
This patch adds e5500's CPU initialization to the TCG CPU initialization
code.
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c | 104 +-
1 files changed, 101 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-pp
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to
support running 64bit code with MSR_CM set.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h |9 +
target-ppc/excp_helper.c |9 +
target-ppc/mem_helper.c |2 +-
target-ppc/transl
The number of SPRs avaiable in different PowerPC chip is still increasing. Add
definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a
Signed-off-by: Max Filippov
---
default-configs/or32-softmmu.mak |2 +-
hw/openrisc_sim.c| 24 +++-
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
index 7590eed..d85b82b
On the e500 series, accessing SPR_EPR magically turns into an access at
that CPU's IACK register on the MPIC. Implement that logic to get kernels
that make use of that feature work.
Signed-off-by: Alexander Graf
---
hw/ppce500_mpc8544ds.c |1 +
target-ppc/Makefile.objs |1 +
target-ppc
On Wed, 20 Jun 2012 14:47:14 -0500
Anthony Liguori wrote:
> > I'm not sure this is better because it suggests that all classes we have
> > today
> > are still valid.
>
> Yes, they are still valid. We cannot and should not change any of the error
> behavior we have today.
We can keep them and
There are several instances of 'typedef struct DMAContext DMAContext'. Remove
them
all except for the one in qemu-common.h.
Signed-off-by: Jason Baron
---
dma.h |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/dma.h b/dma.h
index 0d57e50..862373d 100644
--- a/dma.h
+
Hi,
Based on Benjamin Herrenschmidt's iommu series - these patches provide
infrastructure for a chipset topology where an iommu can sit between
main memory and the isa dma engine. The idea is remap addresses according
to the iommu's wish when we are performing a dma engine r/w operation.
Since th
On Wed, Jun 20, 2012 at 8:41 PM, Jia Liu wrote:
> Hi Max,
>
> On Wed, Jun 20, 2012 at 8:57 PM, Max Filippov wrote:
>> On Wed, Jun 20, 2012 at 1:42 PM, Jia Liu wrote:
>>> Hi Max,
>>>
>>> On Wed, Jun 20, 2012 at 2:29 PM, Max Filippov wrote:
On 06/18/2012 05:02 AM, Jia Liu wrote:
> Add a
hi,
same problem on centos 6.2 with vanilla kernel 3.4.2.
I compiled qemu 1.0.1 from source and qemu 1.1.0 from source.
/opt/qemu-1.0.1/bin/qemu-system-i386 -m 2048 -cdrom Win_XP_Pro_SP3.iso
-hda test.winXP.qcow2 : works
/opt/qemu-1.1.0/bin/qemu-system-i386 -m 2048 -cdrom Win_XP_Pro_SP3.iso
-
Hi,
I almost identical problem so i post here my comment.
I'm trying to use qemu 1.1.0 to run some vm on a RHEL5.8 _without_ kvm
accelaration
(the host have 24 cpu core, I can't install kvm module on the server, policy
problem,
but I still want to exploit some cpu power).
I compiled qemu 1.1.0 w
On 06/20/2012 02:40 PM, Luiz Capitulino wrote:
On Wed, 20 Jun 2012 13:46:08 -0500
Anthony Liguori wrote:
On 06/20/2012 12:48 PM, Luiz Capitulino wrote:
Yet another thread fork.
After talking with Daniel and Markus about QMP errors (which is not just about
QMP, as this affects QEMU as whole),
Extract out the ELF note size function from i386 so we can use it from
other targets.
Signed-off-by: Rabin Vincent
---
dump.c | 15 +++
dump.h |2 ++
target-i386/arch_dump.c | 14 ++
3 files changed, 19 insertions(+), 12 deletions
On Wed, 20 Jun 2012 13:46:08 -0500
Anthony Liguori wrote:
> On 06/20/2012 12:48 PM, Luiz Capitulino wrote:
> > Yet another thread fork.
> >
> > After talking with Daniel and Markus about QMP errors (which is not just
> > about
> > QMP, as this affects QEMU as whole), I've put together the propos
Add a minimal dump-guest-memory support for ARM. The -p option is not
supported and we don't add any QEMU-specific notes.
Signed-off-by: Rabin Vincent
---
configure|4 +--
target-arm/Makefile.objs |2 +-
target-arm/arch_dump.c | 59 +++
Hi,
I almost identical problem so i post here my comment.
I'm trying to use qemu 1.1.0 to run some vm on a RHEL5.8 _without_ kvm
accelaration
(the host have 24 cpu core, I can't install kvm module on the server, policy
problem,
but I still want to exploit some cpu power).
I compiled qemu 1.1.0
Make a common helper function to add ELF notes.
Signed-off-by: Rabin Vincent
---
dump.c | 49 +++
dump.h |4 +
target-i386/arch_dump.c | 206 +++
3 files changed, 100 insertions(+), 159 deletions(-)
dif
Make dump-guest-memory not create read-only files, so that it can
overwrite a file created by a previous invocation without having it to
be removed externally.
Signed-off-by: Rabin Vincent
---
dump.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/dump.c b/dump.c
index 2
On 06/20/2012 12:48 PM, Luiz Capitulino wrote:
Yet another thread fork.
After talking with Daniel and Markus about QMP errors (which is not just about
QMP, as this affects QEMU as whole), I've put together the proposal below.
I'll discuss three points. First, the error format and classes. Secon
On 06/15/2012 04:47 PM, Supriya Kannery wrote:
> New command "block_set_hostcache" added for dynamically changing
> host pagecache setting of a block device.
>
> Usage:
> block_set_hostcache
> = block device
> = on/off
>
> Example:
> (qemu) block_set_hostcache ide0-hd0 off
>
> Sig
Yet another thread fork.
After talking with Daniel and Markus about QMP errors (which is not just about
QMP, as this affects QEMU as whole), I've put together the proposal below.
I'll discuss three points. First, the error format and classes. Second, the
internal API and third compatibility.
Don
This is v2, obviously -- I forgot to change the [PATCH] prefix :-(
-- PMM
On 20 June 2012 18:02, Peter Maydell wrote:
> Now we create object files in a hierarchy under hw/, so the
> 'clean' target must also be updated to delete those object files.
> Rather than using a manual list of subdirector
Now we create object files in a hierarchy under hw/, so the
'clean' target must also be updated to delete those object files.
Rather than using a manual list of subdirectories which will
easily drift out of date, we just delete all .o and .d files
in the target directory hierarchy.
Signed-off-by:
Hi Max,
On Wed, Jun 20, 2012 at 8:57 PM, Max Filippov wrote:
> On Wed, Jun 20, 2012 at 1:42 PM, Jia Liu wrote:
>> Hi Max,
>>
>> On Wed, Jun 20, 2012 at 2:29 PM, Max Filippov wrote:
>>> On 06/18/2012 05:02 AM, Jia Liu wrote:
Add a dummy board for IIS.
Signed-off-by: Jia Liu
>>>
>>
On 14 June 2012 16:14, Andreas Färber wrote:
> Commit ec5b06d (configure: ensure directory exists when creating symlinks)
> moved the creation of directories into the symlink() function but forgot
> the case where no symlink is created.
>
> This leads to build errors on arm Linux due to -I../linux
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