On 05/15/12 03:23, Anthony Liguori wrote:
> On 05/14/2012 08:03 PM, q...@buildbot.b1-systems.de wrote:
>> The Buildbot has detected a new failure on builder default_i386_rhel61
>> while building qemu.
>> Full details are available at:
>>
>> http://buildbot.b1-systems.de/qemu/builders/default_i386
Am 15.05.2012 07:33, schrieb Stefan Weil:
Am 15.05.2012 07:27, schrieb Stefan Weil:
When QEMU was built with the simple trace backend, linking failed:
LINK tests/fdc-test oslib-posix.o: In function `trace_qemu_memalign':
qemu/bin/debug/x86/./trace.h:31: undefined reference to `trace3'
oslib-po
Am 15.05.2012 07:27, schrieb Stefan Weil:
When QEMU was built with the simple trace backend, linking failed:
LINK tests/fdc-test oslib-posix.o: In function `trace_qemu_memalign':
qemu/bin/debug/x86/./trace.h:31: undefined reference to `trace3'
oslib-posix.o: In function `trace_qemu_vmalloc':
q
When QEMU was built with the simple trace backend, linking failed:
LINK tests/fdc-test
oslib-posix.o: In function `trace_qemu_memalign':
qemu/bin/debug/x86/./trace.h:31: undefined reference to `trace3'
oslib-posix.o: In function `trace_qemu_vmalloc':
qemu/bin/debug/x86/./trace.h:35: undefined r
On Monday, May 14, 2012 08:23:04 PM Anthony Liguori wrote:
> On 05/14/2012 08:03 PM, q...@buildbot.b1-systems.de wrote:
> > The Buildbot has detected a new failure on builder default_i386_rhel61
> > while building qemu.>
> > Full details are available at:
> > http://buildbot.b1-systems.de/qemu/bu
Thanks for your reply.
As you say, for an input visitor we dont need to initialize the pointer.
"visit_type_str" in set_mac function and set_pci_devfn function is a input
visitor, it points to
"qmp_input_type_str", if qmp_input_type_str failed, it will alloc a Error
struct and return.
So, i think
On Mon, 2012-05-14 at 21:50 -0500, Anthony Liguori wrote:
> On 05/14/2012 09:32 PM, Benjamin Herrenschmidt wrote:
> > On Mon, 2012-05-14 at 21:03 -0500, Anthony Liguori wrote:
> >> So the CPU thread runs in lock-step with the I/O thread. Dropping the CPU
> >> thread lock to let the I/O thread run
On 05/14/2012 09:32 PM, Benjamin Herrenschmidt wrote:
On Mon, 2012-05-14 at 21:03 -0500, Anthony Liguori wrote:
So the CPU thread runs in lock-step with the I/O thread. Dropping the CPU
thread lock to let the I/O thread run is a dangerous thing to do in a place like
this.
Also, I think you'd e
On Mon, 2012-05-14 at 21:03 -0500, Anthony Liguori wrote:
> So the CPU thread runs in lock-step with the I/O thread. Dropping the CPU
> thread lock to let the I/O thread run is a dangerous thing to do in a place
> like
> this.
>
> Also, I think you'd effectively block the CPU until pending DMA
On 05/14/2012 08:23 PM, David Gibson wrote:
On Mon, May 14, 2012 at 07:42:00PM -0500, Anthony Liguori wrote:
On 05/09/2012 11:48 PM, Benjamin Herrenschmidt wrote:
From: David Gibson
[snip]
@@ -3581,6 +3581,59 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
uint8_t *buf,
}
}
On 05/14/2012 08:42 PM, David Gibson wrote:
On Mon, May 14, 2012 at 07:49:16PM -0500, Anthony Liguori wrote:
[snip]
+void iommu_wait_for_invalidated_maps(DMAContext *dma,
+ dma_addr_t addr, dma_addr_t len)
+{
+DMAMemoryMap *map;
+DMAInvalidationState i
On Mon, May 14, 2012 at 07:52:15PM -0500, Anthony Liguori wrote:
> On 05/09/2012 11:49 PM, Benjamin Herrenschmidt wrote:
> >From: David Gibson
> >
> >The emulated devices can run simultaneously with the guest, so
> >we need to be careful with ordering of load and stores done by
> >them to the guest
On Mon, May 14, 2012 at 03:35:23PM +0300, Gleb Natapov wrote:
> QEMU may want to disable guest's S3/S4 support and it wants to distinguish
> between regular powerdown and S4 powerdown. To support that new fw_cfg
> option was added that passes supported system states and what value should
> guest us
On Mon, May 14, 2012 at 07:49:16PM -0500, Anthony Liguori wrote:
[snip]
> >+void iommu_wait_for_invalidated_maps(DMAContext *dma,
> >+ dma_addr_t addr, dma_addr_t len)
> >+{
> >+DMAMemoryMap *map;
> >+DMAInvalidationState is;
> >+
> >+is.count = 0;
>
On Mon, May 14, 2012 at 07:42:00PM -0500, Anthony Liguori wrote:
> On 05/09/2012 11:48 PM, Benjamin Herrenschmidt wrote:
> >From: David Gibson
[snip]
> >@@ -3581,6 +3581,59 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
> >uint8_t *buf,
> > }
> > }
> >
> >+void cpu_physical_memory_z
On 05/14/2012 08:03 PM, q...@buildbot.b1-systems.de wrote:
The Buildbot has detected a new failure on builder default_i386_rhel61 while
building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_i386_rhel61/builds/263
Buildbot URL: http://buildbot.b1-sys
On Mon, 2012-05-14 at 19:52 -0500, Anthony Liguori wrote:
> >
> > diff --git a/dma-helpers.c b/dma-helpers.c
> > index 36fa963..4350cdf 100644
> > --- a/dma-helpers.c
> > +++ b/dma-helpers.c
> > @@ -312,6 +312,9 @@ int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t
> > addr,
> > buf +=
The Buildbot has detected a new failure on builder default_x86_64_rhel61 while
building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_x86_64_rhel61/builds/264
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: kraxel_rhel61
B
The Buildbot has detected a new failure on builder default_x86_64_fedora16
while building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_x86_64_fedora16/builds/260
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: kraxel_fedor
The Buildbot has detected a new failure on builder default_i386_rhel61 while
building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_i386_rhel61/builds/263
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: kraxel_rhel61_32bit
On 05/09/2012 11:48 PM, Benjamin Herrenschmidt wrote:
Hi folks !
This is a repose (& rebase on top of current HEAD) of
David and Eduard iommu patch series which provides the
necessary infrastructure for doing DMA through an iommu,
along with the SPAPR iommu implementation.
David is on vacation
On 05/09/2012 11:49 PM, Benjamin Herrenschmidt wrote:
From: David Gibson
The emulated devices can run simultaneously with the guest, so
we need to be careful with ordering of load and stores done by
them to the guest system memory, which need to be observed in
the right order by the guest operat
On Mon, 2012-05-14 at 16:02 -0600, Bjorn Helgaas wrote:
> On Fri, May 11, 2012 at 4:56 PM, Alex Williamson
> wrote:
> > In a PCIe environment, transactions aren't always required to
> > reach the root bus before being re-routed. Peer-to-peer DMA
> > may actually not be seen by the IOMMU in these
On 05/09/2012 11:49 PM, Benjamin Herrenschmidt wrote:
From: David Gibson
This patch adds the basic infrastructure necessary to emulate an IOMMU
visible to the guest. The DMAContext structure is extended with
information and a callback describing the translation, and the various
DMA functions us
On 05/09/2012 11:48 PM, Benjamin Herrenschmidt wrote:
From: David Gibson
This patch adds cpu_physical_memory_zero() function. This is equivalent to
calling cpu_physical_memory_write() with a buffer full of zeroes, but
avoids actually allocating such a buffer along the way.
Signed-off-by: David
The Buildbot has detected a new failure on builder default_x86_64_rhel5 while
building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_x86_64_rhel5/builds/248
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: kraxel_rhel5
Buil
The Buildbot has detected a new failure on builder default_s390 while building
qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_s390/builds/239
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: qemu-s390.opensuse.org
Build Reas
On Mon, May 14, 2012 at 03:25:20PM -0300, Luiz Capitulino wrote:
> POSIX mandates[1] that a child process of a multi-thread program uses
> only async-signal-safe functions before exec(). We consider qemu-ga
> to be multi-thread, because it uses glib.
>
> However, qmp_guest_shutdown() uses function
On Fri, May 11, 2012 at 4:56 PM, Alex Williamson
wrote:
> In a PCIe environment, transactions aren't always required to
> reach the root bus before being re-routed. Peer-to-peer DMA
> may actually not be seen by the IOMMU in these cases. For
> IOMMU groups, we want to provide IOMMU drivers a way
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index dc25da3..b437225 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -770,6 +770,14 @@ static inline int pci_write_config_dword(const struct
> pci_dev *dev, int where,
> return pci_bus_write_config_dword(dev->b
Stefan Weil wrote:
Am 14.05.2012 22:12, schrieb Erik Rull:
Hi all,
is there a guideline or manual how to send a patch to the qemu mailing
list? It seems as if this can be done somehow automagically using the
local git repository, but I didn't find a tool to do that.
Thanks!
Best regards,
Eri
Previously qemu-ga version was defined seperately. Since it is aligned
with QEMU releases, use QEMU_VERSION instead. This also implies the
version bump for 1.1[-rcN] release of qemu-ga.
Signed-off-by: Michael Roth
---
qemu-ga.c |4 ++--
qga/commands.c |2 +-
qga/gues
Currently, if we fail to open the specified log file (generally due to a
permissions issue), we'll assign NULL to the logfile handle (stderr,
initially) used by the logging routines, which can cause a segfault to
occur when we attempt to report the error before exiting.
Instead, only re-assign if
Am 13.05.2012 23:04, schrieb Blue Swirl:
> A preview of x86 AREG0 patches can be found at the usual place:
> URL git://repo.or.cz/qemu/blueswirl.git
> http://repo.or.cz/r/qemu/blueswirl.git
It looks like that push has completely replaced your pending ppc conversion?
If someone needs it fo
Am 14.05.2012 22:25, schrieb Max Filippov:
> On Thu, May 10, 2012 at 4:10 AM, Andreas Färber wrote:
>> Hello,
>>
>> Based on my CPUState patches for 1.1 (qom-cpu-1.1) this series kills off the
>> cpu_state_reset() function, which had been renamed as an interim solution
>> to free the identifier "c
This series is another major milestone of merging qemu-kvm into
upstream. It implements the required interfaces and logic to directly
inject MSI-X interrupts generated by the vhost-net kernel module into
the KVM in-kernel irqchip. This involves
- establishing MSI vector notifiers, so far triggered
Analogously to msi_nr_vectors_allocated, add a service for MSI-X. Will
be used by the virtio-pci layer.
Signed-off-by: Jan Kiszka
---
hw/msix.c |5 +
hw/msix.h |2 ++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/msix.c b/hw/msix.c
index c6968aa..2114b99 100644
--
Convert TLS registers to the new cp15 framework
Signed-off-by: Peter Maydell
---
target-arm/helper.c| 19 +++
target-arm/translate.c | 58
2 files changed, 19 insertions(+), 58 deletions(-)
diff --git a/target-arm/helper.c b/t
In preparation of firing vector notifiers on mask changes, call
msix_handle_mask_update also from msix_mask_all. So far, this will have
no real effect.
Signed-off-by: Jan Kiszka
---
hw/msix.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/hw/msix.c b/hw/msix.c
index
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to
use arm_cp_reginfo.
Signed-off-by: Peter Maydell
---
target-arm/helper.c| 54 --
target-arm/helper.h|2 -
target-arm/translate.c | 66
3 fi
Automatically commit route changes after kvm_add_routing_entry and
kvm_irqchip_release_virq. There is no performance relevant use case for
which collecting multiple route changes is beneficial. This makes
kvm_irqchip_commit_routes an internal service which assert()s that the
corresponding IOCTL wil
Make the 11MPCore report a valid value in its cache type register
(the previous value appears to have been incorrectly copied from
the 1136/1176). In particular, do not report that we have an
aliasing VIPT cache, because this causes Linux to attempt to use
the v6 block cache ops which the 11MPCore
Am 02.05.2012 13:30, schrieb Paolo Bonzini:
> The class_base_init TypeInfo callback was present in one of the early
> QOM versions but removed (on my request...) before committing. We
> will need it soon, add it.
>
> Signed-off-by: Paolo Bonzini
Anthony had added a Reviewed-by to v1.
Thanks, a
We will add kvm_irqchip_add_msi_route, so let's make the difference
clearer.
Signed-off-by: Jan Kiszka
---
hw/pc_piix.c |8
kvm-all.c|2 +-
kvm.h|2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 6a75718..c17f9
This allows to drop routes created by kvm_irqchip_add_irq/msi_route
again.
Signed-off-by: Jan Kiszka
---
kvm-all.c |8
kvm-stub.c |4
kvm.h |1 +
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/kvm-all.c b/kvm-all.c
index f45b852..e3ffc91 100644
---
Keys for MS-Windows Keyboards (left / right Win Key, Context Key) were not
working in SDL / VNC environments, this patch fixes it.
Signed-off-by: Erik Rull
---
ui/x_keymap.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/ui/x_keymap.c b/ui/x_keymap.c
index b9b094
Stefan Weil wrote:
Am 14.05.2012 23:10, schrieb Erik Rull:
Eric Blake wrote:
On 05/14/2012 02:58 PM, Anthony Liguori wrote:
You can also do:
git send-email --to=qemu-devel@nongnu.org HEAD~1
Which avoids any clutter.
I also like to do:
git config sendemail.to=qemu-devel@nongnu.org
so I do
Vector notifiers shall be triggered by the MSI/MSI-X core whenever a
relevant configuration change is programmed by the guest. In case of
MSI-X, changes are reported when the effective mask (global &&
per-vector) alters its state. On unmask, the current vector
configuration is included in the event
Provide a dummy kvm_kernel_irqchip so that kvm_irqchip_in_kernel can be
used by code that is not under CONFIG_KVM protection.
Signed-off-by: Jan Kiszka
---
kvm-stub.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/kvm-stub.c b/kvm-stub.c
index b4cf03f..ec9a364 100644
--
On Mon, May 14, 2012 at 8:59 PM, Andreas Färber wrote:
> Am 14.05.2012 21:54, schrieb Blue Swirl:
>> On Mon, May 14, 2012 at 4:15 PM, Andreas Färber wrote:
>>> Am 10.05.2012 02:13, schrieb Andreas Färber:
Andreas Färber (74):
>>> [...]
target-sparc: Let cpu_sparc_init() return SPARCCP
Am 14.05.2012 23:10, schrieb Erik Rull:
Eric Blake wrote:
On 05/14/2012 02:58 PM, Anthony Liguori wrote:
You can also do:
git send-email --to=qemu-devel@nongnu.org HEAD~1
Which avoids any clutter.
I also like to do:
git config sendemail.to=qemu-devel@nongnu.org
so I don't have to remember
Eric Blake wrote:
On 05/14/2012 02:58 PM, Anthony Liguori wrote:
You can also do:
git send-email --to=qemu-devel@nongnu.org HEAD~1
Which avoids any clutter.
I also like to do:
git config sendemail.to=qemu-devel@nongnu.org
so I don't have to remember to use --to every time.
'git send-email
Convert cp15 MMU TLB control (crn=8) to new scheme.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 63 ++
1 files changed, 43 insertions(+), 20 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c371224..d57f943 10
Convert the (dummy) generic timer cp15 implementation.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 23 +++
1 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 88f7ca7..a92bbc7 100644
--- a/target-arm/he
Make use of the new vector notifier to track changes of the MSI-X
configuration of virtio PCI devices. On enabling events, we establish
the required virtual IRQ to MSI-X message route and link the signaling
eventfd file descriptor to this vIRQ line. That way, vhost-generated
interrupts can be direc
Am 14.05.2012 22:53, schrieb Peter Maydell:
On 14 May 2012 21:30, Stefan Weil wrote:
if you use git for sending, you don't risk that your mailer destroys the
format of your patch.
I usually use these commands to send a single patch from the QEMU source
directory:
# Create the patch fil
Remove the no-longer-used CPUARMState c0_cachetype field.
Although this was a constant register we had it in our
migration state. Drop this (with resulting version bump)
because for ARM currently we prefer cleaner migration
code and have not stabilised migration format yet.
Signed-off-by: Peter Ma
Am 14.05.2012 23:06, schrieb Erik Rull:
Thanks!
So I started a git pull to get the latest master and as well a git
reset --hard to assert that there are no modifications remaining.
Then I modified the file ui/x_keymap.c and called then the
git format-patch HEAD^
But I get 3 patches that are
Add services to associate an eventfd file descriptor as input with an
IRQ line as output. Such a line can be an input pin of an in-kernel
irqchip or a virtual line returned by kvm_irqchip_add_route.
Signed-off-by: Jan Kiszka
---
kvm-all.c | 30 ++
kvm-stub.c | 10
Add a service that establishes a static route from a virtual IRQ line to
an MSI message. Will be used for IRQFD and device assignment. As we will
use this service outside of CONFIG_KVM protected code, stub it properly.
Signed-off-by: Jan Kiszka
---
kvm-all.c | 31 +
Am 14.05.2012 22:58, schrieb Anthony Liguori:
On 05/14/2012 03:53 PM, Peter Maydell wrote:
On 14 May 2012 21:30, Stefan Weil wrote:
if you use git for sending, you don't risk that your mailer destroys
the
format of your patch.
I usually use these commands to send a single patch from the QEMU
This helper will also be used by the upcoming config notifier.
Signed-off-by: Jan Kiszka
---
hw/msix.c | 19 +--
1 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/hw/msix.c b/hw/msix.c
index 3835eaa..3197465 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -35,6 +35,15 @
All the users of cpu_arm_set_cp_io have been converted, so we
can remove it and the infrastructure it used.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h | 10
target-arm/helper.c| 54
target-arm/helper.h|3 --
t
Hi,
While working on the AREG0 patches, I noticed strange code in
target-i386/translate.c.
We have this table of function pointers:
static void *sse_op_table3[4 * 3] = {
gen_helper_cvtsi2ss,
gen_helper_cvtsi2sd,
X86_64_ONLY(gen_helper_cvtsq2ss),
X86_64_ONLY(gen_helper_cvtsq2sd),
On 05/14/2012 02:58 PM, Anthony Liguori wrote:
> You can also do:
>
> git send-email --to=qemu-devel@nongnu.org HEAD~1
>
> Which avoids any clutter.
I also like to do:
git config sendemail.to=qemu-devel@nongnu.org
so I don't have to remember to use --to every time.
'git send-email --cover-let
All the uses of ARM_CPUID() to vary behaviour have now been
removed, so we can delete the ARM_CPUID_* macros now.
The one exception is the TI915T/925T, because of its odd behaviour
where the MIDR value can be changed at runtime.
Signed-off-by: Peter Maydell
---
linux-user/cpu-uname.c |5 +---
Am 14.05.2012 21:54, schrieb Blue Swirl:
> On Mon, May 14, 2012 at 4:15 PM, Andreas Färber wrote:
>> Am 10.05.2012 02:13, schrieb Andreas Färber:
>>> Andreas Färber (74):
>> [...]
>>> target-sparc: Let cpu_sparc_init() return SPARCCPU
>>> sun4m: Use cpu_sparc_init() to obtain SPARCCPU
>>> su
Convert the MMU fault status and MPU access permission cp15
registers to the new scheme.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 188 +--
1 files changed, 107 insertions(+), 81 deletions(-)
diff --git a/target-arm/helper.c b/target
Convert the cp15 c3 register (MMU domain access control
or MPU write buffer control). NB that this is horribly
underdecoded for modern cores (should be crn=3,crm=0,
opc1=0,opc2=0) but this change preserves the existing
QEMU behaviour.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 18 +
On 05/14/2012 03:53 PM, Peter Maydell wrote:
On 14 May 2012 21:30, Stefan Weil wrote:
if you use git for sending, you don't risk that your mailer destroys the
format of your patch.
I usually use these commands to send a single patch from the QEMU source
directory:
# Create the patch file (
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.
Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is
a change from previous behaviour, but a return to the behaviour of commit
c3d2689d when OMAP1 support was first added -- subsequent commits have
clea
Convert the cp15 cache ID registers to the new scheme.
Signed-off-by: Peter Maydell
---
target-arm/cpu.c|2 -
target-arm/cpu.h|2 -
target-arm/helper.c | 61 +++---
3 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/targ
On Mon, 14 May 2012, Andreas F?rber wrote:
> Am 12.05.2012 03:16, schrieb Andreas F?rber:
> > Here's patches to optimize and fix potential AREG0 issues on ppc64.
> >
> > So far I've only tested on Darwin/ppc64 - Debian/sparc, HelenOS/sparc64,
> > Haiku/i386, Haiku/x86_64 guests work.
>
> I've no
On 14 May 2012 21:30, Stefan Weil wrote:
> if you use git for sending, you don't risk that your mailer destroys the
> format of your patch.
> I usually use these commands to send a single patch from the QEMU source
> directory:
>
> # Create the patch file (name depends on the subject line of yo
On Mon, 14 May 2012, Roger Pau Monne wrote:
> malc escribi?:
> > On Fri, 11 May 2012, Roger Pau Monne wrote:
> >
> > > This is a bug fix for rc1, although I think this bug has been present
> > > for a long time.
> >
> > If there's a bug than it's within NetBSD itself, this issue has been
> > dis
Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.
Signed-off-by: Peter Maydell
---
target-arm/helper.c|
Convert the cp15 crn=1 registers to the new scheme.
Signed-off-by: Peter Maydell
---
target-arm/cpu-qom.h |1 +
target-arm/cpu.c |7 ++-
target-arm/helper.c | 129 +-
3 files changed, 61 insertions(+), 76 deletions(-)
diff --git a/ta
Convert the cp15 VA-PA translation registers (a subset of
the crn=7 regs) to the new scheme.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 108 ++
1 files changed, 65 insertions(+), 43 deletions(-)
diff --git a/target-arm/helper.c b/targ
Initial infrastructure for data-driven registration of
coprocessor register implementations.
We still fall back to the old-style switch statements pending
complete conversion of all existing registers.
Signed-off-by: Peter Maydell
---
target-arm/cpu-qom.h |3 +
target-arm/cpu.c |
Convert the various WFI and barrier instruction special cases to use
cp_reginfo infrastructure.
Signed-off-by: Peter Maydell
---
target-arm/helper.c| 42 +++
target-arm/translate.c | 51
2 files changed,
Convert the final ID registers to the new cp15 scheme.
Signed-off-by: Peter Maydell
---
target-arm/cpu.c|2 -
target-arm/helper.c | 116 ++-
2 files changed, 68 insertions(+), 50 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu
On Mon, May 14, 2012 at 09:36:36PM +0200, Stefan Weil wrote:
> Hello,
>
> Am 03.05.2012 10:34, schrieb dunrong huang:
> >The str allocated in visit_type_str was not freed
> >
> >Signed-off-by: dunrong huang
> >---
> >hw/qdev-properties.c | 8 ++--
> >1 files changed, 6 insertions(+), 2 deletio
Am 09.05.2012 17:12, schrieb Jim Meyering:
These were identified using: http://github.com/lyda/misspell-check
and run like this to create a bourne shell script using GNU sed's
-i option:
git ls-files|grep -vF .bin | misspellings -f - |grep -v '^ERROR:' |perl \
-pe 's/^(.*?)\[(\d+)\]: (\w+) -> "
Convert the v7 performance monitor cp15 registers to
the new scheme.
Signed-off-by: Peter Maydell
---
target-arm/cpu.c |4 -
target-arm/helper.c| 277 +++-
target-arm/translate.c | 26 +-
3 files changed, 158 insertions(+), 149 del
Convert the cp15 crn=7 registers to the new scheme.
Note that to do this we have to distinguish some registers
used on the ARM9 and ARM10 from some which are ARM1176
only. This is because the old code returned a value of 0
but always set the Z flag (by clearing env->ZF, since we
store the Z flag in
Convert the MPIDR to the new cp15 register scheme.
This includes giving it its own feature bit rather
than doing a CPUID value check.
Signed-off-by: Peter Maydell
---
target-arm/cpu.c|2 ++
target-arm/cpu.h|1 +
target-arm/helper.c | 50 -
Am 14.05.2012 22:12, schrieb Erik Rull:
Hi all,
is there a guideline or manual how to send a patch to the qemu mailing
list? It seems as if this can be done somehow automagically using the
local git repository, but I didn't find a tool to do that.
Thanks!
Best regards,
Erik
Hi Erik,
if
On Thu, May 10, 2012 at 4:10 AM, Andreas Färber wrote:
> Hello,
>
> Based on my CPUState patches for 1.1 (qom-cpu-1.1) this series kills off the
> cpu_state_reset() function, which had been renamed as an interim solution
> to free the identifier "cpu_reset" for QOM.
For the xtensa part: Acked-by:
Convert the cp15 crn=15 (implementation specific) registers
to the new scheme.
Signed-off-by: Peter Maydell
---
target-arm/cpu.c| 40 ++-
target-arm/cpu.h|1 +
target-arm/helper.c | 202 ++-
3 files changed, 126 insertions(+)
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the
cp_reginfo scheme.
Signed-off-by: Peter Maydell
---
target-arm/helper.c| 25 +
target-arm/translate.c | 28
2 files changed, 25 insertions(+), 28 deletions(-)
diff --
Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.
Signed-off-by: Peter Maydell
---
target-arm/cpu.c| 14 ---
target-arm/cpu.h|2 -
target-arm/helper.c | 62 --
3 files changed, 54 insertions(+)
Hi all,
is there a guideline or manual how to send a patch to the qemu mailing
list? It seems as if this can be done somehow automagically using the local
git repository, but I didn't find a tool to do that.
Thanks!
Best regards,
Erik
On 05/02/2012 06:30 AM, Paolo Bonzini wrote:
Since most property types do not have a parse property now, this was
broken. Fix it by looking at the setter instead.
Signed-off-by: Paolo Bonzini
Applied. Thanks.
Regards,
Anthony Liguori
---
hw/qdev-monitor.c |4 ++--
1 file changed,
On 05/14/2012 08:25 AM, Luiz Capitulino wrote:
Only patch, from Michael, that fixes a bug in the QMP input visitor.
The changes (since 94d1991445fa3582c042ee4e5b72606e2fc39cc2) are available
in the following repository:
git://repo.or.cz/qemu/qmp-unstable.git queue/qmp
Pulled. Thanks.
R
On 05/14/2012 10:44 AM, Kevin Wolf wrote:
The following changes since commit 77f4c9a68aedb9b0d290a1def1bfc8714be862ec:
Merge remote-tracking branch 'origin/master' into staging (2012-05-14
08:44:32 -0500)
are available in the git repository at:
git://repo.or.cz/qemu/kevin.git for-anthon
On 05/14/2012 03:29 AM, Gerd Hoffmann wrote:
Hi,
One little usb bugfix for 1.1 ...
please pull,
Gerd
Pulled. Thanks.
Regards,
Anthony Liguori
Gerd Hoffmann (1):
usb-host: handle guest-issued clear halt
hw/usb/host-linux.c |9 +
1 files changed, 9 insertions(+),
On 05/13/2012 01:27 PM, Andreas Färber wrote:
Hello Anthony,
Please pull the following patches cherry-picked from various QOM-related series.
I've dropped Paolo's "Fix -device foo,?" since you already had that queued.
QMP patches will be handled by Luiz.
Cc: Anthony Liguori
If there's other QO
On 05/14/2012 03:25 AM, Gerd Hoffmann wrote:
Hi,
Single little bugfix for 1.1 ...
please pull,
Gerd
Pulled. Thanks.
Regards,
Anthony Liguori
The following changes since commit 94d1991445fa3582c042ee4e5b72606e2fc39cc2:
sun4u: implement interrupt clearing registers (2012-05-12 0
On 05/14/2012 12:39 AM, Stefan Weil wrote:
Hello Anthony,
here are some patches with bug fixes for 1.1.
Pulled. Thanks.
Regards,
Anthony Liguori
Regards,
Stefan W.
The following changes since commit 94d1991445fa3582c042ee4e5b72606e2fc39cc2:
sun4u: implement interrupt clearing registe
On 05/14/2012 01:59 PM, Luiz Capitulino wrote:
I'll declare it then.
>>>
>>> -Wredundant-decls doesn't like it:
>>>
>>> /home/lcapitulino/work/src/qmp-unstable/qga/commands-posix.c:38:15:
>>> warning: redundant redeclaration of ‘environ’ [-Wredundant-decls]
>>> /usr/include/unistd.h:546:15: n
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