Hi,
Just for the record: if I remove the VGA card from the qemu pci bus I
can successfully boot a linux 2.6 kernel with serial console. Apparently
there's something wrong with it.
If you want to discuss please CC me.
johannes
signature.asc
Description: This is a digitally signed message part
_
On 14 mai 05, at 20:15, J. Mayer wrote:
Qemu assume all reserved fields are set to zero, not 1.
PowerPC specifications says: (section 8.1 of PEM)
"Some instructions fields are reserved or must contain a predefined
value as shown in the individual instruction layouts. If a reserved
field does not h
On Sat, 2005-05-14 at 19:20 +0200, Pierre d'Herbemont wrote:
> Hi,
>
> I have been playing with ppc-darwin-user. And I have to say that qemu-
> ppc is too strict with ppc opcode validity:
> On Mac OS X binary release called Tiger (or 10.4), the __bzero
> function [1] contains a mtcrf, which has
Hi,
I have been playing with ppc-darwin-user. And I have to say that qemu-
ppc is too strict with ppc opcode validity:
On Mac OS X binary release called Tiger (or 10.4), the __bzero
function [1] contains a mtcrf, which has been translated to
0x7c901120, by Apple's as. Current qemu rejects it,
On Sat, 2005-05-14 at 14:16 +0200, Fabrice Bellard wrote:
...
> 2) The first implementation would use a cycle counter to schedule
> between CPUs. Is it interesting to go further and to use a host thread
> for each guest CPU at the expense of more locking overhead ?
What inter processor synchroni
I guess you'd really want to simulate multiple CPUs with multiple host
threads. One of the additional problems could then be memory/cache
coherency.
I'm not sure how much of a problem this would be in practice. If both host
and guest require the same (or no) explicit SMP memory barriert it's not a
SMP est definitely possible in QEMU - a few days of work are necessary to
add the missing generic support and an x86 implementation... but currently
I prefer to work an other topics.
Just for your information, some choices need to be made:
1) Do the CPUs share the same translation cache ?
This c
On 14 May 2005, at 14:16, Fabrice Bellard wrote:
1) Do the CPUs share the same translation cache ?
2) The first implementation would use a cycle counter to schedule
between CPUs. Is it interesting to go further and to use a host
thread for each guest CPU at the expense of more locking overhead
Blue Swirl wrote:
Hi,
The architecture used in sparc target (sun4m) supports SMP up to a
maximum of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*),
it would be easy to add the missing interprocessor interrupts, per-CPU
counters and atomic instructions. It would also be simple to add
Hi.
I am new to qemu, but I was quite successful with it so far.
I have also seen some glitches, so I would like to share
my experience.
My system:
i430VX chipset, Pentium I 200MMX, 48MB RAM, S3virge card
Slackware 9.1, kernel 2.4.22 (custom compiled), glibc 2.3.2
I run qemu with the options '-hda
Paul Brook wrote:
In addition to this patch I also needed the attached patch to get MinGW
GCC 3.4.1 builds working...
...
-if (strstart(sym_name, "__op_label", &p)) {
+if (strstart(sym_name, "__op_label", &p) ||
+strstart(sym_name, "_op_label", &p
On Saturday 14 May 2005 10:37, Blue Swirl wrote:
> Hi,
>
> The architecture used in sparc target (sun4m) supports SMP up to a maximum
> of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*), it would be
> easy to add the missing interprocessor interrupts, per-CPU counters and
> atomic inst
> In addition to this patch I also needed the attached patch to get MinGW
> GCC 3.4.1 builds working...
>
>...
> - if (strstart(sym_name, "__op_label", &p)) {
> + if (strstart(sym_name, "__op_label", &p) ||
> +strstart(sym_name, "_op_label", &p)) {
Hi,
The architecture used in sparc target (sun4m) supports SMP up to a maximum
of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*), it would be
easy to add the missing interprocessor interrupts, per-CPU counters and
atomic instructions. It would also be simple to add the prom function
On 5/13/05, Ronald <[EMAIL PROTECTED]> wrote:
> > I'm already using the latest FreeOSZoo windows build.
>
> This doesn't mean that it perform like Christian's or Kazu's one, you can
> get a try.
>
Actually I performed some comparisons yesterday using nbench on
a qemu linux guest on winxp host,
Paul Brook wrote:
On Wednesday 11 May 2005 22:04, Paul Brook wrote:
The attached patch adds support for gcc4 x86 and x86_64 hosts.
This time with the correct patch attached.
Paul
In addition to this patch I also needed the attached patch to get MinGW
GCC 3.4.1 builds working...
- Filip
16 matches
Mail list logo
