On Sat, Jun 14, 2025 at 6:23 PM Jerome Kieffer
wrote:
> Hi Ralph,
>
> There is no problem here except "any hardware more than 10yo* is
> deprecated and we can discontinue its support" which is something Intel
> would love but not me (nor anybody who realized we are living in a
> finite world).
>
Hi Ralph,
There is no problem here except "any hardware more than 10yo* is
deprecated and we can discontinue its support" which is something Intel
would love but not me (nor anybody who realized we are living in a
finite world).
Cheers,
Jerome
PS: since 2003, the frequency of processors has rea
On Fri, Jun 13, 2025 at 11:07 AM Jerome Kieffer
wrote:
> Hi Matti,
>
> Sorry for the delay ...
>
> In one of my project I am working on, we use based Avoton server
> (Intel C2350) for CI/CD which can be rented today (2025) for less than
> 5€/month
> at online.net (a french provider). Switching to
Hi Matti,
Sorry for the delay ...
In one of my project I am working on, we use based Avoton server
(Intel C2350) for CI/CD which can be rented today (2025) for less than 5€/month
at online.net (a french provider). Switching to more recent generation
of processor (E3 1245v5) would imply at least 3
On Sun, May 18, 2025 at 9:40 AM Jerome Kieffer
wrote:
> Hi,
>
> First I would like to highlight that "X86_V2" is very specific to the
> implementation in numpy, basically this implies the support of all 128
> bits SIMD extensions, i.e. SSE1,2,3&4, but does apparenty not requires
> any 256bit SIMD
On Sun, May 18, 2025 at 10:39 AM Jerome Kieffer
wrote:
>
> Hi,
>
> First I would like to highlight that "X86_V2" is very specific to the
> implementation in numpy, basically this implies the support of all 128
> bits SIMD extensions, i.e. SSE1,2,3&4, but does apparenty not requires
> any 256bit SI
Hi Jerome,
`X86_V2` includes also `POPCNT CX16 LAHF` along with SSE4.2.
All CPUs that support `SSE4.2` also include these instructions.
I think Ralf is right to exclude servers in the case of using X86_V2 as a
baseline.
Basically, older servers that run architectures like Penryn (17 years ago)
or
Hi,
First I would like to highlight that "X86_V2" is very specific to the
implementation in numpy, basically this implies the support of all 128
bits SIMD extensions, i.e. SSE1,2,3&4, but does apparenty not requires
any 256bit SIMD (AVX).
Ralph, the stats you are using are made on end-user hardwa
On Sat, May 17, 2025 at 3:00 PM wrote:
> Hi Sayed,
>
> I'm a bit confused: does your suggested change mean that prre-2009
> processors won't work at all, or that no use will be made of the (little)
> acceleration that they provided? The latter seems fine, but not working at
> all seems rather ba
Hi Marten,
By default, they won't work at all - Python runtime error will be raised or
segfault/illegal instruction error may occur. However, if Linux distros or
downstream packagers want to change this default setting, they can do it
through the build options, but without manual SIMD support for
Hi Sayed,
I'm a bit confused: does your suggested change mean that prre-2009 processors
won't work at all, or that no use will be made of the (little) acceleration
that they provided? The latter seems fine, but not working at all seems rather
bad. Though I'd think that for any old processors o
On Fri, May 16, 2025 at 4:23 AM Sayed Adel wrote:
> Hi All,
>
> I wanted to bring your attention to an important change to NumPy that will
> affect CPU compatibility requirements on x86.
>
> PR #28896 (https://github.com/numpy/numpy/pull/28896) is reorganizing how
> NumPy handles x86 CPU features
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