On Thu, Oct 18, 2018 at 04:49:26PM +, Claudiu Manoil wrote:
>
> I can only advise you to check whether the MACCFG2 register settings are
> consistent
> at this point, when ping fails. You should check the I/F Mode bits (22-23)
> and the
> Full Duplex bit (31), in big-endian format. If the
On Thu, Oct 18, 2018 at 04:49:26PM +, Claudiu Manoil wrote:
> I can only advise you to check whether the MACCFG2 register settings are
> consistent
> at this point, when ping fails. You should check the I/F Mode bits (22-23)
> and the
> Full Duplex bit (31), in big-endian format. If these
>-Original Message-
>From: Daniel Walker
>Sent: Thursday, October 18, 2018 5:05 PM
>To: Claudiu Manoil
>Cc: Hemant Ramdasi ; netdev@vger.kernel.org
>Subject: Re: [danie...@cisco.com: Re: gianfar: Implement MAC reset and
>reconfig procedure]
>
[...]
>
>He
On Thu, Oct 18, 2018 at 12:16:06PM +, Claudiu Manoil wrote:
> Hi,
>
> Sorry but I never heard about the phy you're quoting, this m88e1101, what is
> it?
> Link mode? (SGMII, RGMII, ?)
> Our boards (the ones I know) have Vitesse or Atheros phys.
> If the maccfg2 setting you're mentioning reall
On Thu, Oct 18, 2018 at 12:16:06PM +, Claudiu Manoil wrote:
> Hi,
>
> Sorry but I never heard about the phy you're quoting, this m88e1101, what is
> it?
> Link mode? (SGMII, RGMII, ?)
> Our boards (the ones I know) have Vitesse or Atheros phys.
> If the maccfg2 setting you're mentioning reall
On Tue, Oct 16, 2018 at 03:03:07PM -0700, Florian Fainelli wrote:
> On 10/16/2018 02:36 PM, Daniel Walker wrote:
> > Hi,
> >
> > I would like to report an issue in the gianfar driver. The issue is as
> > follows.
> >
> > We have a P2020 board that uses the gianfar driver, and we have a m88e1101
On 10/16/2018 02:36 PM, Daniel Walker wrote:
> Hi,
>
> I would like to report an issue in the gianfar driver. The issue is as
> follows.
>
> We have a P2020 board that uses the gianfar driver, and we have a m88e1101
> PHY connect. When the interface is initially brought up traffic flows as
> no
Hi,
I would like to report an issue in the gianfar driver. The issue is as follows.
We have a P2020 board that uses the gianfar driver, and we have a m88e1101
PHY connect. When the interface is initially brought up traffic flows as
normal. If you take the interface down then bring it back up tra
