On Mon, Sep 11, 2017 at 10:19:20PM +0200, Andrew Lunn wrote:
> > Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout.
> > So no the CLK/RST are really for the PHY.
>
> Thanks for trying that.
>
> You said it was probably during scanning of the bus it times out. What
> address is ca
> Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout.
> So no the CLK/RST are really for the PHY.
Thanks for trying that.
You said it was probably during scanning of the bus it times out. What
address is causing the timeout? 0 or 1? If the internal bus can only
have one PHY on it,
On Mon, Sep 11, 2017 at 06:11:24PM +0200, Andrew Lunn wrote:
> On Fri, Sep 08, 2017 at 04:28:25PM +0200, Corentin Labbe wrote:
> > On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote:
> > > > > Do you know why the reset times out/fails?
> > > > >
> > > >
> > > > Because there are nothing
On Fri, Sep 08, 2017 at 04:28:25PM +0200, Corentin Labbe wrote:
> On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote:
> > > > Do you know why the reset times out/fails?
> > > >
> > >
> > > Because there are nothing connected to it.
> >
> > That should not be an issue. A read should just
On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote:
> > > Do you know why the reset times out/fails?
> > >
> >
> > Because there are nothing connected to it.
>
> That should not be an issue. A read should just return 0x. And it
> should return 0x fast. The timing of the MDIO pr
> > Do you know why the reset times out/fails?
> >
>
> Because there are nothing connected to it.
That should not be an issue. A read should just return 0x. And it
should return 0x fast. The timing of the MDIO protocol is fixed. A
read or a write takes a fixed number of cycles, independ
On Fri, Sep 08, 2017 at 04:00:20PM +0200, Andrew Lunn wrote:
> > > > +static int mdio_mux_syscon_switch_fn(int current_child, int
> > > > desired_child,
> > > > +void *data)
> > > > +{
> > > > + struct stmmac_priv *priv = data;
> > > > + struct sunxi
> > > +static int mdio_mux_syscon_switch_fn(int current_child, int
> > > desired_child,
> > > + void *data)
> > > +{
> > > + struct stmmac_priv *priv = data;
> > > + struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
> > > + u32 reg, val;
> > > + int ret = 0;
> > > +
On Fri, Sep 08, 2017 at 03:05:20PM +0200, Andrew Lunn wrote:
> > +#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID 0
> > +#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID 1
> >
> > /* H3/A64 specific bits */
> > #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides
> > EPIT) */
> > @@ -6
> +#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID 0
> +#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID 1
>
> /* H3/A64 specific bits */
> #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides
> EPIT) */
> @@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv
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