On Sun, Jan 10, 2021 at 07:11:53PM +, Stefan Chulski wrote:
> >
> > On Sun, Jan 10, 2021 at 06:55:11PM +, Stefan Chulski wrote:
> > > > > not connected to the GOP flow control generation mechanism.
> > > > > To solve this issue Armada has firmware running on CM3 CPU
> > > > > dedectated fo
>
> On Sun, Jan 10, 2021 at 06:55:11PM +, Stefan Chulski wrote:
> > > > not connected to the GOP flow control generation mechanism.
> > > > To solve this issue Armada has firmware running on CM3 CPU
> > > > dedectated for Flow Control support. Firmware monitors Packet
> > > > Processor resourc
On Sun, Jan 10, 2021 at 06:55:11PM +, Stefan Chulski wrote:
> > > not connected to the GOP flow control generation mechanism.
> > > To solve this issue Armada has firmware running on CM3 CPU dedectated
> > > for Flow Control support. Firmware monitors Packet Processor resources
> > > and assert
On Sun, Jan 10, 2021 at 06:55:11PM +, Stefan Chulski wrote:
> > > not connected to the GOP flow control generation mechanism.
> > > To solve this issue Armada has firmware running on CM3 CPU dedectated
> > > for Flow Control support. Firmware monitors Packet Processor resources
> > > and assert
> > not connected to the GOP flow control generation mechanism.
> > To solve this issue Armada has firmware running on CM3 CPU dedectated
> > for Flow Control support. Firmware monitors Packet Processor resources
> > and asserts XON/XOFF by writing to Ports Control 0 Register.
>
> What is the mini
Hi,
On Sun, Jan 10, 2021 at 05:30:04PM +0200, stef...@marvell.com wrote:
> Armada hardware has a pause generation mechanism in GOP (MAC).
> GOP has to generate flow control frames based on an indication
> programmed in Ports Control 0 Register. There is a bit per port.
> However assertion of the P
