On 2/2/2018 1:08 PM, Tantilov, Emil S wrote:
Just FYI - we looked at the reads and confirmed that there is no functional
bug in the code because as it happens the CX1/SR bits is the only bits that
are read and set and as such we don't lose any data. This of course means
that the read is not neede
ired-...@lists.osuosl.org
>>Subject: Re: [Intel-wired-lan] Possible read-modify-write bug in ixgbe
>>x550 phy setup
>>
>>On 2/1/2018 4:34 PM, Tantilov, Emil S wrote:
>>>> -Original Message-
>>>> From: Intel-wired-lan [mailto:intel-wired-lan-bo
t;> To: Tantilov, Emil S
>>> Cc: netdev@vger.kernel.org; intel-wired-...@lists.osuosl.org
>>> Subject: [Intel-wired-lan] Possible read-modify-write bug in ixgbe
>x550
>>> phy setup
>>>
>>> Hi Emil,
>>>
>>> I was looking through
Subject: [Intel-wired-lan] Possible read-modify-write bug in ixgbe x550
phy setup
Hi Emil,
I was looking through a set of ixgbe patches and came across this commit
commit 410a494902777c11f95031d9ed757d7f8f09c5c6
ixgbe: add write flush when configuring CS4223/7
and am wondering about the
ed-lan] Possible read-modify-write bug in ixgbe x550
>phy setup
>
>Hi Emil,
>
>I was looking through a set of ixgbe patches and came across this commit
>
> commit 410a494902777c11f95031d9ed757d7f8f09c5c6
> ixgbe: add write flush when configuring CS4223/7
>
>and a
Hi Emil,
I was looking through a set of ixgbe patches and came across this commit
commit 410a494902777c11f95031d9ed757d7f8f09c5c6
ixgbe: add write flush when configuring CS4223/7
and am wondering about the setting of reg_phy_ext in the middle of
ixgbe_setup_mac_link_sfp_x550a(). It lo
