Re: Align DMA buffers to a cacheline

2005-11-08 Thread David S. Miller
From: Anton Blanchard <[EMAIL PROTECTED]> Date: Wed, 9 Nov 2005 03:12:20 +1100 > Do you mean we expect exactly 16 bytes, or at least 16 bytes. Im happy > to ammend it so we always require the minimum 16 bytes, and can expand > it on architectures where it makes sense. I meant "at least 16 bytes".

Re: Align DMA buffers to a cacheline

2005-11-08 Thread Anton Blanchard
Hi, > There is still a lot of code that depends upon there being > a scratch of ~15 bytes there at the beginning of the SKB data > area. > > This kind of change, at best, would require a thorough audit > of every single piece of the networking, particularly things > that tunnel other protocols

Re: Align DMA buffers to a cacheline

2005-11-08 Thread John W. Linville
On Tue, Nov 08, 2005 at 08:57:14AM -0800, David S. Miller wrote: > From: Anton Blanchard <[EMAIL PROTECTED]> > Date: Tue, 8 Nov 2005 17:56:47 +1100 > > > Any thoughts on this? The other option was to override dev_alloc_skb, > > but I would prefer not to if possible. > > There is still a lot of c

Re: Align DMA buffers to a cacheline

2005-11-08 Thread David S. Miller
From: Anton Blanchard <[EMAIL PROTECTED]> Date: Tue, 8 Nov 2005 17:56:47 +1100 > Any thoughts on this? The other option was to override dev_alloc_skb, > but I would prefer not to if possible. There is still a lot of code that depends upon there being a scratch of ~15 bytes there at the beginning

Align DMA buffers to a cacheline

2005-11-08 Thread Anton Blanchard
Hi, On ppc64 we want DMA writes (ie receive packets) to be aligned, hopefully on a cacheline boundary. The NET_IP_ALIGN patch got us part of the way, so that DMAs were 16 byte aligned. The following patch addresses the other source of misalignment. Every skb has 16 bytes of headroom reserved for