From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Sat, 30 Dec 2006 08:36:07 +1100
> Heh, it's very possible it's a regression I added indeed. I'll try to
> have a look next week. Do you know of anybody who can verify on non-mii
> hardware or is pause irrelevant there ?
For PCS based PHY's mo
On Thu, 2006-12-28 at 21:05 -0800, David Miller wrote:
> From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
> Date: Wed, 13 Dec 2006 15:07:24 +1100
>
> > tg3 says
> >
> > tg3: eth0: Link is up at 1000 Mbps, full duplex.
> > tg3: eth0: Flow control is on for TX and on for RX.
> >
> > but sungem say
From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Wed, 13 Dec 2006 15:07:24 +1100
> tg3 says
>
> tg3: eth0: Link is up at 1000 Mbps, full duplex.
> tg3: eth0: Flow control is on for TX and on for RX.
>
> but sungem says
>
> eth0: Link is up at 1000 Mbps, full-duplex.
> eth0: Pause is disab
> Thanks for testing this stuff.
>
> I'll take a look at the pause-enabling issue in the sungem
> drive then work on integrating Eric's patch.
Ok, thanks.
> Probably we'll need to put this in post-2.6.20 as the merge
> window is closed.
Yup, no hurry there.
Ben.
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From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Fri, 15 Dec 2006 11:59:06 +1100
> Patched driver's been running fine for a couple of days & nights with
> constant beating... just those RX MAC fifo overflows every now and then
> (though they cause no data corruption and no big hit on the dri
On Tue, 2006-12-12 at 06:49 +0100, Eric Lemoine wrote:
> On 12/12/06, Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:
> > On Tue, 2006-12-12 at 06:33 +0100, Eric Lemoine wrote:
> > > On 12/12/06, David Miller <[EMAIL PROTECTED]> wrote:
> > > > [...]
> > > > Anyways, Eric your changes look fine as
On Tue, 2006-12-12 at 20:03 -0800, David Miller wrote:
> From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
> Date: Wed, 13 Dec 2006 14:12:13 +1100
>
> > David, could that be the pause stuff not working properly ?
>
> It could be, but if the tg3 says flow control is up in the kernel logs
> things o
Been hitting a raw throughput in both directions plus a few other things
on a dual G5 and the driver didn't crash :-)
I'm seeing a problem though but I'm not sure it's related to your patch,
I'll have to test without it.
Basically, if I use a slightly modified versio of tridge's socklib (raw
xput
From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Wed, 13 Dec 2006 14:12:13 +1100
> David, could that be the pause stuff not working properly ?
It could be, but if the tg3 says flow control is up in the kernel logs
things ought to be OK.
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On Wed, 2006-12-13 at 14:12 +1100, Benjamin Herrenschmidt wrote:
> Been hitting a raw throughput in both directions plus a few other things
> on a dual G5 and the driver didn't crash :-)
>
> I'm seeing a problem though but I'm not sure it's related to your patch,
> I'll have to test without it.
>
On 12/12/06, Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:
On Tue, 2006-12-12 at 06:33 +0100, Eric Lemoine wrote:
> On 12/12/06, David Miller <[EMAIL PROTECTED]> wrote:
> > [...]
> > Anyways, Eric your changes look fine as far as I can tell, can you
> > give them a really good testing on some
On Tue, 2006-12-12 at 06:33 +0100, Eric Lemoine wrote:
> On 12/12/06, David Miller <[EMAIL PROTECTED]> wrote:
> > [...]
> > Anyways, Eric your changes look fine as far as I can tell, can you
> > give them a really good testing on some SMP boxes?
>
> Unfortunately I can't, I don't have the hardware
On 12/12/06, David Miller <[EMAIL PROTECTED]> wrote:
[...]
Anyways, Eric your changes look fine as far as I can tell, can you
give them a really good testing on some SMP boxes?
Unfortunately I can't, I don't have the hardware (only an old ibook here).
--
Eric
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From: "Eric Lemoine" <[EMAIL PROTECTED]>
Date: Wed, 29 Nov 2006 11:56:30 +0100
> I don't understand why we'd need all this.
>
> I think the following code for gem_interrupt should do the trick:
...
> The important thing is: we __netif_rx_schedule even if gem_status is 0
> (shared irq case) becaus
On 11/28/06, David Miller <[EMAIL PROTECTED]> wrote:
From: "Eric Lemoine" <[EMAIL PROTECTED]>
Date: Tue, 14 Nov 2006 22:54:40 +0100
> On 11/14/06, David Miller <[EMAIL PROTECTED]> wrote:
> > From: "Eric Lemoine" <[EMAIL PROTECTED]>
> > Date: Tue, 14 Nov 2006 08:28:42 +0100
> >
> > > because it m
On 11/29/06, David Miller <[EMAIL PROTECTED]> wrote:
From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Wed, 29 Nov 2006 09:57:24 +1100
>
> > This looks mostly fine.
> >
> > I was thinking about the lockless stuff, and I wonder if there
> > is a clever way you can get it back down to one PIO
On Tue, 2006-11-28 at 15:43 -0800, David Miller wrote:
> At least in theory the atomic + any necessary memory barriers
> would be cheaper than the extra PIO read we need otherwise.
Yes, IO reads are generally the worst case scenarios even on machines
with fairly slow locks.
Ben.
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From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Wed, 29 Nov 2006 09:57:24 +1100
>
> > This looks mostly fine.
> >
> > I was thinking about the lockless stuff, and I wonder if there
> > is a clever way you can get it back down to one PIO on the
> > GREG_STAT register.
> >
> > I think you'
> This looks mostly fine.
>
> I was thinking about the lockless stuff, and I wonder if there
> is a clever way you can get it back down to one PIO on the
> GREG_STAT register.
>
> I think you'd need to have the ->poll() clear gp->status, then
> do a smp_wb(), right before it re-enables interrupt
From: "Eric Lemoine" <[EMAIL PROTECTED]>
Date: Tue, 14 Nov 2006 22:54:40 +0100
> On 11/14/06, David Miller <[EMAIL PROTECTED]> wrote:
> > From: "Eric Lemoine" <[EMAIL PROTECTED]>
> > Date: Tue, 14 Nov 2006 08:28:42 +0100
> >
> > > because it makes it explicit that only bits 0 through 6 are taken i
From: "Eric Lemoine" <[EMAIL PROTECTED]>
Date: Tue, 14 Nov 2006 08:28:42 +0100
> because it makes it explicit that only bits 0 through 6 are taken into
> account when writing the IACK register.
The phrase "bits 0 through 6" doesn't make any sense when bit 3 DOES
NOT EXIST in the hardware, it's re
On 11/14/06, David Miller <[EMAIL PROTECTED]> wrote:
From: "Eric Lemoine" <[EMAIL PROTECTED]>
Date: Mon, 13 Nov 2006 00:11:49 +0100
> +#if GEM_INTERRUPT_LOCKLESS
> +
> +/* Bitmask representing the interrupt conditions that we clear using
GREG_IACK.
> + * We clear all the top-level interrupt con
From: "Eric Lemoine" <[EMAIL PROTECTED]>
Date: Mon, 13 Nov 2006 00:11:49 +0100
> +#if GEM_INTERRUPT_LOCKLESS
> +
> +/* Bitmask representing the interrupt conditions that we clear using
> GREG_IACK.
> + * We clear all the top-level interrupt conditions (bits 0 through 6) that we
> + * handle.
> +
From: "Eric Lemoine" <[EMAIL PROTECTED]>
Date: Fri, 10 Nov 2006 14:28:41 +0100
> On 11/10/06, David Miller <[EMAIL PROTECTED]> wrote:
> >
> > Please use GREG_STAT_* instead of magic constants for the
> > interrupt mask and ACK register writes. In fact, there are
> > some questionable values you u
> Yes, the bit 4 isn't used, but I assumed clearing it shouldn't be prolem.
Always leave reserved bits alone ... I agree it's very unlikely in this
case that it could cause a problem but I've seen stranger things
Ben.
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On 11/10/06, David Miller <[EMAIL PROTECTED]> wrote:
Please use GREG_STAT_* instead of magic constants for the
interrupt mask and ACK register writes. In fact, there are
some questionable values you use, in particular this one:
+static inline void gem_ack_int(struct gem *gp)
+{
+ writel(
Please use GREG_STAT_* instead of magic constants for the
interrupt mask and ACK register writes. In fact, there are
some questionable values you use, in particular this one:
+static inline void gem_ack_int(struct gem *gp)
+{
+ writel(0x3f, gp->regs + GREG_IACK);
+}
There is no bit define
The attached patch improves locking in the sungem driver:
- a single lock is used in the driver
- gem_start_xmit, gem_poll, and gem_interrupt are lockless
The new locking design is based on what's in tg3.c.
The patch runs smoothly on my ibook (with CONFIG_SMP set), but it will
need extensive te
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