On Fri, 25 Jan 2019 17:33:50 PST (-0800), Jim Wilson wrote:
On Fri, Jan 25, 2019 at 12:21 PM Palmer Dabbelt wrote:
Jim, would you be opposed to something like this?
This looks OK to me.
OK, thanks. I'll send some patches around :)
+builtin_define_with_int_value ("__riscv_tune_m
On Fri, Jan 25, 2019 at 12:21 PM Palmer Dabbelt wrote:
> Jim, would you be opposed to something like this?
This looks OK to me.
> +builtin_define_with_int_value ("__riscv_tune_misaligned_load_cost",
> +
> riscv_tune_info->slow_unaligned_access ? 102
On Tue, 15 Jan 2019 08:06:47 PST (-0800), bjorn.to...@gmail.com wrote:
Den tis 15 jan. 2019 kl 16:39 skrev Christoph Hellwig :
Hmm, while the RISC-V spec requires misaligned load/store support,
who says they are efficient? Maybe add a little comment that says
on which cpus they are efficient.
Den tis 15 jan. 2019 kl 16:39 skrev Christoph Hellwig :
>
> Hmm, while the RISC-V spec requires misaligned load/store support,
> who says they are efficient? Maybe add a little comment that says
> on which cpus they are efficient.
Good point! :-) I need to check how other architectures does this.
Hmm, while the RISC-V spec requires misaligned load/store support,
who says they are efficient? Maybe add a little comment that says
on which cpus they are efficient.
Signed-off-by: Björn Töpel
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index feeeaa60697c..f13220904d7c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -49,6 +49,7 @@ config RISCV
select RISCV_TIMER
