On Tue, 16 Feb 2021 13:12:29 -0500 Vincent Cheng wrote:
> >> +}
> >> +
> >> +static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
> >> +{
> >> + const char *fmt = "%d ms SYS lock timeout: APLL Loss Lock %d DPLL
> >> state %d";
> >> + u8 i = LOCK_TIMEOUT_MS / LOCK_POLL_INTERVAL_MS;
> >
On Mon, Feb 15, 2021 at 02:48:22PM EST, Jakub Kicinski wrote:
>On Sat, 13 Feb 2021 00:06:04 -0500 vincent.cheng...@renesas.com wrote:
>> +static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
>> +{
>> +int err;
>> +
>> +err = idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, statu
On Sat, 13 Feb 2021 00:06:04 -0500 vincent.cheng...@renesas.com wrote:
> From: Vincent Cheng
>
> Part of the device initialization aligns the rising edge of the output
> clock to the internal 1 PPS clock. If the system APLL and DPLL is not
> locked, then the alignment will fail and there will be
From: Vincent Cheng
Part of the device initialization aligns the rising edge of the output
clock to the internal 1 PPS clock. If the system APLL and DPLL is not
locked, then the alignment will fail and there will be a fixed offset
between the internal 1 PPS clock and the output clock.
After load
