On Mon, 13 Jul 2020 21:50:25 +0100 Matthew Hagan wrote:
> + u32 val = qca8k_read(priv, QCA8K_REG_PORT0_PAD_CTRL);
> + val |= QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG;
> + val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
> + val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLI
A number of devices require additional PORT0_PAD configuration that cannot
otherwise be inferred. This patch is based on John Crispin's "net: dsa:
qca8k: allow swapping of mac0 and mac6", adding the ability to swap mac0
and mac6, as well as to set the transmit and receive clock phase to falling
edg
