On 09/10/17 14:00, Florian Fainelli wrote:
> Le 10/08/17 à 20:23, Greg Ungerer a écrit :
>> On 07/10/17 13:04, Florian Fainelli wrote:
>>> Le 10/03/17 à 23:20, Greg Ungerer a écrit :
On Wed, Mar 29, 2017 at 04:30:16PM -0400, Vivien Didelot wrote:
> All ports -- internal and external, for c
Le 10/08/17 à 20:23, Greg Ungerer a écrit :
> Hi Florian,
>
> On 07/10/17 13:04, Florian Fainelli wrote:
>> Le 10/03/17 à 23:20, Greg Ungerer a écrit :
>>> On Wed, Mar 29, 2017 at 04:30:16PM -0400, Vivien Didelot wrote:
All ports -- internal and external, for chips featuring a PVT -- have a
>
Hi Florian,
On 07/10/17 13:04, Florian Fainelli wrote:
> Le 10/03/17 à 23:20, Greg Ungerer a écrit :
>> On Wed, Mar 29, 2017 at 04:30:16PM -0400, Vivien Didelot wrote:
>>> All ports -- internal and external, for chips featuring a PVT -- have a
>>> mask restricting to which internal ports a frame i
Le 10/03/17 à 23:20, Greg Ungerer a écrit :
> Hi Vivien,
>
> On Wed, Mar 29, 2017 at 04:30:16PM -0400, Vivien Didelot wrote:
>> All ports -- internal and external, for chips featuring a PVT -- have a
>> mask restricting to which internal ports a frame is allowed to egress.
>>
>> Now that DSA expos
Hi Vivien,
On Wed, Mar 29, 2017 at 04:30:16PM -0400, Vivien Didelot wrote:
> All ports -- internal and external, for chips featuring a PVT -- have a
> mask restricting to which internal ports a frame is allowed to egress.
>
> Now that DSA exposes the number of ports and their bridge devices, it i
