Andrew
On 8/26/20 7:58 AM, Andrew Lunn wrote:
On Tue, Aug 25, 2020 at 02:57:35PM -0500, Dan Murphy wrote:
Andrew
On 8/25/20 8:37 AM, Andrew Lunn wrote:
On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote:
The RGMII control register at 0x32 indicates the states for the bits
RGM
On Tue, Aug 25, 2020 at 02:57:35PM -0500, Dan Murphy wrote:
> Andrew
>
> On 8/25/20 8:37 AM, Andrew Lunn wrote:
> > On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote:
> > > The RGMII control register at 0x32 indicates the states for the bits
> > > RGMII_TX_CLK_DELAY and RGMII_RX_C
Andrew
On 8/25/20 8:37 AM, Andrew Lunn wrote:
On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote:
The RGMII control register at 0x32 indicates the states for the bits
RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:
RGMII Transmit/Receive Clock Delay
0x0 = RGMII tr
On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote:
> The RGMII control register at 0x32 indicates the states for the bits
> RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:
>
> RGMII Transmit/Receive Clock Delay
> 0x0 = RGMII transmit clock is shifted with respect to tr
From: Daniel Gorsulowski
Date: Tue, 25 Aug 2020 14:07:21 +0200
> The RGMII control register at 0x32 indicates the states for the bits
> RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:
>
> RGMII Transmit/Receive Clock Delay
> 0x0 = RGMII transmit clock is shifted with respect to trans
The RGMII control register at 0x32 indicates the states for the bits
RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:
RGMII Transmit/Receive Clock Delay
0x0 = RGMII transmit clock is shifted with respect to transmit/receive data.
0x1 = RGMII transmit clock is aligned with respect to
