From: Subbaraya Sundeep
Support SPI and sequence number fields of
ESP/AH header to be hashed for RSS. By default
ESP/AH fields are not considered for RSS and
needs to be set explicitly as below:
ethtool -U eth0 rx-flow-hash esp4 sdfn
or
ethtool -U eth0 rx-flow-hash ah4 sdfn
or
ethtool -U eth0 rx-
From: Subbaraya Sundeep
Octeontx2 hardware needs buffer pointers which are 128 byte
aligned. napi_alloc_frag() returns buffer pointers which are
not 128 byte aligned sometimes because if napi_alloc_skb() is
called when a packet is received then subsequent napi_alloc_frag()
returns buffer which is
From: Subbaraya Sundeep
On 98xx silicon, NPC block has additional
mcam entries, counters and NIX1 interfaces.
Extended set of registers are present for the
new mcam entries and counters.
This patch does the following:
- updates the register accessing macros
to use extended set if present.
- con
From: Rakesh Babu
This patch modifies NIX functions to operate
with nix_hw context so that existing functions
can be used for both NIX0 and NIX1 blocks. And
the NIX blocks present in the system are initialized
during driver init and freed during exit.
Signed-off-by: Rakesh Babu
Signed-off-by: S
From: Subbaraya Sundeep
OcteonTx2 series of silicons have multiple variants, the
98xx variant has two network interface controllers (NIX blocks)
each of which supports upto 100Gbps. Similarly 98xx supports
two crypto blocks (CPT) to double the crypto performance.
The current RVU drivers support a
From: Rakesh Babu
If NIX1 block is also implemented then add a new
directory for NIX1 in debugfs root. Stats of
NIX1 block can be read/writen from/to the files
in directory "/sys/kernel/debug/octeontx2/nix1/".
Signed-off-by: Rakesh Babu
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Gou
From: Subbaraya Sundeep
Firmware configures NIX block mapping for all CGXs
to achieve maximum throughput. This patch reads
the configuration and create mapping between RVU
PF and NIX blocks. And for LBK VFs assign NIX0 for
even numbered VFs and NIX1 for odd numbered VFs.
Signed-off-by: Subbaraya
From: Subbaraya Sundeep
CGX links are followed by LBK links but number of
CGX and LBK links varies between platforms. Hence
get the number of links present in hardware from
AF and use it to calculate LBK link number.
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
Signed-off-by:
From: Subbaraya Sundeep
This patch puts together all mailbox changes
for 98xx silicon:
Attach ->
Modify resource attach mailbox handler to
request LFs from a block address out of multiple
blocks of same type. If a PF/VF need LFs from two
blocks of same type then attach mbox should be
called twic
From: Rakesh Babu
Unlike earlier silicon variants, OcteonTx2 98xx
silicon has 2 NIX blocks and each of the CGX is
mapped to either of the NIX blocks. Each NIX
block supports 100G. Mapping btw NIX blocks and
CGX is done by firmware based on CGX speed config
to have a maximum possible network bandw
From: Rakesh Babu
AF manages the tasks of allocating, freeing
LFs from RVU blocks to PF and VFs. With new
NIX1 and CPT1 blocks in 98xx, this patch
adds support for handling new blocks too.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Rakesh Babu
Signed-of
From: Subbaraya Sundeep
Initialize MCE context for the assigned NIX0/1
block for a CGX mapped PF. Modified rvu_nix_aq_enq_inst
function to work with nix_hw so that MCE contexts
for both NIX blocks can be inited.
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
Signed-off-by: Rakes
From: Subbaraya Sundeep
Since multiple blocks of same type are present in
98xx, modify functions which get resource count and
which update resource count to work with individual
block address instead of block type.
Reviewed-by: Jesse Brandeburg
Signed-off-by: Subbaraya Sundeep
Signed-off-by: S
From: Rakesh Babu
Unlike earlier silicon variants, OcteonTx2 98xx
silicon has 2 NIX blocks and each of the CGX is
mapped to either of the NIX blocks. Each NIX
block supports 100G. Mapping btw NIX blocks and
CGX is done by firmware based on CGX speed config
to have a maximum possible network bandw
From: Rakesh Babu
If NIX1 block is also implemented then add a new
directory for NIX1 in debugfs root. Stats of
NIX1 block can be read/writen from/to the files
in directory "/sys/kernel/debug/octeontx2/nix1/".
Signed-off-by: Rakesh Babu
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Gou
From: Subbaraya Sundeep
Since multiple blocks of same type are present in
98xx, modify functions which get resource count and
which update resource count to work with individual
block address instead of block type.
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
Signed-off-by: Ra
From: Subbaraya Sundeep
On 98xx silicon, NPC block has additional
mcam entries, counters and NIX1 interfaces.
Extended set of registers are present for the
new mcam entries and counters.
This patch does the following:
- updates the register accessing macros
to use extended set if present.
- con
From: Subbaraya Sundeep
OcteonTx2 series of silicons have multiple variants, the
98xx variant has two network interface controllers (NIX blocks)
each of which supports upto 100Gbps. Similarly 98xx supports
two crypto blocks (CPT) to double the crypto performance.
The current RVU drivers support a
From: Subbaraya Sundeep
This patch puts together all mailbox changes
for 98xx silicon:
Attach ->
Modify resource attach mailbox handler to
request LFs from a block address out of multiple
blocks of same type. If a PF/VF need LFs from two
blocks of same type then attach mbox should be
called twic
From: Subbaraya Sundeep
CGX links are followed by LBK links but number of
CGX and LBK links varies between platforms. Hence
get the number of links present in hardware from
AF and use it to calculate LBK link number.
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
Signed-off-by:
From: Rakesh Babu
AF manages the tasks of allocating, freeing
LFs from RVU blocks to PF and VFs. With new
NIX1 and CPT1 blocks in 98xx, this patch
adds support for handling new blocks too.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Rakesh Babu
Signed-of
From: Rakesh Babu
This patch modifies NIX functions to operate
with nix_hw context so that existing functions
can be used for both NIX0 and NIX1 blocks. And
the NIX blocks present in the system are initialized
during driver init and freed during exit.
Signed-off-by: Rakesh Babu
Signed-off-by: S
From: Subbaraya Sundeep
Initialize MCE context for the assigned NIX0/1
block for a CGX mapped PF. Modified rvu_nix_aq_enq_inst
function to work with nix_hw so that MCE contexts
for both NIX blocks can be inited.
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
Signed-off-by: Rakes
From: Subbaraya Sundeep
Firmware configures NIX block mapping for all CGXs
to achieve maximum throughput. This patch reads
the configuration and create mapping between RVU
PF and NIX blocks. And for LBK VFs assign NIX0 for
even numbered VFs and NIX1 for odd numbered VFs.
Signed-off-by: Subbaraya
From: Subbaraya Sundeep
This patchset adds tracepoints support for mailbox.
In Octeontx2, PFs and VFs need to communicate with AF
for allocating and freeing resources. Once all the
configuration is done by AF for a PF/VF then packet I/O
can happen on PF/VF queues. When an interface
is brought up
From: Subbaraya Sundeep
Added tracepoints in mailbox code so that
the mailbox operations like message allocation,
sending message and message interrupts are traced.
Also the mailbox errors occurred like timeout
or wrong responses are traced.
These will help in debugging mailbox issues.
Here's an
From: Subbaraya Sundeep
With tracepoints support present in the mailbox
code this patch adds tracepoints in PF and VF drivers
at places where mailbox messages are allocated,
sent and at message interrupts.
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/
From: Subbaraya Sundeep
This patchset adds tracepoints support for mailbox.
In Octeontx2, PFs and VFs need to communicate with AF
for allocating and freeing resources. Once all the
configuration is done by AF for a PF/VF then packet I/O
can happen on PF/VF queues. When an interface
is brought up
From: Subbaraya Sundeep
With tracepoints support present in the mailbox
code this patch adds tracepoints in PF and VF drivers
at places where mailbox messages are allocated,
sent and at message interrupts.
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/
From: Subbaraya Sundeep
Added tracepoints in mailbox code so that
the mailbox operations like message allocation,
sending message and message interrupts are traced.
Also the mailbox errors occurred like timeout
or wrong responses are traced.
These will help in debugging mailbox issues.
Here's an
From: Subbaraya Sundeep
Added tracepoints in mailbox code so that
the mailbox operations like message allocation,
sending message and message interrupts are traced.
Also the mailbox errors occurred like timeout
or wrong responses are traced.
These will help in debugging mailbox issues.
Here's an
From: Subbaraya Sundeep
With tracepoints support present in the mailbox
code this patch adds tracepoints in PF and VF drivers
at places where mailbox messages are allocated,
sent and at message interrupts.
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/
From: Subbaraya Sundeep
This patchset adds tracepoints support for mailbox.
In Octeontx2, PFs and VFs need to communicate with AF
for allocating and freeing resources. Once all the
configuration is done by AF for a PF/VF then packet I/O
can happen on PF/VF queues. When an interface
is brought up
From: Zyta Szpak
Four new mbox messages ids and handler are added in order to
enable or disable timestamping procedure on tx and rx side.
Additionally when PTP is enabled, the packet parser must skip
over 8 bytes and start analyzing packet data there. To make NPC
profiles work seemlesly PTR_ADVAN
From: Aleksey Makarov
This patch adds PTP clock and uses it in Octeontx2
network device. PTP clock uses mailbox calls to
access the hardware counter on the RVU side.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Aleksey Makarov
Signed-off-by: Sunil Goutham
From: Subbaraya Sundeep
Hi,
This patchset adds PTP support for Octeontx2 platform.
PTP is an independent coprocessor block from which
CGX block fetches timestamp and prepends it to the
packet before sending to NIX block. Patches are as
follows:
Patch 1: Patch to enable/disable packet timstampin
From: Aleksey Makarov
Precision Timestamping block found on Octeontx2
platform is an independent coprocessor and has
internal PTP hardware clock. Once configured PTP
runs independently and when a packet arrives
CGX hardware block gets the current timestamp
from PTP block and forwards the packet t
From: Aleksey Makarov
This patch adds PTP clock and uses it in Octeontx2
network device. PTP clock uses mailbox calls to
access the hardware counter on the RVU side.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Aleksey Makarov
Signed-off-by: Sunil Goutham
From: Aleksey Makarov
Precision Timestamping block found on Octeontx2
platform is an independent coprocessor and has
internal PTP hardware clock. Once configured PTP
runs independently and when a packet arrives
CGX hardware block gets the current timestamp
from PTP block and forwards the packet t
From: Zyta Szpak
Four new mbox messages ids and handler are added in order to
enable or disable timestamping procedure on tx and rx side.
Additionally when PTP is enabled, the packet parser must skip
over 8 bytes and start analyzing packet data there. To make NPC
profiles work seemlesly PTR_ADVAN
From: Subbaraya Sundeep
Hi,
This patchset adds PTP support for Octeontx2 platform.
PTP is an independent coprocessor block from which
CGX block fetches timestamp and prepends it to the
packet before sending to NIX block. Patches are as
follows:
Patch 1: Patch to enable/disable packet timstampin
From: Subbaraya Sundeep
Hi,
This patchset adds PTP support for Octeontx2 platform.
PTP is an independent coprocessor block from which
CGX block fetches timestamp and prepends it to the
packet before sending to NIX block. Patches are as
follows:
Patch 1: Patch to enable/disable packet timstampin
From: Aleksey Makarov
This patch adds PTP clock and uses it in Octeontx2
network device. PTP clock uses mailbox calls to
access the hardware counter on the RVU side.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Aleksey Makarov
Signed-off-by: Sunil Goutham
From: Zyta Szpak
Four new mbox messages ids and handler are added in order to
enable or disable timestamping procedure on tx and rx side.
Additionally when PTP is enabled, the packet parser must skip
over 8 bytes and start analyzing packet data there. To make NPC
profiles work seemlesly PTR_ADVAN
From: Aleksey Makarov
This patch adds driver for Precision Time
Protocol Clock and Timestamping block found on
Octeontx2 platform. The driver does initial
configuration and exposes a function to adjust
PTP hardware clock.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Sign
From: Subbaraya Sundeep
Hi,
This patchset adds PTP support for Octeontx2 platform.
PTP is an independent coprocessor block from which
CGX block fetches timestamp and prepends it to the
packet before sending to NIX block. Patches are as
follows:
Patch 1: Patch to enable/disable packet timstampin
From: Aleksey Makarov
This patch adds PTP clock and uses it in Octeontx2
network device. PTP clock uses mailbox calls to
access the hardware counter on the RVU side.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Aleksey Makarov
Signed-off-by: Sunil Goutham
From: Zyta Szpak
Four new mbox messages ids and handler are added in order to
enable or disable timestamping procedure on tx and rx side.
Additionally when PTP is enabled, the packet parser must skip
over 8 bytes and start analyzing packet data there. To make NPC
profiles work seemlesly PTR_ADVAN
From: Aleksey Makarov
This patch adds driver for Precision Time
Protocol Clock and Timestamping block found on
Octeontx2 platform. The driver does initial
configuration and exposes a function to adjust
PTP hardware clock.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Sign
From: Subbaraya Sundeep
During driver exit cancel the queued
reset_task work in VF driver.
Fixes: 3184fb5ba96e ("octeontx2-vf: Virtual function driver support")
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
---
v2 changes:
None
drivers/net/ethernet/marvell/octeontx2/
From: Subbaraya Sundeep
Added unregister_netdev in the driver remove
function. Generally unregister_netdev is called
after disabling all the device interrupts but here
it is called before disabling device mailbox
interrupts. The reason behind this is VF needs
mailbox interrupt to communicate with
From: Subbaraya Sundeep
Two bugs exist in the code related to reset_task
in PF driver one is the missing protection
against network stack ndo_open and ndo_close.
Other one is the missing cancel_work.
This patch fixes those problems.
Fixes: 4ff7d1488a84 ("octeontx2-pf: Error handling support")
Si
From: Subbaraya Sundeep
Hi,
There are problems in the existing Octeontx2
netdev drivers like missing cancel_work for the
reset task, missing lock in reset task and
missing unergister_netdev in driver remove.
This patch set fixes the above problems.
Thanks,
Sundeep
Subbaraya Sundeep (3):
oct
From: Subbaraya Sundeep
During driver exit cancel the queued
reset_task work in VF driver.
Fixes: 3184fb5ba96e ("octeontx2-vf: Virtual function driver support")
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c | 1 +
1 file
From: Subbaraya Sundeep
Hi,
There are problems in the existing Octeontx2
netdev drivers like missing cancel_work for the
reset task, missing lock in reset task and
missing unergister_netdev in driver remove.
This patch set fixes the above problems.
Thanks,
Sundeep
Subbaraya Sundeep (3):
octe
From: Subbaraya Sundeep
Two bugs exist in the code related to reset_task
in PF driver one is the missing protection
against network stack ndo_open and ndo_close.
Other one is the missing cancel_work.
This patch fixes those problems.
Fixes: 4ff7d1488a84 ("octeontx2-pf: Error handling support")
Si
From: Subbaraya Sundeep
unregister_netdev is missing in the VF driver
remove function. Hence add it.
Fixes: 3184fb5ba96e ("octeontx2-vf: Virtual function driver support")
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c | 1
From: Aleksey Makarov
This patch adds driver for Precision Time
Protocol Clock and Timestamping block found on
Octeontx2 platform. The driver does initial
configuration and exposes a function to adjust
PTP hardware clock.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Sign
From: Aleksey Makarov
This patch adds PTP clock and uses it in Octeontx2
network device. PTP clock uses mailbox calls to
access the hardware counter on the RVU side.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Aleksey Makarov
Signed-off-by: Sunil Goutham
From: Zyta Szpak
Four new mbox messages ids and handler are added in order to
enable or disable timestamping procedure on tx and rx side.
Additionally when PTP is enabled, the packet parser must skip
over 8 bytes and start analyzing packet data there. To make NPC
profiles work seemlesly PTR_ADVAN
From: Subbaraya Sundeep
Hi,
This patchset adds PTP support for Octeontx2 platform.
PTP is an independent coprocessor block from which
CGX block fetches timestamp and prepends it to the
packet before sending to NIX block. Patches are as
follows:
Patch 1: Patch to enable/disable packet timstampin
From: Aleksey Makarov
This patch adds PTP clock and uses it in Octeontx2
network device. PTP clock uses mailbox calls to
access the hardware counter on the RVU side.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Aleksey Makarov
Signed-off-by: Sunil Goutham
From: Aleksey Makarov
This patch adds driver for Precision Time
Protocol Clock and Timestamping block found on
Octeontx2 platform. The driver does initial
configuration and exposes a function to adjust
PTP hardware clock.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Sign
From: Zyta Szpak
Four new mbox messages ids and handler are added in order to
enable or disable timestamping procedure on tx and rx side.
Additionally when PTP is enabled, the packet parser must skip
over 8 bytes and start analyzing packet data there. To make NPC
profiles work seemlesly PTR_ADVAN
From: Subbaraya Sundeep
Hi,
This patchset adds PTP support for Octeontx2 platform.
PTP is an independent coprocessor block from which
CGX block fetches timestamp and prepends it to the
packet before sending to NIX block. Patches are as
follows:
Patch 1: Patch to enable/disable packet timstampin
From: Subbaraya Sundeep
Hi,
This patchset adds PTP support for Octeontx2 platform.
PTP is an independent coprocessor block from which
CGX block fetches timestamp and prepends it to the
packet before sending to NIX block. Patches are as
follows:
Patch 1: Patch to enable/disable packet timstampin
From: Aleksey Makarov
This patch adds PTP clock and uses it in Octeontx2
network device. PTP clock uses mailbox calls to
access the hardware counter on the RVU side.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Signed-off-by: Aleksey Makarov
Signed-off-by: Sunil Goutham
From: Zyta Szpak
Four new mbox messages ids and handler are added in order to
enable or disable timestamping procedure on tx and rx side.
Additionally when PTP is enabled, the packet parser must skip
over 8 bytes and start analyzing packet data there. To make NPC
profiles work seemlesly PTR_ADVAN
From: Aleksey Makarov
This patch adds driver for Precision Time
Protocol Clock and Timestamping block found on
Octeontx2 platform. The driver does initial
configuration and exposes a function to adjust
PTP hardware clock.
Co-developed-by: Subbaraya Sundeep
Signed-off-by: Subbaraya Sundeep
Sign
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