Update DT bindings to describe all of the clocks that the axienet
driver will now be able to make use of.
Acked-by: Rob Herring
Signed-off-by: Robert Hancock
---
.../bindings/net/xilinx_axienet.txt | 25 ++-
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git
well as the Xilinx device tree generator, except for mgt_clk
which is not present there.
For backward compatibility, if no named clocks are present, the first
clock present is used for determining the MDIO bus clock divider.
Reviewed-by: Radhey Shyam Pandey
Signed-off-by: Robert Hancock
Changed since v1:
-Clarified clock usages in documentation and code comments
Robert Hancock (2):
dt-bindings: net: xilinx_axienet: Document additional clocks
net: axienet: Enable more clocks
.../bindings/net/xilinx_axienet.txt | 25 ++
drivers/net/ethernet/xilinx
On Wed, 2021-03-24 at 11:08 -0600, Rob Herring wrote:
> On Fri, Mar 12, 2021 at 01:52:13PM -0600, Robert Hancock wrote:
> > Update DT bindings to describe all of the clocks that the axienet
> > driver will now be able to make use of.
> >
> > Si
On Sun, 2021-03-14 at 14:27 -0700, David Miller wrote:
> From: Robert Hancock
> Date: Thu, 11 Mar 2021 14:11:15 -0600
>
> > Add support to the axienet driver for controlling all of the clocks that
> > the logic core may utilize.
>
> This series does not apply
On Sat, 2021-03-13 at 02:45 +0100, Andrew Lunn wrote:
> On Thu, Mar 11, 2021 at 02:18:13PM -0600, Robert Hancock wrote:
> > When using a fixed-link configuration in SGMII mode, it's not really
> > sensible to have auto-negotiation enabled since the link settings are
> &g
well as the Xilinx device tree generator, except for mgt_clk
which is not present there.
For backward compatibility, if no named clocks are present, the first
clock present is used for determining the MDIO bus clock divider.
Reviewed-by: Radhey Shyam Pandey
Signed-off-by: Robert Hancock
Update DT bindings to describe all of the clocks that the axienet
driver will now be able to make use of.
Signed-off-by: Robert Hancock
---
.../bindings/net/xilinx_axienet.txt | 25 ++-
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation
nged since v1:
-Clarified clock usages in documentation and code comments
Robert Hancock (2):
dt-bindings: net: xilinx_axienet: Document additional clocks
net: axienet: Enable more clocks
.../bindings/net/xilinx_axienet.txt | 25 ++
drivers/net/ethernet/xilinx/xilinx
On Fri, 2021-03-12 at 18:39 +, Radhey Shyam Pandey wrote:
> > -Original Message-
> > From: Robert Hancock
> > Sent: Friday, March 12, 2021 11:13 PM
> > To: Radhey Shyam Pandey ; da...@davemloft.net;
> > k...@kernel.org
> > Cc: netdev@vger.kernel.org
Update DT bindings to describe all of the clocks that the axienet
driver will now be able to make use of.
Signed-off-by: Robert Hancock
---
.../bindings/net/xilinx_axienet.txt | 25 ++-
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation
e comments
Robert Hancock (2):
dt-bindings: net: xilinx_axienet: Document additional clocks
net: axienet: Enable more clocks
.../bindings/net/xilinx_axienet.txt | 25 ++
drivers/net/ethernet/xilinx/xilinx_axienet.h | 8 +++--
.../net/ethernet/xilinx/xilinx_axienet_m
well as the Xilinx device tree generator, except for mgt_clk
which is not present there.
For backward compatibility, if no named clocks are present, the first
clock present is used for determining the MDIO bus clock divider.
Reviewed-by: Radhey Shyam Pandey
Signed-off-by: Robert Hancock
On Thu, 2021-03-11 at 14:11 -0600, Robert Hancock wrote:
> This driver was only enabling the first clock on the device, regardless
> of its name. However, this controller logic can have multiple clocks
> which should all be enabled. Add support for enabling additional clocks.
> The
Some fixes to the macb driver for use in SGMII mode with a fixed-link (such as
for chip-to-chip connectivity).
Robert Hancock (2):
net: macb: poll for fixed link state in SGMII mode
net: macb: Disable PCS auto-negotiation for SGMII fixed-link mode
drivers/net/ethernet/cadence/macb.h
When using a fixed-link configuration in SGMII mode, it's not really
sensible to have auto-negotiation enabled since the link settings are
fixed by definition. In other configurations, such as an SGMII
connection to a PHY, it should generally be enabled.
Signed-off-by: Robert Ha
link state is actually up.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/cadence/macb_main.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index 15362d016a87..ca72a16c8da3 100644
--- a
well as the Xilinx device tree generator, except for mgt_clk
which is not present there.
For backward compatibility, if no named clocks are present, the first
clock present is used for determining the MDIO bus clock divider.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx
Update DT bindings to describe all of the clocks that the axienet
driver will now be able to make use of.
Signed-off-by: Robert Hancock
---
.../bindings/net/xilinx_axienet.txt | 23 ++-
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/Documentation
Add support to the axienet driver for controlling all of the clocks that
the logic core may utilize.
Robert Hancock (2):
dt-bindings: net: xilinx_axienet: Document additional clocks
net: axienet: Enable more clocks
.../bindings/net/xilinx_axienet.txt | 23 +
drivers
The driver did not always clean up all allocated resources when probe
failed. Fix the probe cleanup path to clean up everything that was
allocated.
Fixes: 57baf8cc70 ("net: axienet: Handle deferred probe on clock properly")
Signed-off-by: Robert Hancock
---
.../net/ether
Add a flag and helper function to indicate that a PHY device is part of
an SFP module, which is set on attach. This can be used by PHY drivers
to handle SFP-specific quirks or behavior.
Signed-off-by: Robert Hancock
---
drivers/net/phy/phy_device.c | 2 ++
include/linux/phy.h | 11
. Skip this configuration for PHYs which are bound to an SFP
bus.
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 8e7fc3368380
/datasheets/powersolutions/ds-bps-sfp-1gbt-05-series.pdf
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-06-series.pdf
Signed-off-by: Robert Hancock
Acked-by: Florian Fainelli
---
drivers/net/phy/broadcom.c | 84 --
include/linux/brcmphy.h
indentation
-Added missing setting of MII_BCM54XX_AUXCTL_MISC_WREN in
MII_BCM54XX_AUXCTL_SHDWSEL_MISC register
Robert Hancock (3):
net: phy: broadcom: Set proper 1000BaseX/SGMII interface mode for
BCM54616S
net: phy: Add is_on_sfp_module flag and phy_on_sfp helper
net: phy: broadcom: Do not
. Skip this configuration for PHYs which are bound to an SFP
bus.
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 8e7fc3368380
Add a flag and helper function to indicate that a PHY device is part of
an SFP module, which is set on attach. This can be used by PHY drivers
to handle SFP-specific quirks or behavior.
Signed-off-by: Robert Hancock
---
drivers/net/phy/phy_device.c | 2 ++
include/linux/phy.h | 11
/datasheets/powersolutions/ds-bps-sfp-1gbt-05-series.pdf
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-06-series.pdf
Signed-off-by: Robert Hancock
Acked-by: Florian Fainelli
---
drivers/net/phy/broadcom.c | 84 --
include/linux/brcmphy.h
MII_BCM54XX_AUXCTL_MISC_WREN in
MII_BCM54XX_AUXCTL_SHDWSEL_MISC register
Robert Hancock (3):
net: phy: broadcom: Set proper 1000BaseX/SGMII interface mode for
BCM54616S
net: phy: Add is_on_sfp_module flag and phy_on_sfp helper
net: phy: broadcom: Do not modify LED configuration for SFP module
interface.
Signed-off-by: Robert Hancock
---
Changed since v1: Fixed typo and added more explanation in commit message
drivers/net/phy/marvell.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index
On Sat, 2021-02-13 at 10:45 +, Russell King - ARM Linux admin wrote:
> On Fri, Feb 12, 2021 at 08:18:40PM -0600, Robert Hancock wrote:
> > + if (!phydev->sfp_bus &&
> > + (!phydev->attached_dev || !phydev->attached_dev->sfp_bus)) {
>
> First
On Sat, 2021-02-13 at 17:43 +0100, Andrew Lunn wrote:
> On Fri, Feb 12, 2021 at 06:23:56PM -0600, Robert Hancock wrote:
> > Newer versions of the Xilinx AXI Ethernet core (specifically version 7.2 or
> > later) allow the core to be configured with a PHY interface mode of "B
. Skip this configuration for PHYs which are bound to an SFP
bus.
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 484791ac236b
/datasheets/powersolutions/ds-bps-sfp-1gbt-05-series.pdf
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-06-series.pdf
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 84 --
include/linux/brcmphy.h| 4 ++
2 files changed
Updates to the Broadcom PHY driver related to use with copper SFP modules.
Changed since v1:
-Reversed conditional to reduce indentation
-Added missing setting of MII_BCM54XX_AUXCTL_MISC_WREN in
MII_BCM54XX_AUXCTL_SHDWSEL_MISC register
Robert Hancock (2):
net: phy: broadcom: Set proper
On Fri, 2021-02-12 at 17:26 -0800, Florian Fainelli wrote:
>
> On 2/12/2021 4:28 PM, 'Robert Hancock' via BCM-KERNEL-FEEDBACK-LIST,PDL
> wrote:
> > The default configuration for the BCM54616S PHY may not match the desired
> > mode when using 1000BaseX or SGMII inte
On Sat, 2021-02-13 at 01:09 +, Russell King - ARM Linux admin wrote:
> On Fri, Feb 12, 2021 at 06:26:29PM -0600, Robert Hancock wrote:
> > When 88E111 is operating in SGMII mode, auto-negotiation should be enabled
>
> 88E.
yup..
>
> > on the SGMII side so th
some
other mode like 1000BaseX, as may happen in some SFP module situations,
it may not be.
Call genphy_check_and_restart_aneg on the fiber page to ensure that auto-
negotiation is properly enabled on the SGMII interface.
Signed-off-by: Robert Hancock
---
drivers/net/phy/marvell.c | 13
Document the new xlnx,switch-x-sgmii attribute which is used to indicate
that the Ethernet core supports dynamic switching between 1000BaseX and
SGMII.
Signed-off-by: Robert Hancock
---
Documentation/devicetree/bindings/net/xilinx_axienet.txt | 4
1 file changed, 4 insertions(+)
diff
Hook up the nway_reset ethtool operation to the corresponding phylink
function so that "ethtool -r" can be supported.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ether
Updates to the Broadcom PHY driver related to use with copper SFP modules.
Robert Hancock (2):
net: phy: broadcom: Set proper 1000BaseX/SGMII interface mode for
BCM54616S
net: phy: broadcom: Do not modify LED configuration for SFP module
PHYs
drivers/net/phy/broadcom.c | 109
plications
which can use both fiber and copper SFP modules.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 29 +
.../net/ethernet/xilinx/xilinx_axienet_main.c | 60 ---
2 files changed, 71 insertions(+), 18 deletions(-)
diff --git a/d
. Skip this configuration for PHYs which are bound to an SFP
bus.
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 78542580f2b2
/datasheets/powersolutions/ds-bps-sfp-1gbt-05-series.pdf
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-06-series.pdf
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 83 --
include/linux/brcmphy.h| 4 ++
2 files changed
using an MDIO
bus, as the clock is required in any case.
Fixes: 09a0354cadec267be7f ("net: axienet: Use clock framework to get device
clock rate")
Signed-off-by: Robert Hancock
---
.../net/ethernet/xilinx/xilinx_axienet_main.c | 26 +--
1 file changed, 12 inserti
Updates to the Xilinx AXI Ethernet driver to add support for an additional
ethtool operation, and to support dynamic switching between 1000BaseX and
SGMII interface modes.
Robert Hancock (3):
net: axienet: hook up nway_reset ethtool operation
dt-bindings: net: xilinx_axienet: add xlnx,switch
Figured I would poke someone to add this patch to the stable queue - I
don't see it in
https://patchwork.kernel.org/bundle/netdev/stable/?state=* right now.
This patch is reported to fix a severe upload speed regression in many
Intel wireless adapters existing since kernel 5.9, as described in
http
://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf
Signed-off-by: Robert Hancock
Reviewed-by: Russell King
---
Changed since v4: Fixed coding style in m88e_config_init_1000basex.
drivers/net/phy/marvell.c | 100 +++-
include
Update the axienet driver to properly support the Xilinx PCS/PMA PHY
component which is used for 1000BaseX and SGMII modes, including
properly configuring the auto-negotiation mode of the PHY and reading
the negotiated state from the PHY.
Signed-off-by: Robert Hancock
---
Changed since v2
On Tue, 2020-10-27 at 14:25 +, Radhey Shyam Pandey wrote:
> > -Original Message-
> > From: Robert Hancock
> > Sent: Tuesday, October 27, 2020 1:15 AM
> > To: Radhey Shyam Pandey ; da...@davemloft.net;
> > k...@kernel.org
> > Cc: li...@armlin
On Mon, 2020-10-26 at 18:57 +, Radhey Shyam Pandey wrote:
> Thanks for the patch.
>
> > -Original Message-
> > From: Robert Hancock
> > Sent: Monday, October 26, 2020 11:26 PM
> > To: Radhey Shyam Pandey ; da...@davemloft.net;
> > k...@
The Xilinx PCS/PMA PHY requires that BMCR_ISOLATE be disabled for proper
operation in 1000BaseX mode. It should be safe to ensure this bit is
disabled in phylink_mii_c22_pcs_config in all cases.
Signed-off-by: Robert Hancock
Reviewed-by: Russell King
---
Resubmit tagged for net-next.
drivers
://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf
Signed-off-by: Robert Hancock
Reviewed-by: Russell King
---
Changed in v4: Fixed variable order in m88e_config_aneg, added Russell's
Reviewed-by
drivers/net/phy/marvell.c
Update the axienet driver to properly support the Xilinx PCS/PMA PHY
component which is used for 1000BaseX and SGMII modes, including
properly configuring the auto-negotiation mode of the PHY and reading
the negotiated state from the PHY.
Signed-off-by: Robert Hancock
---
Resubmit of v2 tagged
://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf
Signed-off-by: Robert Hancock
---
Changed since v2: Renamed 1000BX -> 1000X to avoid confusion with 1000Base-BX
drivers/net/phy/marvell.c | 99 -
include/linux/marvell_ph
The Xilinx PCS/PMA PHY requires that BMCR_ISOLATE be disabled for proper
operation in 1000BaseX mode. It should be safe to ensure this bit is
disabled in phylink_mii_c22_pcs_config in all cases.
Signed-off-by: Robert Hancock
---
drivers/net/phy/phylink.c | 3 ++-
1 file changed, 2 insertions
://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf
Signed-off-by: Robert Hancock
---
drivers/net/phy/marvell.c | 99 -
include/linux/marvell_phy.h | 3 ++
2 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/drivers
Update the axienet driver to properly support the Xilinx PCS/PMA PHY
component which is used for 1000BaseX and SGMII modes, including
properly configuring the auto-negotiation mode of the PHY and reading
the negotiated state from the PHY.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet
to a Linux PC on the other end, but
unfortunately ethtool doesn't seem to report the link partner
advertisements on that adapter, only the host advertisements (Intel
82574L, e1000e).
--
Robert Hancock
Senior Hardware Designer, Advanced Technologies
www.calian.com
estion as I'm not
familiar with all the other setups where this part would be used. So
I'm inclined to leave that part specific to this ID.
--
Robert Hancock
Senior Hardware Designer, Advanced Technologies
www.calian.com
1000BaseT between the module PHY and the
copper link partner. I believe the 88E has some smarts to delay the
copper negotiation until it gets the advertisement over 1000BaseX, uses
those to figure out its advertisement, and then uses the copper link
partner's response to determine the 1000Ba
MII_BMCR, BMCR_ISOLATE, 0);
>
> Hi Robert
>
> That looks like a layering violation. Maybe move this into
> phylink_mii_c22_pcs_config(), it is accessing MII_BMCR anyway.
Could do - do we think there's any harm in just disabling BMCR_ISOLATE
in all cases in that function?
--
Robert Hancock
Senior Hardware Designer, Advanced Technologies
www.calian.com
g_init could likely be merged into
m88e_config_init.
Mainly what stopped me from making all of these changes generic to all
88E is that I'm a bit less confident in the different config_aneg
behavior, it might be more specific to this SFP copper module case?
--
Robert Hancock
Senior Hardware Designer, Advanced Technologies
www.calian.com
On Mon, 2020-10-19 at 22:08 +0100, Russell King - ARM Linux admin
wrote:
> On Mon, Oct 19, 2020 at 02:49:13PM -0600, Robert Hancock wrote:
> > The Finisar FCLF8520P2BTL 1000BaseT SFP module uses a Marvel
> > 81E PHY
>
> You mean 88E here.
>
Whoops, will f
Hancock
---
drivers/net/phy/marvell.c | 82 +
include/linux/marvell_phy.h | 3 ++
2 files changed, 85 insertions(+)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 5aec673a0120..8d85c96209ad 100644
--- a/drivers/net/phy/marvell.c
Update the axienet driver to properly support the Xilinx PCS/PMA PHY
component which is used for 1000BaseX and SGMII modes, including
properly configuring the auto-negotiation mode of the PHY and reading
the negotiated state from the PHY.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet
On 2020-04-28 5:01 p.m., Russell King - ARM Linux admin wrote:
On Tue, Apr 28, 2020 at 03:59:45PM -0600, Robert Hancock wrote:
On 2020-04-22 1:51 a.m., Russell King - ARM Linux admin wrote:
On Tue, Apr 21, 2020 at 07:45:47PM -0600, Robert Hancock wrote:
Hi Andre/Russell,
Just wondering where
On 2020-04-22 1:51 a.m., Russell King - ARM Linux admin wrote:
On Tue, Apr 21, 2020 at 07:45:47PM -0600, Robert Hancock wrote:
Hi Andre/Russell,
Just wondering where things got to with the changes for SGMII on Xilinx
axienet that you were discussing (below)? I am looking into our Xilinx setup
A couple of enhancements to the Microchip KSZ switch driver: one to add
PHY register settings for errata workarounds for more stable operation, and
another to add a device tree option to change the output clock rate as
required by some board designs.
Robert Hancock (2):
net: dsa: microchip: Add
The KSZ9477 series chips have a SYNCLKO pin which by default outputs a
25MHz clock, but some board setups require a 125MHz clock instead. Added
a microchip,synclko-125 device tree property to allow indicating a
125MHz clock output is required.
Signed-off-by: Robert Hancock
---
Documentation
: Robert Hancock
---
drivers/net/dsa/microchip/ksz9477.c | 62
drivers/net/dsa/microchip/ksz_priv.h | 1 +
2 files changed, 63 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz9477.c
b/drivers/net/dsa/microchip/ksz9477.c
index c026d15..7be6d84 100644
counter reading
support")
Signed-off-by: Robert Hancock
---
drivers/net/dsa/microchip/ksz_common.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz_common.c
b/drivers/net/dsa/microchip/ksz_common.c
index 39dace8..f46086f 100644
--- a/drivers/net/dsa/microchip
de
in the first place. Add this in.
Signed-off-by: Robert Hancock
---
drivers/net/phy/phy_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 03c885e..5387890 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/p
18.031159] 7fc0:
[ 18.031166] 7fe0: 0013
[ 18.031176] Code: 1a06 e51630e0 e0833405 e5933050 (e593302c)
[ 18.031279] ---[ end trace ca82392a6c2aa959 ]---
--
Robert Hancock
We were accessing the pointer returned from platform_get_resource before
checking if it was valid, causing an oops if it was not. Move this access
after the call to devm_ioremap_resource which does the validity check.
Signed-off-by: Robert Hancock
---
This bug was introduced in my recent
link
>>> modes - I view what you've done there as a hack rather than proper
>>> design.
>
> I do have the beginnings of a quirk system for the sfp-bus layer,
> since I've been conversing with someone with a GPON module that
> does appear to follow the SFP MSA, in particular with regard to the
> time it takes the module to start responding on I2C, and in regard
> of the speeds it actually supports (basically, the EEPROM is
> misleading.) So, that should be useful for you as well.
>
> http://git.armlinux.org.uk/cgit/linux-arm.git/log/?h=phy
>
> is my playground of patches for SFP, which are in various stages of
> maturity, some which have been posted for inclusion (and merged)
> others that have been waiting some time.
>
--
Robert Hancock
Senior Software Developer
SED Systems, a division of Calian Ltd.
Email: hanc...@sedsystems.ca
On 2019-06-02 9:15 a.m., Russell King - ARM Linux admin wrote:
> On Fri, May 31, 2019 at 06:17:51PM -0600, Robert Hancock wrote:
>> Our device is mainly intended for fiber modules, which is why 1000BaseX
>> is being used. The variant of fiber modules we are using (for exam
interrupts and stop all delayed work in the SFP
driver during the shutdown process, so that we ensure that no pending
operations are still occurring after the SFP shutdown completes.
Signed-off-by: Robert Hancock
---
Changed since v1: Free interrupts during shutdown to avoid need for shutdown
sm_mutex nests inside of it.
Suggested-by: Russell King
Signed-off-by: Robert Hancock
---
drivers/net/phy/sfp.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c
index 01af080..edd2de5 100644
--- a/drivers/net/phy/sfp.c
+++ b
This has an updated version of an earlier patch to ensure that SFP
operations are stopped during shutdown, and another patch suggested by
Russell King to address a potential concurrency issue with SFP state
checks.
Robert Hancock (2):
net: sfp: Stop SFP polling and interrupt handling during
On 2019-06-07 4:42 a.m., Russell King - ARM Linux admin wrote:
> On Thu, Jun 06, 2019 at 02:57:22PM -0600, Robert Hancock wrote:
>> The idea there was to deal with the case where GPIO interrupts were
>> previously raised before shutdown and not yet handled by the threaded
>>
The axienet driver requires the use of an axistream-connected attribute,
but this isn't documented in the devicetree bindings. Document how this
attribute is supposed to be used, including the upcoming change to make
the usage of this attribute optional.
Signed-off-by: Robert Ha
Failing initialization on a missing MAC address property is excessive.
We can just fall back to using a random MAC instead, which at least
leaves the interface in a functioning state.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 5 +++--
1 file changed
Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 6e75c43..d138db8 100644
--- a/drivers/net/ethernet/xilinx
Add support for setting the RX and TX ring sizes for this driver using
ethtool. Also increase the default RX ring size as the previous default
was far too low for good performance in some configurations.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 2
clock used for the device in the device
tree using the clock framework. If the clock is specified then it will
be used when calculating the clock divisor. The previous CPU clock
detection method is left for backward compatibility if no clock is
specified.
Signed-off-by: Robert Hancock
These registers are important for troubleshooting the state of the DMA
cores.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
b
the actual Ethernet register block.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 ++
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 1 +
drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c | 11 +--
3 files changed, 8 insertions(+), 6
The mdio child node for the MDIO bus is generally required when using
this driver but was not documented other than being shown in the
example. Document it as an optional (but usually required) parameter.
Signed-off-by: Robert Hancock
---
Documentation/devicetree/bindings/net/xilinx_axienet.txt
Convert this driver to use the phylink API rather than the legacy PHY
API. This allows for better support for SFP modules connected using a
1000BaseX or SGMII interface.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/Kconfig | 2 +-
drivers/net/ethernet/xilinx
.
Also, lock the MDIO bus lock around the device reset process, to avoid
MDIO accesses from occurring while the MDIO is disabled during the reset.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 3 +-
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 38
needs to be specified in the device tree.
Signed-off-by: Robert Hancock
---
.../devicetree/bindings/net/xilinx_axienet.txt | 3 +-
drivers/net/ethernet/xilinx/xilinx_axienet.h | 1 +
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 49 ++
3 files changed, 52
this should be relatively safe.
Signed-off-by: Robert Hancock
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
b/drivers/net/ethernet/xilinx/xi
This driver should now build on (at least) X86 and ARM platforms, so add
them as supported platforms for the driver in Kconfig.
Signed-off-by: Robert Hancock
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/xilinx/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
Specify IRQF_SHARED to support shared interrupts. If the interrupt
handler is called and the device is not indicating an interrupt,
just return IRQ_NONE rather than spewing error messages.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 14 --
1
such.
Signed-off-by: Robert Hancock
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 11 +++---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 26 ---
2 files changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/net
are completely stopped.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 +
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 54 +--
2 files changed, 42 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/xilinx
accessors.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 4 ++--
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h
b/drivers/net/ethernet
te is specified.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 43 +++
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
wakeup and the adapter's transmit hanging.
To avoid this, after stopping the queue, check again whether there is
sufficient space in the TX ring. If so, wake up the queue again.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 20 +---
1
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