> > The limitation is not on the MAC, PCS or the PHY. For Intel mgbe, the
> > overclocking of 2.5 times clock rate to support 2.5G is only able to
> > be configured in the BIOS during boot time. Kernel driver has no
> > access to modify the clock rate for 1Gbps/2.5G mode. The way to
> > determined
> > > You have a MAC and an PCS in the stmmac IP block. That then has some
> > > sort of SERDES interface, running 1000BaseX, SGMII, SGMII
> > > overclocked at 2.5G or 25000BaseX. Connected to the SERDES you have
> > > a PHY which converts to copper, giving you 2500BaseT.
> > >
> > > You said earli
EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
sequence and vice versa.
Signed-off-by: Voon Weifeng
---
Changes:
v1 -> v2
-change subject from "net: intel" to "stmmac: intel"
---
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 +
EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
sequence and vice versa.
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 ++
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 +
2 files changed, 11 insertions(+)
diff
> On Fri, Apr 02, 2021 at 07:45:04AM +0000, Voon, Weifeng wrote:
> > > > + /* 2.5G mode only support 2500baseT full duplex only */
> > > > + if (priv->plat->has_gmac4 && priv->plat->speed_2500_en) {
> > > >
> > + /* 2.5G mode only support 2500baseT full duplex only */
> > + if (priv->plat->has_gmac4 && priv->plat->speed_2500_en) {
> > + phylink_set(mac_supported, 2500baseT_Full);
> > + phylink_set(mask, 10baseT_Half);
> > + phylink_set(mask, 10baseT_Full);
> > +
ch TX intr and RX intr (TI/RI) will be handled by TX/RX ISR
without the need of calling the common MAC ISR.
Updated the TX/RX NORMAL interrupts status checking process as the
NIS status bit is not asserted for any RI/TI events for INTM=1.
Signed-off-by: Wong, Vee Khee
Co-developed-by: Voon Weife
ned-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
Changes:
v1 -> v2
- Refactor out a huge if statement into separate subfunctions.
- Removed the netdev_info for every successful request of IRQs.
- Return 0 for each successful request of IRQs.
---
drivers/net/ethernet/stmicro/stmma
-vector interrupts. If it fails, then it will automatically fallback
to request allocation for single interrupts.
Signed-off-by: Ong Boon Leong
Co-developed-by: Voon Weifeng
Signed-off-by: Voon Weifeng
---
Changes:
v1 -> v2
- Moved the msi tx/rx base vector check before alloc irq
- Restuctu
From: Ong Boon Leong
Refactor stmmac_interrupt() by introducing stmmac_common_interrupt()
so that we prepare the ISR operation to be friendly to MSI later.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
Changes:
v1 -> v2
-Remove defensive check for invalid dev poin
From: Ong Boon Leong
In preparation to make stmmac support multi-vector MSI, we introduce the
interrupt status masking according to RX, TX or RXTX. Default to use RXTX
inside stmmac_dma_interrupt(), so there is no run-time logic difference
now.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon
This patchset adds support for multi MSI interrupts in addition to
current single common interrupt implementation. Each MSI interrupt is tied
to a newly introduce interrupt service routine(ISR). Hence, each interrupt
will only go through the corresponding ISR.
In order to increase the efficiency,
> On Tue, 16 Mar 2021 20:18:21 +0800 Voon Weifeng wrote:
> > From: Ong Boon Leong
> >
> > Now we introduce MSI interrupt service routines and hook these
> > routines up if stmmac_open() sees valid irq line being requested:-
> >
> > stmmac_mac_interrupt()
ch TX intr and RX intr (TI/RI) will be handled by TX/RX ISR
without the need of calling the common MAC ISR.
Updated the TX/RX NORMAL interrupts status checking process as the
NIS status bit is not asserted for any RI/TI events for INTM=1.
Signed-off-by: Wong, Vee Khee
Co-developed-by: Voon Weife
ned-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 15 +
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 16 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 415 --
include/linux/stmmac.h| 8 +
From: Ong Boon Leong
In preparation to make stmmac support multi-vector MSI, we introduce the
interrupt status masking according to RX, TX or RXTX. Default to use RXTX
inside stmmac_dma_interrupt(), so there is no run-time logic difference
now.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon
-vector interrupts. If it fails, then it will automatically fallback
to request allocation for single interrupts.
Signed-off-by: Ong Boon Leong
Co-developed-by: Voon Weifeng
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/dwmac-intel.c | 112 +-
1 file changed
From: Ong Boon Leong
Refactor stmmac_interrupt() by introducing stmmac_common_interrupt()
so that we prepare the ISR operation to be friendly to MSI later.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 59 +++
1
This patchset adds support for multi MSI interrupts in addition to
current single common interrupt implementation. Each MSI interrupt is tied
to a newly introduce interrupt service routine(ISR). Hence, each interrupt
will only go through the corresponding ISR.
In order to increase the efficiency,
-vector interrupts. If it fails, then it will automatically fallback
to request allocation for single interrupts.
Signed-off-by: Ong Boon Leong
Co-developed-by: Voon Weifeng
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/dwmac-intel.c | 112 +-
1 file changed
ch TX intr and RX intr (TI/RI) will be handled by TX/RX ISR
without the need of calling the common MAC ISR.
Updated the TX/RX NORMAL interrupts status checking process as the
NIS status bit is not asserted for any RI/TI events for INTM=1.
Signed-off-by: Wong, Vee Khee
Co-developed-by: Voon Weife
ned-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 15 +
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 16 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 415 --
include/linux/stmmac.h| 8 +
From: Ong Boon Leong
Refactor stmmac_interrupt() by introducing stmmac_common_interrupt()
so that we prepare the ISR operation to be friendly to MSI later.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 59 +++
1
From: Ong Boon Leong
In preparation to make stmmac support multi-vector MSI, we introduce the
interrupt status masking according to RX, TX or RXTX. Default to use RXTX
inside stmmac_dma_interrupt(), so there is no run-time logic difference
now.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon
This patchset adds support for multi MSI interrupts in addition to
current single common interrupt implementation. Each MSI interrupt is tied
to a newly introduce interrupt service routine(ISR). Hence, each interrupt
will only go through the corresponding ISR.
In order to increase the efficiency,
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
v3 changelog:
-Changed stmmac_lpi_entry_timer_config() to static function
v2 changelog:
-removed #define for LPI_ET_ENABLE and LPI_ET_DISABLE and directly use
literals
-removed not require
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
v3 changelog:
-Changed stmmac_lpi_entry_timer_config() to static function
v2 changelog:
-removed #define for LPI_ET_ENABLE and LPI_ET_DISABLE and directly use
literals
-removed not require
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
v2 changelog:
-removed #define for LPI_ET_ENABLE and LPI_ET_DISABLE and directly use
literals
-removed not required function header in stmmac.h
-renamed stmmac_lpi_entry_timer_e
alue is configured through ethtool. The driver will auto
> select the LPI HW timer if the value in the HW timer supported range.
> Else, the driver will fallback to SW timer.
>
> Signed-off-by: Vineetha G. Jaya Kumaran
> Signed-off-by: Voon Weifeng
Please help to review and comment. Thanks.
Weifeng
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 3 ++
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 2 ++
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 24 ++
drivers/ne
imer supported range.
> Else, the driver will fallback to SW timer.
>
> Signed-off-by: Vineetha G. Jaya Kumaran
> Signed-off-by: Voon Weifeng
> ---
Please drop this patch. Sorry for accidentally sending out this patch.
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 3 ++
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 2 ++
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 24 ++
drivers/ne
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 3 ++
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 2 ++
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 24 +++
drivers/ne
"stmmac: add the Energy Efficient Ethernet support")
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
Changelog V2
*Not removing/modifying the eee_timer.
*EEE LPI timer can be configured through ethtool and also the eee_timer
module param.
*EEE TW Timer will be configure
h is not correct.
Hence, this patch fixes the the configuration of LPI TW timer via
module parameters instead of ethtool. And, "ethtool --set-eee tx-timer"
should configure EEE LPI timer.
Fixes: d765955d2ae0 ("stmmac: add the Energy Efficient Ethernet support")
Signed-off-by: Vin
From: Rusaimi Amira Ruslan
Adding reference clock (1us tic) for all LPI timer on Intel platforms.
The reference clock is derived from ptp clk. This also enables all LPI
counter.
Signed-off-by: Rusaimi Amira Ruslan
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/dwmac
e58ad6 ("net: stmmac: Fix a race in EEE enable callback")
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
b/drive
> On Wed, Sep 04, 2019 at 10:02:54PM +0800, Voon Weifeng wrote:
> > From: "Chuah, Kim Tatt"
> >
> > DW EQoS v5.xx controllers added capability for interrupt generation
> > when MDIO interface is done (GMII Busy bit is cleared).
> > This patch adds su
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