On Sat, Sep 26, 2020 at 08:52:17PM +0200, Marek Vasut wrote:
> On 9/9/20 10:38 AM, Richard Leitner wrote:
> > On Fri, Sep 04, 2020 at 09:23:26PM +0200, Marek Vasut wrote:
> >> On 9/4/20 9:02 PM, Richard Leitner wrote:
> >>> On Fri, Sep 04, 2020 at 05:26:14PM +0200, Ma
On Fri, Sep 04, 2020 at 09:23:26PM +0200, Marek Vasut wrote:
> On 9/4/20 9:02 PM, Richard Leitner wrote:
> > On Fri, Sep 04, 2020 at 05:26:14PM +0200, Marek Vasut wrote:
> >> On 9/4/20 4:02 PM, Andrew Lunn wrote:
> >>> On Fri, Sep 04, 2020 at 12:45:44AM +0200, Marek
mail.com
> >>>>
> >>>> That might be a fix for the long run, but I doubt there's any chance to
> >>>> backport it all to stable, is there ?
> >>>
> >>> No. For stable we need something simpler.
> >>
> >>
From: Richard Leitner
As suggested by Rob Herring [1] rename the previously introduced
reset-{,post-}delay-us bindings to the clearer reset-{,de}assert-us
[1] https://patchwork.kernel.org/patch/10104905/
Signed-off-by: Richard Leitner
---
Documentation/devicetree/bindings/net/phy.txt | 8
Hi Rob,
On 12/15/2017 11:17 PM, Rob Herring wrote:
> On Mon, Dec 11, 2017 at 01:16:57PM +0100, Richard Leitner wrote:
>> From: Richard Leitner
>>
>> Some PHYs need a minimum time after the reset gpio was asserted and/or
>> deasserted. To ensure we meet these timi
From: Richard Leitner
Some PHYs need the refclk to be a continuous clock. Therefore they don't
allow turning it off and on again during operation. Nonetheless such a
clock switching is performed by some ETH drivers (namely FEC [1]) for
power saving reasons. An example for an affected PHY i
From: Richard Leitner
This patch series fixes the use of the SMSC LAN8710/20 with a Freescale ETH
when the refclk is generated by the FSL.
This patchset depends on the "phylib: Add device reset GPIO support" patch
submitted by Geert Uytterhoeven/Sergei Shtylyov, which was merged to
n
From: Richard Leitner
Some PHYs need a minimum time after the reset gpio was asserted and/or
deasserted. To ensure we meet these timing requirements add two new
optional devicetree parameters for the phy: reset-delay-us and
reset-post-delay-us.
Signed-off-by: Richard Leitner
Reviewed-by: Geert
From: Richard Leitner
Some PHYs (for example the SMSC LAN8710/LAN8720) doesn't allow turning
the refclk on and off again during operation (according to their
datasheet). Nonetheless exactly this behaviour was introduced for power
saving reasons by commit e8fcfcd5684a ("net: fec: op
From: Richard Leitner
The Microchip/SMSC LAN8710/LAN8720 PHYs need (according to their
datasheet [1]) a continuous REF_CLK when configured to "REF_CLK In Mode".
Therefore set the PHY_RST_AFTER_CLK_EN flag for those PHYs to let the
ETH driver reset them after the REF_CLK is enabled.
Hi Geert,
On 12/07/2017 03:52 PM, Geert Uytterhoeven wrote:
> Hi Richard,
>
> On Thu, Dec 7, 2017 at 3:43 PM, Richard Leitner wrote:
>> --- a/drivers/net/phy/mdio_device.c
>> +++ b/drivers/net/phy/mdio_device.c
>> @@ -24,6 +24,7 @@
>> #include
>>
From: Richard Leitner
Some PHYs need a minimum time after the reset gpio was asserted and/or
deasserted. To ensure we meet these timing requirements add two new
optional devicetree parameters for the phy: reset-delay-us and
reset-post-delay-us.
Signed-off-by: Richard Leitner
Reviewed-by: Geert
From: Richard Leitner
The Microchip/SMSC LAN8710/LAN8720 PHYs need (according to their
datasheet [1]) a continuous REF_CLK when configured to "REF_CLK In Mode".
Therefore set the PHY_RST_AFTER_CLK_EN flag for those PHYs to let the
ETH driver reset them after the REF_CLK is enabled.
From: Richard Leitner
Some PHYs (for example the SMSC LAN8710/LAN8720) doesn't allow turning
the refclk on and off again during operation (according to their
datasheet). Nonetheless exactly this behaviour was introduced for power
saving reasons by commit e8fcfcd5684a ("net: fec: op
From: Richard Leitner
This patch series fixes the use of the SMSC LAN8710/20 with a Freescale ETH
when the refclk is generated by the FSL.
This patchset depends on the "phylib: Add device reset GPIO support" patch
submitted by Geert Uytterhoeven/Sergei Shtylyov, which was merged to
n
From: Richard Leitner
Some PHYs need the refclk to be a continuous clock. Therefore they don't
allow turning it off and on again during operation. Nonetheless such a
clock switching is performed by some ETH drivers (namely FEC [1]) for
power saving reasons. An example for an affected PHY i
Hi Andy,
On 12/06/2017 02:50 AM, Andy Duan wrote:
> From: Richard Leitner Sent: Tuesday, December 05, 2017 9:26
> PM
>> Some PHYs (for example the SMSC LAN8710/LAN8720) doesn't allow turning
>> the refclk on and off again during operation (according to their datasheet).
Hi Andrew,
On 12/05/2017 06:34 PM, Andrew Lunn wrote:
On Tue, Dec 05, 2017 at 02:25:58PM +0100, Richard Leitner wrote:
From: Richard Leitner
Some PHYs need the refclk to be a continuous clock. Therefore they don't
allow turning it off and on again during operation. Nonetheless such a
Hi Andrew,
On 12/05/2017 06:28 PM, Andrew Lunn wrote:
Hi Richard
+++ b/drivers/of/of_mdio.c
@@ -77,6 +77,14 @@ static int of_mdiobus_register_phy(struct mii_bus *mdio,
if (of_property_read_bool(child, "broken-turn-around"))
mdio->phy_ignore_ta_mask |= 1 << addr;
+ if
Hi Geert,
On 12/05/2017 02:54 PM, Geert Uytterhoeven wrote:
> Hi Richard,
>
> On Tue, Dec 5, 2017 at 2:25 PM, Richard Leitner wrote:
>> From: Richard Leitner
>>
>> Some PHYs need a minimum time after the reset gpio was asserted and/or
>> deasserted. To ensure
From: Richard Leitner
Some PHYs need a minimum time after the reset gpio was asserted and/or
deasserted. To ensure we meet these timing requirements add two new
optional devicetree parameters for the phy: reset-delay-us and
reset-post-delay-us.
This patch depends on the "phylib: Add d
From: Richard Leitner
This patch series fixes the use of the SMSC LAN8710/20 with a Freescale ETH
when the refclk is generated by the FSL.
This patch depends on the "phylib: Add device reset GPIO support" patch
submitted by Geert Uytterhoeven/Sergei Shtylyov, see:
From: Richard Leitner
Some PHYs need the refclk to be a continuous clock. Therefore they don't
allow turning it off and on again during operation. Nonetheless such a
clock switching is performed by some ETH drivers (namely FEC [1]) for
power saving reasons. An example for an affected PHY i
From: Richard Leitner
Some PHYs (for example the SMSC LAN8710/LAN8720) doesn't allow turning
the refclk on and off again during operation (according to their
datasheet). Nonetheless exactly this behaviour was introduced for power
saving reasons by commit e8fcfcd5684a ("net: fec: op
From: Richard Leitner
The Microchip/SMSC LAN8710/LAN8720 PHYs need (according to their
datasheet [1]) a continuous REF_CLK when configured to "REF_CLK In Mode".
Therefore set the PHY_RST_AFTER_CLK_EN flag for those PHYs to let the
ETH driver reset them after the REF_CLK is enabled.
ng initial setup]
> [geert: Consolidate GPIO descriptor acquiring code]
> Signed-off-by: Geert Uytterhoeven
> ---
Successfully tested this patch on a i.MX6SOLO based board containing a
LAN8710 PHY:
Tested-by: Richard Leitner
On 11/27/2017 02:50 PM, Andrew Lunn wrote:
> On Mon, Nov 27, 2017 at 08:16:45AM +0100, Richard Leitner wrote:
>> From: Richard Leitner
>>
>> Previously phy_id was u32 and phy_id_mask was unsigned int. As the
>> phy_id_mask defines the important bits of the phy_id (a
From: Richard Leitner
Previously phy_id was u32 and phy_id_mask was unsigned int. As the
phy_id_mask defines the important bits of the phy_id (and is therefore
the same size) these two variables should be the same data type.
Signed-off-by: Richard Leitner
Reviewed-by: Florian Fainelli
From: Richard Leitner
Previously phy_id was u32 and phy_id_mask was unsigned int. As the
phy_id_mask defines the important bits of the phy_id (and is therefore
the same size) these two variables should be the same data type.
Signed-off-by: Richard Leitner
---
This patch is extracted from the
On 11/20/2017 02:13 PM, Geert Uytterhoeven wrote:
> Hi Richard,
>
> On Mon, Nov 20, 2017 at 1:55 PM, Richard Leitner
> wrote:
>> On 11/20/2017 11:35 AM, Andy Duan wrote:
>>> 3. add reset gpio descriptor for common phy device driver.
>>
>> ... if I understo
On 11/20/2017 11:35 AM, Andy Duan wrote:
> From: Richard Leitner Sent: Monday, November
> 20, 2017 5:57 PM
>> To: Andy Duan ; f.faine...@gmail.com;
>> and...@lunn.ch
>> Cc: Richard Leitner ; netdev@vger.kernel.org; linux-
>> ker...@vger.kernel.org
>> Subje
On 11/20/2017 10:47 AM, Andy Duan wrote:
> From: Richard Leitner Sent: Monday, November 20, 2017 4:34
> PM
>> To: f.faine...@gmail.com; Andy Duan ;
>> and...@lunn.ch
>> Cc: netdev@vger.kernel.org; linux-ker...@vger.kernel.org;
>> richard.leit...@skidata.com
From: Richard Leitner
The fec_reset_phy function allowed only one execution during probeing.
To make it more usable move the dt parsing and gpio allocation to the
probe function. The parameters of the phy reset are added to the
fec_enet_private struct. As a result the fec_reset_phy function may
From: Richard Leitner
Previously phy_id was u32 and phy_id_mask was unsigned int. As the
phy_id_mask defines the important bits of the phy_id (and is therefore the
same size) these two variables should be the same datatype.
Signed-off-by: Richard Leitner
---
include/linux/phy.h | 2 +-
1 file
From: Richard Leitner
Some PHYs (for example the SMSC LAN8710/LAN8720) doesn't allow turning
the refclk on and off again during operation (according to their
datasheet). Nonetheless exactly this behaviour was introduced for power
saving reasons by commit e8fcfcd5684a ("net: fec: op
From: Richard Leitner
This patch series fixes the use of the SMSC LAN8710/20 with a Freescale ETH
when the refclk is generated by the FSL.
Changes v2:
- simplify and fix fec_reset_phy function to support multiple calls
- include: linux: phy: harmonize phy_id{,_mask} type
On 10/23/2017 01:01 AM, Richard Leitner wrote:
On 10/23/2017 12:48 AM, Florian Fainelli wrote
On 10/22/2017 03:30 PM, Richard Leitner wrote:
On 10/22/2017 08:31 PM, Florian Fainelli wrote:
On 10/22/2017 06:11 AM, Richard Leitner wrote:
...
But back to this patch: Is it OK the way it
On 10/23/2017 12:48 AM, Florian Fainelli wrote> On 10/22/2017 03:30 PM,
Richard Leitner wrote:
On 10/22/2017 08:31 PM, Florian Fainelli wrote:
On 10/22/2017 06:11 AM, Richard Leitner wrote:
...
Andrew Lunn suggested to make the PHY driver a clock driver and let it
export the refclk...
On 10/22/2017 08:31 PM, Florian Fainelli wrote:
On 10/22/2017 06:11 AM, Richard Leitner wrote:
From: Richard Leitner
From: Richard Leitner
Some PHYs (for example the LAN8710) doesn't allow turning the ethernet
ref clocks off and on again without reset (according to their data
From: Richard Leitner
From: Richard Leitner
Some PHYs (for example the LAN8710) doesn't allow turning the ethernet
ref clocks off and on again without reset (according to their datasheet).
Exactly this behaviour was introduced for power saving reasons by
commit e8fcfcd5684a (&quo
On 07/07/2017 04:00 PM, Andrew Lunn wrote:
>> Ok. I'm fine with moving the phy-reset-gpios binding into the PHY.
>> But one question still remains: Who should then trigger the "hard
>> reset" of the PHY?
>
> Hi Richard
>
> I think i see a few whys to do this, but first i need to check
> somethin
Hi Andy,
thanks for the clarifications!
On 07/07/2017 01:08 PM, Andy Duan wrote:
3. Who should then trigger the "hard reset" of the PHY? phy_init_hw? The FEC?
The point is that the LAN8710 is currently not always working correctly,
therefore this small change was proposed. Should we really chan
On 07/07/2017 09:03 AM, Andy Duan wrote:
From: Richard Leitner Sent: Friday, July 07, 2017
1:51 PM
Since it is common issue so long as using the PHY, can you move it into smsc
phy driver like in .smsc_phy_reset() function ?
And get the reset pin from phy dts node.
Some more points that
On 07/07/2017 07:30 AM, Andy Duan wrote:
From: Richard Leitner Sent: Thursday, July 06,
2017 9:06 PM
To: Andy Duan ; robh...@kernel.org;
mark.rutl...@arm.com
Cc: netdev@vger.kernel.org; devicet...@vger.kernel.org; linux-
ker...@vger.kernel.org; d...@g0hl1n.net; Richard Leitner
Subject
On 07/06/2017 03:55 PM, Andrew Lunn wrote:
>> diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt
>> b/Documentation/devicetree/bindings/net/fsl-fec.txt
>> index 6f55bdd..1766579 100644
>> --- a/Documentation/devicetree/bindings/net/fsl-fec.txt
>> +++ b/Documentation/devicetree/binding
anytime after probe.
Signed-off-by: Richard Leitner
---
drivers/net/ethernet/freescale/fec.h | 4 ++
drivers/net/ethernet/freescale/fec_main.c | 85 ---
2 files changed, 47 insertions(+), 42 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec.h
b
om/thread/389902
https://community.nxp.com/message/309354
With this patch applied the issue didn't occur for at least a few
hundred PORs of our board.
Fixes: e8fcfcd5684a ("net: fec: optimize the clock management to sa...")
Signed-off-by: Richard Leitner
---
Documenta
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