Add support for Amethyst internal PHY.
The only difference from Peridot is HWMON.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell.c | 117 +++-
include/linux/marvell_phy.h | 1 +
2 files changed, 115 insertions(+), 3 deletions(-)
diff --git a/drivers
Amethyst internal PHYs also report empty model number in MII_PHYSID2.
Fill in switch product number, as is done for Topaz and Peridot.
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/dsa/mv88e6xxx/chip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/dsa
Use the &= operator instead of
ret = ret & ...
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 9529aaa3bed3..e505060d074
Here are some updates for Marvell PHY HWMON, mainly
- refactoring for code deduplication
- Amethyst PHY support
Changes since v1:
- addressed Andrew's comments
- fixed macro names
MII_88E6393_MISC_TEST_SAMPLES_4096 to _2048
MII_88E6393_MISC_TEST_SAMPLES_8192 to _4096
...
Marek Beh
Use a structure of Marvell PHY specific HWMON methods to reduce code
duplication. Store a pointer to this structure into the PHY driver's
driver_data member.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell.c | 369 +-
1 file changed, 125 inser
is reserved, although it is R/W. Since the code works, I think we can
assume that it is correct.)
Rename this register and define all 4 values according to 6393X
documentation.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell.c | 19 +--
1 file changed, 9 insertions(+), 10
On Tue, 13 Apr 2021 16:36:35 +0200
Andrew Lunn wrote:
> > +static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types
> > type,
> > + u32 attr, int channel, long *temp)
> > {
> > struct phy_device *phydev = dev_get_drvdata(dev);
> > - int err;
> > +
On Tue, 13 Apr 2021 16:25:33 +0200
Andrew Lunn wrote:
> On Tue, Apr 13, 2021 at 09:55:35AM +0200, Marek Behún wrote:
> > Register 27_6.15:14 has the following description in 88E6393X
> > documentation:
> > Temperature Sensor Enable
> > 0x0 - Sample every 1s
>
Amethyst internal PHYs also report empty model number in MII_PHYSID2.
Fill in switch product number, as is done for Topaz and Peridot.
Signed-off-by: Marek Behún
---
drivers/net/dsa/mv88e6xxx/chip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers
the 6390 code uses this register currently,
but the 6390 code handles it as two 1-bit registers (somewhat), instead
of one register with 4 possible values.
Rename this register and define all 4 values according to 6393X
documentation.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell.c | 19
Use the &= operator instead of
ret = ret & ...
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index bae2a225b550..9eb65898da83 100644
--- a/drivers
Add support for Amethyst internal PHY.
The only difference from Peridot is HWMON.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell.c | 117 +++-
include/linux/marvell_phy.h | 1 +
2 files changed, 115 insertions(+), 3 deletions(-)
diff --git a/drivers
Here are some updates for Marvell PHY HWMON, mainly
- refactoring for code deduplication
- Amethyst PHY support
Marek Behún (5):
net: phy: marvell: refactor HWMON OOP style
net: phy: marvell: fix HWMON enable register for 6390
net: phy: marvell: use assignment by bitwise AND operator
net
Use a structure of Marvell PHY specific HWMON methods to reduce code
duplication. Store a pointer to this structure into the PHY driver's
driver_data member.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell.c | 371 +-
1 file changed, 127 inser
On Mon, 12 Apr 2021 18:38:29 +0200
Pali Rohár wrote:
> On Monday 12 April 2021 18:12:35 Andrew Lunn wrote:
> > On Mon, Apr 12, 2021 at 05:52:39PM +0200, Pali Rohár wrote:
> > > On Monday 12 April 2021 17:32:33 Andrew Lunn wrote:
> > > > > Anyway, now I'm looking at phy/marvell.c driver again
On Mon, 12 Apr 2021 15:16:59 +0300
Ivan Bornyakov wrote:
> Some SFP modules uses RX_LOS for link indication. In such cases link
> will be always up, even without cable connected. RX_LOS changes will
> trigger link_up()/link_down() upstream operations. Thus, check that SFP
> link is operational be
> + /* Some internal PHYs don't have a model number. */
> + if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
> + chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
> + prod_id = family_prod_id_table[chip->info->family];
> + if (prod_id)
> +
On Wed, 7 Apr 2021 09:14:29 +0200
Arnd Bergmann wrote:
> On Wed, Apr 7, 2021 at 2:24 AM Marek Behún wrote:
> >
> > The -Wextra flag enables -Woverride-init in newer versions of GCC.
> >
> > This causes the compiler to warn when a value is written twice in a
>
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 90 +---
1 file changed, 54 insertions(+), 36 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 20d3e572c935..2dc1317e601e 100644
--- a/drivers/net/phy/marvell1
Add all MACTYPE definitions for 88E2110, 88E2180, 88E2111 and 88E2181.
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index
Add all MACTYPE definitions for 88X3310, 88X3310P, 88X3340 and 88X3340P.
In order to have consistent naming, rename
MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH to
MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH.
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c
Rename port control registers to indicate that they are valid only for
88X33x0, not for 88E21x0.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy
This module supports not only Alaska X, but also Alaska M.
Change module description appropriately.
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers
Add constants for 2.5G and 5G speed in PCS speed register into mdio.h.
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
include/uapi/linux/mdio.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index 3f302e2523b2..bdf77dffa5a4
88E2111 is a variant of 88E2110 which does not support 5 gigabit speeds.
Differentiate these variants via the match_phy_device() method, since
they have the same PHY ID.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 62
1 file changed, 62
Add myself as maintainer of the marvell10g ethernet PHY driver, in
addition to Russell King.
Signed-off-by: Marek Behún
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 217c7470bfa9..3ea9539821b5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
The 88X3340 contains 4 cores similar to 88X3310, but there is a
difference: it does not support xaui host mode. Instead the
corresponding MACTYPE means
rxaui / 5gbase-r / 2500base-x / sgmii without AN
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 58
The driver name "mv88x2110" should be instead "mv88e2110".
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.
Now that we have a chip structure, we can store the temperature reading
method in this structure (OOP style).
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a
setting
the MACTYPE register). There is work in progress to enable this driver
to deduce the best MACTYPE from the knowledge of which interface modes
are supported by the host, but this work is not finished yet.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 103
These modes are also supported by these PHYs.
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index f2f0da9717be
This space should be a tab instead.
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 9b514124af0d..f2f0da9717be 100644
--- a
The 88E2110 does not support xaui nor rxaui modes. Check for correct
interface mode for different chips.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 37 +---
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy
The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.
Signed-off-by: Marek Behún
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers
-port SXGMII modes
are ignored for now)
Changes since v1:
- added various MACTYPEs support also for 88E21XX
- differentiate between specific models with same PHY_ID
- better check for compatible interface
- print exact model
Marek Behún (16):
net: phy: marvell10g: rename register
net
On Wed, 7 Apr 2021 09:14:29 +0200
Arnd Bergmann wrote:
> On Wed, Apr 7, 2021 at 2:24 AM Marek Behún wrote:
> >
> > The -Wextra flag enables -Woverride-init in newer versions of GCC.
> >
> > This causes the compiler to warn when a value is written twice in a
>
MAP(bm, 64) = INITIALIZE_BITMAP(0, 1, 32, 33);
can only be implemented by allowing a designated initializer to
initialize the same members multiple times (because the compiler
complains even if the multiple initializations initialize to the same
value).
Disable the -Woverride-init flag.
Signed-off-by: Marek
On Wed, 7 Apr 2021 02:10:24 +0200
Andrew Lunn wrote:
> > @@ -479,8 +479,8 @@ static int mv3310_config_init(struct phy_device *phydev)
> > val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
> > if (val < 0)
> > return val;
> > - priv->rate_match = ((val & MV_V2_PORT
On Wed, 7 Apr 2021 01:33:33 +0200
Andrew Lunn wrote:
> On Wed, Apr 07, 2021 at 12:10:56AM +0200, Marek Behún wrote:
> > Add support for all rate matching modes for 88X3310 (currently only
> > 10gbase-r is supported, but xaui and rxaui can also be used).
> >
> > Add su
On Wed, 7 Apr 2021 01:38:30 +0200
Andrew Lunn wrote:
> On Wed, Apr 07, 2021 at 12:10:58AM +0200, Marek Behún wrote:
> > Use the new variadic-macro.h library to implement macro
> > INITIALIZE_BITMAP(nbits, ...), which can be used for compile time bitmap
> > initialization in
On Wed, 7 Apr 2021 01:30:28 +0200
Andrew Lunn wrote:
> > +static inline const struct mv3310_chip *
> > +to_mv3310_chip(struct phy_device *phydev)
> > +{
> > + return phydev->drv->driver_data;
> > +}
>
> No inline functions in C code please. Let the compiler decide.
>
>Andrew
Fixed in m
Add myself as maintainer of the marvell10g ethernet PHY driver, in
addition to Russell King.
Signed-off-by: Marek Behún
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 217c7470bfa9..3ea9539821b5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
This module supports not not only Alaska X, but also Alaska M.
Change module description appropriately.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
88E2111 is a variant of 88E2110 which does not support 5 gigabit speeds.
Differentiate these variants via the match_phy_device() method, since
they have the same PHY ID.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 59
1 file changed, 59
The driver name "mv88x2110" should be instead "mv88e2110".
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 74a91853ef46..51b7a
Add constants for 2.5G and 5G speed in PCS speed register into mdio.h.
Signed-off-by: Marek Behún
---
include/uapi/linux/mdio.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index 3f302e2523b2..bdf77dffa5a4 100644
--- a/include/uapi
The 88X3340 contains 4 cores similar to 88X3310, but there is a
difference: it does not support xaui host mode. Instead the
corresponding MACTYPE means
rxaui / 5gbase-r / 2500base-x / sgmii without AN
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 55
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 90 +---
1 file changed, 54 insertions(+), 36 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index a7c7c87201fa..2fd823318de8 100644
--- a/drivers/net/phy/marvell1
Now that we have a chip structure, we can store the temperature reading
method in this structure (OOP style).
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b
The 88E2110 does not support xaui nor rxaui modes. Check for correct
interface mode for different chips.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b
-time
error if an argument is out of range.
Signed-off-by: Marek Behún
---
include/linux/bitmap.h | 24
1 file changed, 24 insertions(+)
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index 70a932470b2d..a9e74d3420bf 100644
--- a/include/linux/bitmap.h
+++ b
This space should be a tab instead.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 9b514124af0d..f2f0da9717be 100644
--- a/drivers/net/phy
The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index
models with same PHY_ID
- better check for compatible interface
- print exact model
Marek Behún (18):
net: phy: marvell10g: rename register
net: phy: marvell10g: fix typo
net: phy: marvell10g: allow 5gbase-r and usxgmii
net: phy: marvell10g: indicate 88X33x0 only port control registers
Add support for all rate matching modes for 88X3310 (currently only
10gbase-r is supported, but xaui and rxaui can also be used).
Add support for rate matching for 88E2110 (on 88E2110 the MACTYPE
register is at a different place).
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c
) used to implement a sane
way for compile-time bitmap initialization, something like
static DECLARE_BITMAP(bm, 100) = INITIALIZE_BITMAP(100, 7, 9, 66, 98);
Signed-off-by: Marek Behún
---
include/linux/variadic-macro.h | 221 +
1 file changed, 221 insertions
Add all MACTYPE definitions for 88E2110, 88E2180, 88E2111 and 88E2181.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 7d9a45437b69..556c9b43860e 100644
Add all MACTYPE definitions for 88X3310, 88X3310P, 88X3340 and 88X3340P.
In order to have consistent naming, rename
MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH to
MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 18
These modes are also supported by these PHYs.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index f2f0da9717be..881a0717846e 100644
--- a/drivers
Rename port control registers to indicate that they are valid only for
88X33x0, not for 88E21x0.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy
On Fri, 26 Mar 2021 09:07:34 +
Russell King - ARM Linux admin wrote:
> > Nice, didn't know about that. But I fear whether this would always work
> > for the 88X3310 vs 88X3310P, it is possible that this feature is only
> > recognizable if the firmware in the PHY is already running.
>
> The
On Thu, 25 Mar 2021 21:44:21 +0100
Heiner Kallweit wrote:
> On 25.03.2021 21:29, Marek Behún wrote:
> > On Thu, 25 Mar 2021 15:54:52 +
> > Russell King - ARM Linux admin wrote:
> >
> >> The 88X3310 and 88X3340 can be differentiated by bit 3 in the revision
On Thu, 25 Mar 2021 15:54:52 +
Russell King - ARM Linux admin wrote:
> The 88X3310 and 88X3340 can be differentiated by bit 3 in the revision.
> In other words, 88X3310 is 0x09a0..0x09a7, and 88X3340 is
> 0x09a8..0x09af. We could add a separate driver structure, which would
> then allow the k
On Thu, 25 Mar 2021 15:54:52 +
Russell King - ARM Linux admin wrote:
> On Thu, Mar 25, 2021 at 02:12:49PM +0100, Marek Behún wrote:
> > @@ -443,12 +446,24 @@ static int mv3310_probe(struct phy_device *phydev)
> >
> > switch (phydev->drv->phy_id) {
> >
On Thu, 25 Mar 2021 14:12:49 +0100
Marek Behún wrote:
> Print exact mode, one of
typo: model
Add constants for 2.5G and 5G speed in PCS speed register into mdio.h.
Signed-off-by: Marek Behún
---
include/uapi/linux/mdio.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index 3f302e2523b2..bdf77dffa5a4 100644
--- a/include/uapi
Do a model-specific check for compatible interface:
- 88X3340 does not support XAUI
- 88E21XX does not support XAUI and RXAUI
- 88E21X1 does not support 5gbase-r
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 38
1 file changed, 25 insertions
Print exact mode, one of
88E2110
88E2111
88E2180
88E2181
88X3310
88X3310P
88X3340
88X3340P
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b
Add support for all rate matching modes, not only for 10gbase-r.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 67 ++--
1 file changed, 57 insertions(+), 10 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
Currently the only "changing" MACTYPE we support is when the PHY changes
between
10gbase-r / 5gbase-r / 2500base-x / sgmii
Add support for
xaui / 5gbase-r / 2500base-x / sgmii
rxaui / 5gbase-r / 2500base-x / sgmii
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell
Add code to determine number of ports, from which we differentiate
88E211X from 88E218X and 88X3310 from 88X3340.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 44 +++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy
Add all MACTYPE definitions for 88E2110, 88E2180, 88E2111 and 88E2181.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 7d9a45437b69..556c9b43860e 100644
Indicate via register names registers that are only valid for 88X33X0,
not for 88E21X0.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
This modes are also supported by this PHYs.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index f2f0da9717be..881a0717846e 100644
--- a/drivers
Add all MACTYPE definitions for 88X3310, 88X3310P, 88X3340 and 88X3340P.
In order to have consistent naming, rename
MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH to
MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 18
Here are some updates for marvell10g PHY driver.
Changes since v1:
- added various MACTYPEs support also for 88E21XX
- differentiate between specific models with same PHY_ID
- better check for compatible interface
- print exact model
Marek Behún (12):
net: phy: marvell10g: rename register
This space should be a tab instead.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 9b514124af0d..f2f0da9717be 100644
--- a/drivers/net/phy
The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index
On Wed, 24 Mar 2021 17:11:25 -0700
Florian Fainelli wrote:
> On 3/24/2021 4:45 PM, Marek Behún wrote:
> > On Wed, 24 Mar 2021 16:16:41 -0700
> > Florian Fainelli wrote:
> >
> >> On 3/24/2021 4:00 PM, Marek Behún wrote:
> >>> On Wed, 24 Mar 2021 14
On Wed, 24 Mar 2021 16:16:41 -0700
Florian Fainelli wrote:
> On 3/24/2021 4:00 PM, Marek Behún wrote:
> > On Wed, 24 Mar 2021 14:19:28 -0700
> > Florian Fainelli wrote:
> >
> >>> Another problem is that if lower modes are supported, we should
> >&
On Wed, 24 Mar 2021 14:19:28 -0700
Florian Fainelli wrote:
> > Another problem is that if lower modes are supported, we should
> > maybe use them in order to save power.
>
> That is an interesting proposal but if you want it to be truly valuable,
> does not that mean that an user ought to be a
On Wed, 24 Mar 2021 14:07:06 -0600
Rob Herring wrote:
> On Wed, Mar 24, 2021 at 11:35:55AM +0100, Marek Behún wrote:
> > In order to be able to define a property describing an array of PHY
> > interface modes, we need to change the current scalar
> > `phy-connection-t
On Wed, 24 Mar 2021 16:59:46 +
Russell King - ARM Linux admin wrote:
> On Wed, Mar 24, 2021 at 05:50:21PM +0100, Marek Behún wrote:
> > Save MACTYPE instead of rate_matching boolean. We will need this for
> > other configurations.
>
> This could lead us to having
On Wed, 24 Mar 2021 16:58:36 +
Russell King - ARM Linux admin wrote:
> On Wed, Mar 24, 2021 at 05:50:20PM +0100, Marek Behún wrote:
> > Add all MACTYPE definitions for 88X3310/88X3310P.
> >
> > In order to have consistent naming, rename
> > MV_V2_PORT
Here are some updates for marvell10g PHY driver.
Marek Behún (7):
net: phy: marvell10g: rename register
net: phy: marvell10g: fix typo
net: phy: marvell10g: allow 5gabse-r and usxgmii
net: phy: marvell10g: add MACTYPE definitions for 88X3310/88X3310P
net: phy: marvell10g: save MACTYPE
Currently the only "changing" MACTYPE we support is when the PHY changes
between
10gbase-r / 5gbase-r / 2500base-x / sgmii
Add support for
xaui / 5gbase-r / 2500base-x / sgmii
rxaui / 5gbase-r / 2500base-x / sgmii
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell
The 88X3310P supports rate matching mode also for XAUI and RXAUI.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index b4f9831b4db6
This space should be a tab instead.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 96c081a7ec54..567e7900e5b8 100644
--- a/drivers/net/phy
Save MACTYPE instead of rate_matching boolean. We will need this for
other configurations.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index
This modes are also supported by this PHYs.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 567e7900e5b8..70639b9393f3 100644
--- a/drivers/net
Add all MACTYPE definitions for 88X3310/88X3310P.
In order to have consistent naming, rename
MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH to
MV_V2_PORT_CTRL_MACTYPE_10GR_RATE_MATCH.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 13 ++---
1 file changed, 10 insertions(+), 3
The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.
Signed-off-by: Marek Behún
---
drivers/net/phy/marvell10g.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index
property is missing, all modes
supported by the PHY and MAC are presumed to be supported by the board.
Signed-off-by: Marek Behún
---
.../devicetree/bindings/net/ethernet-phy.yaml | 18 ++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ethernet
.
Signed-off-by: Marek Behún
---
.../bindings/net/ethernet-controller.yaml | 89 ++-
1 file changed, 48 insertions(+), 41 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
that the same
list does not have to be defined twice.
Marek
Marek Behún (2):
dt-bindings: ethernet-controller: create a type for PHY interface
modes
dt-bindings: ethernet-phy: define `supported-mac-connection-types`
property
.../bindings/net/ethernet-controller.yaml | 89
On Mon, 22 Mar 2021 22:11:04 +0100
Andrew Lunn wrote:
> On Mon, Mar 22, 2021 at 08:49:58PM +0100, Marek Behún wrote:
> > In order to be able to define a property describing an array of PHY
> > interface modes, we need to change the current scalar
> > `phy-connection-t
On Mon, 22 Mar 2021 19:56:05 +
Russell King - ARM Linux admin wrote:
> On Mon, Mar 22, 2021 at 08:49:59PM +0100, Marek Behún wrote:
> > diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml
> > b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
> &g
.
Signed-off-by: Marek Behún
---
Is `phy-connection-type` prefered over `phy-mode`? If not, maybe the
type could be called `phy-modes-array`...
---
.../bindings/net/ethernet-controller.yaml | 89 ++-
1 file changed, 48 insertions(+), 41 deletions(-)
diff --git a/Documentation
-types`,
which lists these unsupported modes.
Signed-off-by: Marek Behún
---
As in the previous patch: we allow both `phy-connection-type` and
`phy-mode` to define PHY interface mode. Should we call this new
property as it is proposed by this patch, or something different,
like `unsupported-mac
-types`,
which lists these unsupported modes.
Signed-off-by: Marek Behún
---
As in the previous patch: we allow both `phy-connection-type` and
`phy-mode` to define PHY interface mode. Should we call this new
property as it is proposed by this patch, or something different,
like `unsupported-mac
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