Re: [PATCH 6/9] riscv: bpf: Move bpf_jit_alloc_exec() and bpf_jit_free_exec() to core

> We will drop the executable permissions of the code pages from the > mapping at allocation time soon. Move bpf_jit_alloc_exec() and > bpf_jit_free_exec() to bpf_jit_core.c so that they can be shared by > both RV64I and RV32I. Looks good to me. Acked-by: Luke Nelson

Re: [PATCH bpf-next v2 0/3] RISC-V selftest/bpf fixes

Nice, thanks for the fixes! (For the whole series:) Acked-by: Luke Nelson

Re: [PATCH] arm64: bpf: Fix branch offset in JIT

On Mon, Sep 14, 2020 at 11:08 AM Xi Wang wrote: > I don't think there's some consistent semantics of "offsets" across > the JITs of different architectures (maybe it's good to clean that > up). RV64 and RV32 JITs are doing something similar to arm64 with > respect to offsets. CCing Björn and Luk

[PATCH bpf-next v1 2/3] bpf, riscv: Add encodings for compressed instructions

t;c.add rd, rs2" when rd == rs1. To make using RVC encodings simpler, this patch also adds helper functions that selectively emit either a regular instruction or a compressed instruction if possible. For example, emit_add will produce a "c.add" if possible and regular "add"

[PATCH bpf-next v1 0/3] bpf, riscv: Add compressed instructions to rv64 JIT

it value in "lower" + The immediate checks for emit_{addiw,li,addi} use signed comparisons, so this enables the RVC variants to be used more often (e.g., if val == -1, then lower should be -1 as opposed to 4095). Luke Nelson (3): bpf, riscv: Modify JIT

[PATCH bpf-next v1 3/3] bpf, riscv: Use compressed instructions in the rv64 JIT

c.ldsp s3,16(sp) 68: 6a22c.ldsp s4,8(sp) 6a: 6145c.addi16sp sp,48 6c: 853ec.mva0,a5 6e: 8082c.jrra Cc: Björn Töpel Signed-off-by: Luke Nelson --- Björn: I added you as Cc instead of Acked-by for this patch so you would have a chance to review

[PATCH bpf-next v1 1/3] bpf, riscv: Modify JIT ctx to support compressed instructions

insns_rvoff" function to simplify the code. Signed-off-by: Luke Nelson --- arch/riscv/net/bpf_jit.h| 31 --- arch/riscv/net/bpf_jit_comp32.c | 14 +++--- arch/riscv/net/bpf_jit_comp64.c | 12 ++-- arch/riscv/net/bpf_jit_core.c | 6 +++--- 4 f

Re: [RFC PATCH bpf-next 0/3] bpf, riscv: Add compressed instructions to rv64 JIT

> > First of all; Really nice work. I like this, and it makes the code > easier to read as well (e.g. emit_mv). I'm a bit curious why you only > did it for RV64, and not RV32? I have some minor comments on the > patches. I strongly encourage you to submit this as a proper (non-RFC) > set for bpf-ne

[RFC PATCH bpf-next 2/3] bpf, riscv: Add encodings for compressed instructions

t;c.add rd, rs2" when rd == rs1. To make using RVC encodings simpler, this patch also adds helper functions that selectively emit either a regular instruction or a compressed instruction if possible. For example, emit_add will produce a "c.add" if possible and regular "add"

[RFC PATCH bpf-next 0/3] bpf, riscv: Add compressed instructions to rv64 JIT

s1,32(sp) 64: 6962c.ldsp s2,24(sp) 66: 69c2c.ldsp s3,16(sp) 68: 6a22c.ldsp s4,8(sp) 6a: 6145c.addi16sp sp,48 6c: 853ec.mva0,a5 6e: 8082c.jr ra Luke Nelson (3): bpf, riscv: Modify JIT ctx to support compressed instruct

[RFC PATCH bpf-next 3/3] bpf, riscv: Use compressed instructions in the rv64 JIT

c.ldsp s2,24(sp) 66: 69c2c.ldsp s3,16(sp) 68: 6a22c.ldsp s4,8(sp) 6a: 6145c.addi16sp sp,48 6c: 853ec.mva0,a5 6e: 8082c.jrra Signed-off-by: Luke Nelson --- arch/riscv/net/bpf_jit_comp64.c | 275 +

[RFC PATCH bpf-next 1/3] bpf, riscv: Modify JIT ctx to support compressed instructions

off-by: Luke Nelson --- arch/riscv/net/bpf_jit.h| 23 --- arch/riscv/net/bpf_jit_comp32.c | 14 +++--- arch/riscv/net/bpf_jit_comp64.c | 12 ++-- arch/riscv/net/bpf_jit_core.c | 6 +++--- 4 files changed, 36 insertions(+), 19 deletions(-) diff --git

[PATCH bpf-next v2 2/3] bpf, arm64: Optimize AND,OR,XOR,JSET BPF_K using arm64 logical immediates

encoding process is quite complex, the JIT reuses existing functionality in arch/arm64/kernel/insn.c for encoding logical immediates rather than duplicate it in the JIT. Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson Acked-by: Daniel Borkmann --- arch/arm64/net/bpf_jit.h

[PATCH bpf-next v2 3/3] bpf, arm64: Optimize ADD,SUB,JMP BPF_K using arm64 add/sub immediates

ad of time. Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson Acked-by: Daniel Borkmann --- arch/arm64/net/bpf_jit.h | 8 arch/arm64/net/bpf_jit_comp.c | 36 +-- 2 files changed, 38 insertions(+), 6 deletions(-) diff --

[PATCH bpf-next v2 1/3] arm64: insn: Fix two bugs in encoding 32-bit logical immediates

Signed-off-by: Luke Nelson Reviewed-by: Marc Zyngier Suggested-by: Will Deacon --- arch/arm64/kernel/insn.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 4a9e773a177f..cc2f3d901c91 100644 --- a/ar

[PATCH bpf-next v2 0/3] arm64 BPF JIT Optimizations

/arm64/kernel/insn.c using Serval. The series also fixes the two bugs before introducing the optimizations. Tested on aarch64 QEMU virt machine using test_bpf and test_verifier. v2: - Cleaned up patch to insn.c. (Marc Zyngier, Will Deacon) Luke Nelson (3): arm64: insn: Fix two bugs in encoding

Re: [RFC PATCH bpf-next 1/3] arm64: insn: Fix two bugs in encoding 32-bit logical immediates

Hi Will, On Fri, May 8, 2020 at 4:47 AM Will Deacon wrote: > > Yes, please! And please include Daniel's acks on the BPF changes too. It's a > public holiday here in the UK today, but I can pick this up next week. Thanks! > Nice! Two things: > > (1) I really think you should give a talk on this

Re: [RFC PATCH bpf-next 1/3] arm64: insn: Fix two bugs in encoding 32-bit logical immediates

Hi everyone, Thanks for the comments! Responses below: > It's a bit grotty spreading the checks out now. How about we tweak things > slightly along the lines of: > > > diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c > index 4a9e773a177f..60ec788eaf33 100644 > --- a/arch/arm64/ker

[RFC PATCH bpf-next 1/3] arm64: insn: Fix two bugs in encoding 32-bit logical immediates

h all 1,302 encodable 32-bit logical immediates and all 5,334 encodable 64-bit logical immediates. Fixes: ef3935eeebff ("arm64: insn: Add encoder for bitwise operations using literals") Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson --- arch/arm64/ke

[RFC PATCH bpf-next 0/3] arm64 BPF JIT Optimizations

/arm64/kernel/insn.c using Serval. The series also fixes the two bugs before introducing the optimizations. Tested on aarch64 QEMU virt machine using test_bpf and test_verifier. Luke Nelson (3): arm64: insn: Fix two bugs in encoding 32-bit logical immediates bpf, arm64: Optimize AND,OR,XOR,JSET

[RFC PATCH bpf-next 3/3] bpf, arm64: Optimize ADD,SUB,JMP BPF_K using arm64 add/sub immediates

ad of time. Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson --- arch/arm64/net/bpf_jit.h | 8 arch/arm64/net/bpf_jit_comp.c | 36 +-- 2 files changed, 38 insertions(+), 6 deletions(-) diff --git a/arch/arm64/net/bpf_ji

[RFC PATCH bpf-next 2/3] bpf, arm64: Optimize AND,OR,XOR,JSET BPF_K using arm64 logical immediates

encoding process is quite complex, the JIT reuses existing functionality in arch/arm64/kernel/insn.c for encoding logical immediates rather than duplicate it in the JIT. Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson --- arch/arm64/net/bpf_jit.h | 14

[PATCH bpf-next 2/4] bpf, riscv: Optimize FROM_LE using verifier_zext on RV64

Signed-off-by: Xi Wang Signed-off-by: Luke Nelson --- arch/riscv/net/bpf_jit_comp64.c | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c index e2636902a74e..c3ce9a911b66 100644 --- a/arch

[PATCH bpf-next 0/4] RV64 BPF JIT Optimizations

correctness using Serval. Luke Nelson (4): bpf, riscv: Enable missing verifier_zext optimizations on RV64 bpf, riscv: Optimize FROM_LE using verifier_zext on RV64 bpf, riscv: Optimize BPF_JMP BPF_K when imm == 0 on RV64 bpf, riscv: Optimize BPF_JSET BPF_K using andi on RV64 arch/riscv/net

[PATCH bpf-next 3/4] bpf, riscv: Optimize BPF_JMP BPF_K when imm == 0 on RV64

Signed-off-by: Luke Nelson --- arch/riscv/net/bpf_jit_comp64.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c index c3ce9a911b66..b07cef952019 100644 --- a/arch/riscv/net/bpf_jit_comp64.c

[PATCH bpf-next 4/4] bpf, riscv: Optimize BPF_JSET BPF_K using andi on RV64

equivalent and therefore the JIT produces identical code for them. Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson --- arch/riscv/net/bpf_jit_comp64.c | 27 +++ 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/arch/riscv/net

[PATCH bpf-next 1/4] bpf, riscv: Enable missing verifier_zext optimizations on RV64

F_LSH BPF_X and BPF_{LSH,RSH,ARSH} BPF_K are still missing the optimization. This patch enables the zero-extension optimization for these remaining cases. Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson --- arch/riscv/net/bpf_jit_comp64.c | 8 1 file changed

[PATCH bpf 0/2] bpf, arm: Small JIT optimizations

/20200408181229.10909-1-luke.r.n...@gmail.com/ [2] https://lore.kernel.org/bpf/20200409221752.28448-1-luke.r.n...@gmail.com/ Luke Nelson (2): bpf, arm: Optimize emit_a32_arsh_r64 using conditional instruction bpf, arm: Optimize ALU ARSH K using asr immediate instruction arch/arm/net/bpf_jit_32

[PATCH bpf-next 2/2] bpf, arm: Optimize ALU ARSH K using asr immediate instruction

-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson --- arch/arm/net/bpf_jit_32.c | 10 +++--- arch/arm/net/bpf_jit_32.h | 3 +++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index 48b89211ee5c

[PATCH bpf-next 1/2] bpf, arm: Optimize ALU64 ARSH X using orrpl conditional instruction

QEMU using lib/test_bpf and test_verifier. Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson --- arch/arm/net/bpf_jit_32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index bf85d6db4931

[PATCH bpf-next] bpf, riscv: Fix stack layout of JITed code on RV32

diagram of the stack layout. Tested on riscv32 QEMU virt machine. Signed-off-by: Luke Nelson --- arch/riscv/net/bpf_jit_comp32.c | 98 ++--- 1 file changed, 65 insertions(+), 33 deletions(-) diff --git a/arch/riscv/net/bpf_jit_comp32.c b/arch/riscv/net/bpf_jit_comp32.c