On Mon, Dec 18, 2017 at 07:21:30PM +0800, Greentime Hu wrote:
> Hi, Guo Ren:
>
> 2017-12-18 17:08 GMT+08:00 Guo Ren :
> > Hi Greentime,
> >
> > On Fri, Dec 08, 2017 at 05:11:50PM +0800, Greentime Hu wrote:
> > [...]
> >>
> >> diff --git
1 = kmap(page1) // Mostly vaddr1 = vaddr0
val = vaddr1; //No tlb-miss and it will get page0's val not page1, because
last expired vaddr0's entry is left in CPU-MMU-tlb.
Best Regards
Guo Ren
s in a invalid state, no operation happen on
tlbop_rwr.
Then they are atomic safe ,no spin_lock_irq need.
:)
Guo Ren
On Wed, Dec 13, 2017 at 04:30:41PM +0800, Greentime Hu wrote:
> 2017-12-13 16:19 GMT+08:00 Guo Ren :
> > On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote:
> >
> >> I think it should be fine if an interruption between mtsr_dsb and
> >> tlbop_rwr bec
On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote:
> I think it should be fine if an interruption between mtsr_dsb and
> tlbop_rwr because this is a optimization by sw.
Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will
break that vaddr's pfn in the CPU tlb-bu
t; and "tlbop_rwr" and a
update_mmu_cache() is invoked again, then an error page mapping is
set up in your tlb-buffer when tlbop_rwr is excuted from interrupt.
Because it's another addr in NDS32_SR_TLB_VPN.
It seems that tlb-hardrefill can help build tlb-buffer mapping, why you
update it in this software way?
Guo Ren
