Hi Tom,
we use OUT_CS_REG_SEQ for updating registers which are next to each other.
It saves CS space.
BEGIN_CS(6);
OUT_CS_REG(reg, a1);
OUT_CS_REG(reg + 4, a2);
OUT_CS_REG(reg + 8, a3);
END_CS;
can be rewritten to
BEGIN_CS(4);
OUT_CS_REQ_SEQ(reg, 3); // auto-increment reg on a register write.
O
Hi,
The two attached patches enable the hardware loop capabilities for
vertex shaders. I haven't tested on an r300 card yet, but glsl-vs-loop
from piglit passes on my r500 card. Nested loops don't work yet, I
think it is an issue with the branch emulation, but I'm not sure.
It would be helpful
