"Rogovin, Kevin" writes:
> Hello,
>
> Thank you for the very fast answers, some more questions:
>
>
>> It's not a preference question. The registers are 8 floats wide.
>> Vertex shaders get invoked 2 vertices at a time, with a register
>> containing these values:
>>
>> . +--+--+--
On 17 September 2013 05:13, Rogovin, Kevin wrote:
> Hello,
>
> Thank you for the very fast answers, some more questions:
>
>
> > It's not a preference question. The registers are 8 floats wide.
> > Vertex shaders get invoked 2 vertices at a time, with a register
> containing these values:
> >
>
On 09/17/2013 05:13 AM, Rogovin, Kevin wrote:
> Hello,
>
> Thank you for the very fast answers, some more questions:
>
>
>> It's not a preference question. The registers are 8 floats wide.
>> Vertex shaders get invoked 2 vertices at a time, with a register containing
>> these values:
>>
>> .
Hello,
Thank you for the very fast answers, some more questions:
> It's not a preference question. The registers are 8 floats wide.
> Vertex shaders get invoked 2 vertices at a time, with a register containing
> these values:
>
> . +--+--+--+--+--+--+--+--+
>
"Rogovin, Kevin" writes:
> Hello all,
>
> I am new to Mesa development (and in particular the i965 driver). I am
> currently trying to gain an understanding of Mesa's implementation
> with mostly an eye on (just) the i965 driver. Some questions:
>
> There are some docs in docs, how up to date are
Hello all,
I am new to Mesa development (and in particular the i965 driver). I am
currently trying to gain an understanding of Mesa's implementation with mostly
an eye on (just) the i965 driver. Some questions:
There are some docs in docs, how up to date are those documents? In particular
I sa
