On 07/03/17 22:39, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 04/03/17 01:44, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
From: Matt Turner
In commit c35fa7a, we changed the "width" of DF source registers to 2,
which is conceptu
Samuel Iglesias Gonsálvez writes:
> On 04/03/17 01:44, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>>> From: Matt Turner
>>>
>>> In commit c35fa7a, we changed the "width" of DF source registers to 2,
>>> which is conceptually fine. Unfortunately a VertStride of 2 is not
>>>
On Tue, Mar 7, 2017 at 5:11 AM, Samuel Iglesias Gonsálvez
wrote:
>
>
> On 04/03/17 01:44, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>>> From: Matt Turner
>>>
>>> In commit c35fa7a, we changed the "width" of DF source registers to 2,
>>> which is conceptually fine. Unfortunat
On 04/03/17 01:44, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> From: Matt Turner
>>
>> In commit c35fa7a, we changed the "width" of DF source registers to 2,
>> which is conceptually fine. Unfortunately a VertStride of 2 is not
>> allowed by align16 instructions on IVB/BYT,
Samuel Iglesias Gonsálvez writes:
> From: Matt Turner
>
> In commit c35fa7a, we changed the "width" of DF source registers to 2,
> which is conceptually fine. Unfortunately a VertStride of 2 is not
> allowed by align16 instructions on IVB/BYT, and the regular VertStride
> of 4 works fine in any
From: Matt Turner
In commit c35fa7a, we changed the "width" of DF source registers to 2,
which is conceptually fine. Unfortunately a VertStride of 2 is not
allowed by align16 instructions on IVB/BYT, and the regular VertStride
of 4 works fine in any case.
See
generated_tests/spec/arb_gpu_shader
