Re: [Mesa-dev] [PATCH v2 3/4] i965/gen10: Enable float blend optimization

2017-11-03 Thread Nanley Chery
On Fri, Nov 03, 2017 at 11:50:44AM -0700, Anuj Phogat wrote: > On Fri, Nov 3, 2017 at 11:05 AM, Nanley Chery wrote: > > On Fri, Nov 03, 2017 at 09:46:29AM -0700, Nanley Chery wrote: > >> On Wed, Nov 01, 2017 at 03:50:54PM -0700, Anuj Phogat wrote: > >> > This optimization is enabled for previous g

Re: [Mesa-dev] [PATCH v2 3/4] i965/gen10: Enable float blend optimization

2017-11-03 Thread Anuj Phogat
On Fri, Nov 3, 2017 at 11:05 AM, Nanley Chery wrote: > On Fri, Nov 03, 2017 at 09:46:29AM -0700, Nanley Chery wrote: >> On Wed, Nov 01, 2017 at 03:50:54PM -0700, Anuj Phogat wrote: >> > This optimization is enabled for previous generations too. >> > See Mesa commit c17e214a6b >> > On CNL this bit

Re: [Mesa-dev] [PATCH v2 3/4] i965/gen10: Enable float blend optimization

2017-11-03 Thread Nanley Chery
On Fri, Nov 03, 2017 at 11:39:34AM -0700, Anuj Phogat wrote: > On Fri, Nov 3, 2017 at 9:46 AM, Nanley Chery wrote: > > On Wed, Nov 01, 2017 at 03:50:54PM -0700, Anuj Phogat wrote: > >> This optimization is enabled for previous generations too. > >> See Mesa commit c17e214a6b > >> On CNL this bit h

Re: [Mesa-dev] [PATCH v2 3/4] i965/gen10: Enable float blend optimization

2017-11-03 Thread Anuj Phogat
On Fri, Nov 3, 2017 at 9:46 AM, Nanley Chery wrote: > On Wed, Nov 01, 2017 at 03:50:54PM -0700, Anuj Phogat wrote: >> This optimization is enabled for previous generations too. >> See Mesa commit c17e214a6b >> On CNL this bit has been moved to CACHE_MODE_SS register. >> >> Cc: Nanley Chery >> Sig

Re: [Mesa-dev] [PATCH v2 3/4] i965/gen10: Enable float blend optimization

2017-11-03 Thread Nanley Chery
On Fri, Nov 03, 2017 at 09:46:29AM -0700, Nanley Chery wrote: > On Wed, Nov 01, 2017 at 03:50:54PM -0700, Anuj Phogat wrote: > > This optimization is enabled for previous generations too. > > See Mesa commit c17e214a6b > > On CNL this bit has been moved to CACHE_MODE_SS register. > > > > Cc: Nanle

Re: [Mesa-dev] [PATCH v2 3/4] i965/gen10: Enable float blend optimization

2017-11-03 Thread Nanley Chery
On Wed, Nov 01, 2017 at 03:50:54PM -0700, Anuj Phogat wrote: > This optimization is enabled for previous generations too. > See Mesa commit c17e214a6b > On CNL this bit has been moved to CACHE_MODE_SS register. > > Cc: Nanley Chery > Signed-off-by: Anuj Phogat > --- > src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH v2 3/4] i965/gen10: Enable float blend optimization

2017-11-01 Thread Anuj Phogat
This optimization is enabled for previous generations too. See Mesa commit c17e214a6b On CNL this bit has been moved to CACHE_MODE_SS register. Cc: Nanley Chery Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_defines.h | 3 +++ src/mesa/drivers/dri/i965/brw_state_upload.c | 6