On 09.11.2017 18:37, Jan Vesely wrote:
On Thu, 2017-11-09 at 09:13 +0100, Nicolai Hähnle wrote:
The internal docs are pretty much the same (i.e. confusing and
non-explicit), but my layman's reading of the RTL is that DX10_CLAMP
only affects clamping. So if you have a
v_mul_f32 0, inf
This
On Thu, 2017-11-09 at 09:13 +0100, Nicolai Hähnle wrote:
> The internal docs are pretty much the same (i.e. confusing and
> non-explicit), but my layman's reading of the RTL is that DX10_CLAMP
> only affects clamping. So if you have a
>
>v_mul_f32 0, inf
This is a GCN instruction. does it a
The internal docs are pretty much the same (i.e. confusing and
non-explicit), but my layman's reading of the RTL is that DX10_CLAMP
only affects clamping. So if you have a
v_mul_f32 0, inf
that will generate a NaN just fine and is simply unaffected by
DX10_CLAMP. However, if the clamp bit i
FWIW I'd really appreciate it if someone could shed some light on that
mystery bit there...
Roland
Am 09.11.2017 um 03:58 schrieb srol...@vmware.com:
> From: Roland Scheidegger
>
> I don't know what this bit really does. The docs are somewhere between
> misleading and wrong however, as at least
From: Roland Scheidegger
I don't know what this bit really does. The docs are somewhere between
misleading and wrong however, as at least the newer ones (that bit exists with
GCN as well) imply all NaNs would get converted to zeros, which is definitely
NOT the case (and that would not be dx10 com
