Francisco Jerez writes:
> This is not a real IR in the sense of a long-lived representation of
> the program. An SVEC4 instruction, defined as an opcode operating on
> 4-vectors of FS registers, is broken up into its scalar components
> (each an fs_inst) as soon as it's emitted. The svec4_inst
This is not a real IR in the sense of a long-lived representation of
the program. An SVEC4 instruction, defined as an opcode operating on
4-vectors of FS registers, is broken up into its scalar components
(each an fs_inst) as soon as it's emitted. The svec4_inst object is a
convenient way to carr
