[Mesa-dev] [PATCH 09/18] radeon/vcn: add encode header algorithms

2017-11-08 Thread boyuan.zhang
From: Boyuan Zhang Since bitstream headers, e.g. sps, pps, slice, are encoded in driver side, we need to add corresponding algorithms that required to generate those headers. According to h.264 specs, signed/unsigned interger Exp-Golomb-coded syntax element with left bit first (code_se and code_u

Re: [Mesa-dev] [PATCH 09/18] radeon/vcn: add encode header algorithms

2017-11-07 Thread Alex Deucher
On Tue, Nov 7, 2017 at 4:59 PM, wrote: > From: Boyuan Zhang Better patch description please. What are these for? Please provide a brief overview. > > Signed-off-by: Boyuan Zhang > --- > src/gallium/drivers/radeon/radeon_vcn_enc.h | 6 ++ > src/gallium/drivers/radeon/radeon_vcn_enc_1_

[Mesa-dev] [PATCH 09/18] radeon/vcn: add encode header algorithms

2017-11-07 Thread boyuan.zhang
From: Boyuan Zhang Signed-off-by: Boyuan Zhang --- src/gallium/drivers/radeon/radeon_vcn_enc.h | 6 ++ src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 121 2 files changed, 127 insertions(+) diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.h b/src/galliu